CN111612881B - Multithreading rendering method and system for multilayer integrated circuit graphics and electronic equipment - Google Patents
Multithreading rendering method and system for multilayer integrated circuit graphics and electronic equipment Download PDFInfo
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- CN111612881B CN111612881B CN201910136436.6A CN201910136436A CN111612881B CN 111612881 B CN111612881 B CN 111612881B CN 201910136436 A CN201910136436 A CN 201910136436A CN 111612881 B CN111612881 B CN 111612881B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
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Abstract
The invention provides a multi-thread rendering method, a system and electronic equipment for multi-layer integrated circuit graphics, which are used for rendering the integrated circuit graphics with a plurality of layers.
Description
[ field of technology ]
The present invention relates to the field of integrated circuit image processing, and in particular, to a multithreading rendering method, system and electronic device for multi-layer integrated circuit graphics.
[ background Art ]
In modern society, a method for converting three-dimensional data into a two-dimensional image visible on a screen by using an image rendering technology is widely applied to various electronic devices.
The image rendering is to convert the obtained three-dimensional coordinate data of the object into two-dimensional coordinate data and display the two-dimensional coordinate data based on display coordinates, thereby obtaining a two-dimensional display with a three-dimensional scene.
The integrated circuit image is generally formed by stacking a plurality of layers, each layer is used for completing a specific function, the rendering of the integrated circuit image comprises the rendering of graphics in the plurality of layers, but in the existing integrated circuit image rendering method, the rendering of one image is usually single-thread rendering, and the rendering mode is insufficient in thread utilization rate of a computer processor, so that the rendering efficiency is lower.
[ invention ]
In order to solve the problem of lower rendering efficiency in the existing image rendering method, the invention provides a multi-thread rendering method of a multi-layer integrated circuit graph.
The invention provides a technical scheme for solving the technical problems as follows: a multi-threaded rendering method of a multi-layered integrated circuit graphic, comprising the steps of: step S1: moving the display area to a region to be rendered, wherein the region to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of a data set in a known data set; step S2: dividing an image to be rendered in a display area into a plurality of sub-areas so as to divide the image to be rendered into a plurality of sub-images; step S3: allocating a first thread to each sub-region correspondingly, and allocating a second thread matched with each layer in the corresponding sub-image to each first thread; step S4: each second thread utilizes the marks of the images to be rendered to match corresponding rendering graphics with the same marks in a part of data sets, and renders all rendering graphics in the sub-images to obtain rendering graphics of the sub-images; step S5: and rendering the rendering graphs of all the sub-images by the plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
Preferably, the partial data set is a tree data structure comprising a root node and a plurality of leaf nodes corresponding to the root node based on indexes, and the partial data set contains all rendering graphics required for rendering the image to be rendered; the step S4 specifically includes the following steps: step S41: the second thread matches the mark of the image to be rendered with the rendering graph with the same mark in the root node by utilizing the part of data set, and the rendering graph of the root node is obtained; step S42: entering a corresponding leaf node from the root node based on the index of the root node, and matching the corresponding leaf node with the rendering graph with the same mark by using the mark of the image to be rendered to obtain the rendering graph in the leaf node; step S43: and continuing to enter a corresponding next-stage leaf node from the leaf node based on the new index to match, so as to obtain a rendering graph in the next-stage leaf node, and obtaining a plurality of rendering graphs in the multi-stage leaf node until all leaf nodes corresponding to the index are matched.
Preferably, in step S4, the plurality of second threads render in parallel, and a rendering result of all layers in the sub-image is obtained.
Preferably, the step S5 specifically includes the following steps: step S51: all the rendering graphics of the plurality of sub-images are rendered by the plurality of first threads in parallel, and a rendering graph with local coordinates of the image to be rendered is obtained; step S52: the local coordinates of the rendered map are converted to display coordinates to display the final rendered map in the rendering area.
Preferably, a plurality of the sub-regions are sub-regions of equal area.
Preferably, before step S1, the method further comprises the step S0 of: and cutting out the area outside the image to be rendered in the display area so as to cut out all data outside the range of the image to be rendered.
The present invention also provides a multi-threaded rendering system for multi-layer integrated circuit graphics, comprising: the region selection unit is used for moving the display region to a region to be rendered, wherein the region to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of data sets in the known data sets; the region dividing unit is used for dividing the image to be rendered in the display region into a plurality of sub-regions so as to divide the image to be rendered into a plurality of sub-images; a thread allocation unit, each sub-region is allocated with a first thread correspondingly, and each first thread is allocated with a second thread matched with each layer in the corresponding sub-image; the image rendering unit is used for matching the marks of the images to be rendered in the partial data set by each second thread with corresponding rendering graphics with the same marks, rendering all the rendering graphics in the sub-images, and obtaining rendering graphics of the sub-images; and the imaging unit is used for rendering the rendering graphs of all the sub-images through a plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
Preferably, the method further comprises: and the cutting unit is used for cutting the rendering area outside the required rendering graphic range so as to cut all data outside the required rendering graphic range.
Preferably, the graphic rendering unit further comprises: the first node matching unit is used for matching the second thread with the rendering graph with the same mark in the root node by using the mark of the image to be rendered and part of data set to obtain the rendering graph of the root node; the second node matching unit is used for entering the corresponding leaf node from the root node based on the index of the root node, and matching the corresponding leaf node with the rendering graph with the same mark by utilizing the mark of the image to be rendered to obtain the rendering graph in the leaf node; and the matching cut-off unit is used for continuing to enter the corresponding next-stage leaf node from the leaf node based on the new index to perform matching, so as to obtain the rendering graph in the next-stage leaf node, and obtaining a plurality of rendering graphs in the multi-stage leaf node until all the leaf nodes corresponding to the index are matched.
The invention also provides an electronic device comprising a memory and a processor, characterized in that: the memory having stored therein a computer program configured to perform the multi-threaded rendering method of a multi-layered integrated circuit graphic described in any one of the above when run; the processor is arranged to perform a multi-threaded rendering method of the multi-layered integrated circuit graphics described in any one of the above by means of the computer program.
Compared with the prior art, the multithreading rendering method of the multilayer integrated circuit graph has the following advantages:
the method comprises the steps of dividing one image to be rendered into a plurality of sub-images, distributing a first thread to each sub-image, distributing a corresponding number of second threads to the layer number of each sub-image, so that multi-thread rendering of each image and the graphics of a plurality of layers in each image is realized, the rendering efficiency is improved, and the rendering time is reduced.
By cutting the area outside the image to be rendered in the display area before dividing the image to be rendered, all data beyond the range of the image to be rendered is cut off, so that the calculated amount of rendering is reduced, and the rendering efficiency is improved.
The plurality of subregions divided by the display region are subregions with equal areas, so that the calculated amount of each first thread is more balanced during rendering, and the utilization rate of the threads is improved.
By utilizing the tree-shaped data structure of the known data set, traversing the tree-shaped data structure of the known data set according to the mark of the image to be rendered, all the rendering graphics of the image to be rendered are obtained, and the rendering efficiency and the rendering accuracy of the graphics rendering are improved.
The local coordinates of the rendering graph are converted into display coordinates so as to display the final rendering graph in the rendering area, so that the rendering graph is displayed in the correct position of the display area through the converted display coordinates after the rendering graph is rendered.
[ description of the drawings ]
FIG. 1a is a flowchart illustrating a multi-threaded rendering method for multi-layered integrated circuit graphics according to a first embodiment of the present invention;
FIG. 1b is a schematic diagram of a tree data structure of a known data set in a multi-threaded rendering method of a multi-layered integrated circuit graphics according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a multi-threaded rendering method of a multi-layered integrated circuit according to a first embodiment of the present invention;
FIG. 3 is a detailed flowchart of step S4 of a multi-threaded rendering method of multi-layered integrated circuit graphics according to a first embodiment of the present invention;
FIG. 4 is a detailed flowchart of step S5 of a multi-threaded rendering method of multi-layered integrated circuit graphics according to a first embodiment of the present invention;
FIG. 5 is a block diagram of a multi-threaded rendering system for multi-layered integrated circuit graphics provided in accordance with a second embodiment of the present invention;
FIG. 6 is a block diagram of a graphics rendering unit in a multi-threaded rendering system for multi-layered integrated circuit graphics according to a second embodiment of the present invention;
fig. 7 is a block diagram of an electronic device according to a third embodiment of the present invention.
Reference numerals illustrate:
1. a region selection unit; 2. a region dividing unit; 3. a thread allocation unit; 4. a graphics rendering unit; 5. an imaging unit; 6. a cutting unit;
10. a memory; 20. a processor;
41. a first node matching unit; 42. a second node matching unit; 43. a matching cut-off unit;
100. a display area; 200. a sub-region; 300. a root node; 400. leaf nodes; 500. and (5) indexing.
[ detailed description ] of the invention
For the purpose of making the technical solution and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples of implementation. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1a, a first embodiment of the present invention provides a multi-threaded rendering method of multi-layered integrated circuit graphics for rendering integrated circuit graphics having multiple layers. It will be appreciated that in integrated circuit patterns, it is common to have multiple layers of circuitry superimposed, each composed of a different pattern.
The multi-thread rendering method of the multi-layer integrated circuit graph is used for rendering an image to be rendered in a display area, wherein the image to be rendered is the integrated circuit graph with a plurality of layers, and specifically comprises the following steps of:
step S1: moving the display area to a region to be rendered, wherein the region to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of a data set in a known data set;
it may be understood that the known data set includes a plurality of geometric shapes of the whole integrated circuit graph and marks corresponding to the geometric shapes, the known data set is a tree-shaped data structure including a root node and a plurality of leaf nodes corresponding to the root node based on indexes, the root node and the leaf nodes include the geometric shapes, any root node or leaf node includes the geometric shapes, and since the image to be rendered in the whole area to be rendered is a partial image of the whole integrated circuit graph, only the partial data set corresponding to the image to be rendered in the known data set needs to be rendered. As shown in fig. 1b, taking the root node 300 and leaf node 400 shown in fig. 1b as an example, and taking only a 3-level tree structure as an example in fig. 1b, in other embodiments, the tree data structure may be multi-level. This example is merely illustrative of the invention and is not meant to be limiting. A root node 300 is connected to a plurality of (or one) leaf nodes 400 through the root node's index 500, and the plurality of leaf nodes 400 continue to enter the next level of leaf nodes 400 through the new index 500, thereby forming a dataset having a 3-level tree data structure.
It will be appreciated that the partial data set is a partial tree data structure of the tree data structures of the known data set, which contains all rendering graphics within the image to be rendered.
It will be appreciated that the label of the image to be rendered is a label of all rendered graphics within the image to be rendered, which label is present in each root node and leaf node of the known data set and the partial data set. The mark of the image to be rendered is unique information which is different from other images, and can be a serial number or a code which randomly compiles rules. The rendering graphics corresponding to the marks of the image to be rendered in each root node and each leaf node are different.
With continued reference to fig. 1a, the multi-threaded rendering method of the multi-layered integrated circuit graphics further includes:
step S2: dividing the display area into a plurality of sub-areas to divide the image to be rendered into a plurality of sub-images;
in some other embodiments, the display area may also be a combination of a plurality of equal area sub-areas.
It will be appreciated that for convenience of explanation, in the present invention, the display area is divided into 3×3 sub-areas as an example, but this is merely illustrative of the present invention and not limiting of the present invention.
Step S3: allocating a first thread to each sub-region correspondingly, and allocating a second thread matched with each layer in the corresponding sub-image to each first thread;
for example, a 3 x 3 sub-region is allocated 9 first threads, each of which corresponds one-to-one to the sub-region. In each sub-region, the first thread allocates a corresponding number of second threads according to the number of layers included in the sub-image corresponding to the sub-region, for example, if 9 layers of graphics are included in the sub-image corresponding to one sub-region, 9 second threads are allocated, and each second thread is matched with each layer.
Step S4: each second thread utilizes the marks of the images to be rendered to match corresponding rendering graphics with the same marks in a part of data sets, and renders all rendering graphics in the sub-images to obtain rendering graphics of the sub-images;
it can be understood that the rendering graphics with the same mark corresponding to the mark of the image to be rendered are matched in the partial data set one by one through matching in a plurality of root nodes and leaf nodes on a tree data structure of the partial data set, and each node (root node or leaf node) contains a plurality of different rendering graphics with the same mark, the second thread correspondingly obtains a plurality of rendering graphics with the same mark after matching in each node (root node or leaf node) by using the mark of the image to be rendered, and when traversing the tree data structure of the whole partial data set, all rendering graphics in the sub-image corresponding to each second thread are obtained.
Step S5: and rendering the rendering graphs of all the sub-images by the plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
In some other embodiments, before step S1, further comprising:
step S0: and cutting out the area outside the image to be rendered in the display area so as to cut out all data outside the range of the image to be rendered.
It can be understood that before the image to be rendered is rendered, the image to be rendered needs to be subjected to visibility judgment, that is, the image to be rendered is not completely composed of the required rendering graphics, and the image to be rendered also comprises background features irrelevant to the image to be rendered within an allowable error range, so that the irrelevant background features are cut, the calculated amount of rendering is reduced, and the rendering efficiency is improved.
Referring to fig. 2, step S2: the image to be rendered in the display area is divided into a plurality of sub-areas to divide the image to be rendered into a plurality of sub-images. For example, as shown in fig. 2, 9 sub-areas 200 on the display area 100 are divided into 3×3 specifications, and when an image to be rendered is displayed on the display area 100, it is displayed within a plurality of sub-areas 200 according to the 3×3 specifications.
It can be understood that the image to be rendered is divided into a plurality of sub-areas, so that the image to be rendered is divided into a plurality of sub-images, so that the plurality of sub-images can be rendered in parallel through multithreading in a subsequent step, and the rendering efficiency is improved.
Referring to fig. 3, step S4: and each second thread utilizes the marks of the images to be rendered to match corresponding rendering graphics with the same marks in a part of data sets, renders all rendering graphics in the sub-images, and obtains rendering graphics of the sub-images. Step S4 specifically includes steps S41 to S43, and it is understood that steps S41 to S43 are only one implementation of this example, and implementation thereof is not limited to steps S41 to S43, as shown in fig. 3, and the step flow is as follows:
step S41: the second thread matches the mark of the image to be rendered with the rendering graph with the same mark in the root node by utilizing the part of data set, and the rendering graph of the root node is obtained;
step S42: entering a corresponding leaf node from the root node based on the index of the root node, and matching the corresponding leaf node with the rendering graph with the same mark by using the mark of the image to be rendered to obtain the rendering graph in the leaf node;
step S43: continuing to enter a corresponding next-stage leaf node from the leaf node based on the new index to match, and obtaining a rendering graph in the next-stage leaf node; and obtaining a plurality of rendering graphs in the multi-stage leaf nodes until all leaf nodes corresponding to the indexes are matched.
It can be understood that the obtained rendering graphic is a graphic formed by rendering the vertex coordinates of the graphic and connecting the vertex coordinates according to the connection relationship of the rendering graphic in the rendering process.
Referring to fig. 4, step S5: and rendering the rendering graphs of all the sub-images by the plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs. Step S5 specifically includes steps S51 to S52, and it is understood that steps S51 to S52 are only one implementation of this example, and implementation thereof is not limited to steps S51 to S52, as shown in fig. 4, and the step flow is as follows:
step S51: all the rendering graphics of the plurality of sub-images are rendered by the plurality of first threads in parallel, and a rendering graph with local coordinates of the image to be rendered is obtained;
step S52: the local coordinates of the rendered map are converted to display coordinates to display the final rendered map in the rendering area.
It can be understood that in image rendering, all graphics in the obtained rendering image of the image to be rendered include conversion of various coordinate systems in the rendering process, so as to convert three-dimensional image data into two-dimensional data of graphics displayed on a two-dimensional screen, and in the rendering process, the coordinates of the obtained rendering image are local coordinates, and the rendering image needs to be displayed on a correct position of the display area by converting the local coordinates of the rendering image into display coordinates.
Referring to fig. 5, a second embodiment of the present invention provides a multi-threaded rendering system for multi-layered integrated circuit graphics. The multi-threaded rendering system includes: a region selection unit 1, a region division unit 2, a thread allocation unit 3, a graphics rendering unit 4, and an imaging unit 5.
The area selection unit 1 is used for moving the display area to the area to be rendered, wherein the area to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of data sets in the known data sets;
a region dividing unit 2 for dividing an image to be rendered in the display region into a plurality of sub-regions to divide the image to be rendered into a plurality of sub-images;
a thread allocation unit 3, each sub-region is allocated with a first thread correspondingly, and each first thread is allocated with a second thread matched with each layer in the corresponding sub-image;
a graphics rendering unit 4, configured to match, in a partial dataset, the marks of the image to be rendered with corresponding rendering graphics having the same marks by using each of the second threads, render all rendering graphics in the sub-image, and obtain a rendering image of the sub-image; a kind of electronic device with high-pressure air-conditioning system
And the imaging unit 5 is used for rendering the rendering graphs of all the sub-images through a plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
Referring to fig. 6, the graphics rendering unit 4 further includes a first node matching unit 41, a second node matching unit 42, and a matching cut-off unit 43.
A first node matching unit 41, configured to match the second thread with a rendering pattern with the same mark in the root node by using the mark of the image to be rendered and a part of the data set, so as to obtain a rendering pattern of the root node;
a second node matching unit 42, configured to enter a corresponding leaf node from the root node based on the index of the root node, and match, with the rendering graphics having the same mark in the corresponding leaf node, using the mark of the image to be rendered, to obtain the rendering graphics in the leaf node;
and the matching cut-off unit 43 is configured to continue to enter the corresponding next-stage leaf node from the leaf node based on the new index to perform matching, obtain the rendering graphics in the next-stage leaf node, and obtain multiple rendering graphics in the multi-stage leaf node until all the leaf nodes corresponding to the index are matched.
Optionally, the multi-threaded rendering system of the multi-layered integrated circuit graphics further comprises a clipping unit 6 for clipping the rendering area outside the required rendering graphics range to clip out all data outside the required rendering graphics range.
Referring to fig. 6, a third embodiment of the present invention provides an electronic device comprising a memory 10 and a processor 20, the memory 10 having stored therein a computer program arranged to perform, when run, the steps of a multi-threaded rendering method embodiment of the multi-layered integrated circuit graphics of any of the above.
The processor 20 is arranged to perform the steps of the multi-threaded rendering method embodiment of the multi-layered integrated circuit graphics of any of the above by means of the computer program.
Alternatively, in this embodiment, the electronic device may be located in at least one network device of a plurality of network devices of the computing machine network.
Specifically, the electronic device is an image rendering device applied to the field of image rendering, and is used for performing multi-thread rendering on an image so as to improve the rendering efficiency.
Specifically, the electronic device may also be applied to the field of computer rendering of integrated circuit graphics, and is used for rendering photomask graphics data, so as to improve the rendering efficiency of the photomask graphics and reduce the rendering time.
Compared with the prior art, the multithreading rendering method of the multilayer integrated circuit graph has the following advantages:
the method comprises the steps of dividing one image to be rendered into a plurality of sub-images, distributing a first thread to each sub-image, distributing a corresponding number of second threads to the layer number of each sub-image, so that multi-thread rendering of each image and the graphics of a plurality of layers in each image is realized, the rendering efficiency is improved, and the rendering time is reduced.
By cutting the area outside the image to be rendered in the display area before dividing the image to be rendered, all data beyond the range of the image to be rendered is cut off, so that the calculated amount of rendering is reduced, and the rendering efficiency is improved.
The plurality of subregions divided by the display region are subregions with equal areas, so that the calculated amount of each first thread is more balanced during rendering, and the utilization rate of the threads is improved.
By utilizing the tree-shaped data structure of the known data set, traversing the tree-shaped data structure of the known data set according to the mark of the image to be rendered, all the rendering graphics of the image to be rendered are obtained, and the rendering efficiency and the rendering accuracy of the graphics rendering are improved.
The local coordinates of the rendering graph are converted into display coordinates so as to display the final rendering graph in the rendering area, so that the rendering graph is displayed in the correct position of the display area through the converted display coordinates after the rendering graph is rendered.
The above-described functions defined in the method of the present application are performed when the computer program is executed by a processor. It should be noted that, the computer memory described in the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer memory may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing.
More specific examples of computer memory may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable signal medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present application may be implemented by software, or may be implemented by hardware. The described units may also be provided in a processor, for example, described as: a processor includes a region dividing unit, a thread allocating unit, a graphics rendering unit, and an imaging unit. The names of these units do not constitute a limitation on the unit itself in some cases, and for example, a graphics rendering unit may also be described as "acquire a unit with graphics to be rendered based on graphics data".
As another aspect, the present application also provides a computer memory, which may be included in the apparatus described in the above embodiments; or may be present alone without being fitted into the device. The computer memory carries one or more programs that, when executed by the apparatus, cause the apparatus to: the multi-line Cheng Xuanran is realized by dividing a to-be-rendered image into a plurality of subareas, distributing a first thread to each subarea, and distributing a corresponding number of second threads to the layer number of each subarea, so that each area and the graphics of a plurality of layers in each area are realized.
The above embodiments are merely preferred embodiments of the present invention, and are not intended to limit the present invention, but any modifications, equivalents, improvements, etc. within the principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A multi-threaded rendering method of a multi-layered integrated circuit graphic, comprising the steps of:
step S1: moving the display area to a region to be rendered, wherein the region to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of a data set in a known data set;
step S2: dividing an image to be rendered in a display area into a plurality of sub-areas so as to divide the image to be rendered into a plurality of sub-images;
step S3: allocating a first thread to each sub-region correspondingly, and allocating a second thread matched with each layer in the corresponding sub-image to each first thread;
step S4: each second thread utilizes the marks of the images to be rendered to match corresponding rendering graphics with the same marks in a part of data sets, and renders all rendering graphics in the sub-images to obtain rendering graphics of the sub-images; a kind of electronic device with high-pressure air-conditioning system
Step S5: and rendering the rendering graphs of all the sub-images by the plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
2. A multi-threaded rendering method of multi-layered integrated circuit graphics as recited in claim 1, wherein: the partial data set is a tree data structure comprising a root node and a plurality of leaf nodes corresponding to the root node based on indexes, and comprises all rendering graphics required by rendering operation on the image to be rendered;
the step S4 specifically includes the following steps:
step S41: the second thread matches the mark of the image to be rendered with the rendering graph with the same mark in the root node by utilizing the part of data set, and the rendering graph of the root node is obtained;
step S42: entering a corresponding leaf node from the root node based on the index of the root node, and matching the corresponding leaf node with the rendering graph with the same mark by using the mark of the image to be rendered to obtain the rendering graph in the leaf node;
step S43: and continuing to enter a corresponding next-stage leaf node from the leaf node based on the new index to match, so as to obtain a rendering graph in the next-stage leaf node, and obtaining a plurality of rendering graphs in the multi-stage leaf node until all leaf nodes corresponding to the index are matched.
3. A multi-threaded rendering method of multi-layered integrated circuit graphics as recited in claim 2, wherein: in step S4, the plurality of second threads render in parallel, and a rendering result of all layers in the sub-image is obtained.
4. A multi-threaded rendering method of multi-layered integrated circuit graphics as recited in claim 1, wherein: the step S5 specifically includes the following steps:
step S51: all the rendering graphics of the plurality of sub-images are rendered by the plurality of first threads in parallel, and a rendering graph with local coordinates of the image to be rendered is obtained;
step S52: the local coordinates of the rendered map are converted to display coordinates to display the final rendered map in the rendering area.
5. A multi-threaded rendering method of multi-layered integrated circuit graphics as recited in claim 1, wherein: the plurality of subareas are subareas with equal areas.
6. A multi-threaded rendering method of multi-layered integrated circuit graphics as recited in claim 1, wherein: before step S1, the method further includes:
step S0: and cutting out the area outside the image to be rendered in the display area so as to cut out all data outside the range of the image to be rendered.
7. A multi-threaded rendering system for multi-layer integrated circuit graphics, comprising:
the region selection unit is used for moving the display region to a region to be rendered, wherein the region to be rendered comprises an image to be rendered and a mark of the image to be rendered, and the image to be rendered corresponds to part of data sets in the known data sets;
the region dividing unit is used for dividing the image to be rendered in the display region into a plurality of sub-regions so as to divide the image to be rendered into a plurality of sub-images;
a thread allocation unit, each sub-region is allocated with a first thread correspondingly, and each first thread is allocated with a second thread matched with each layer in the corresponding sub-image;
the image rendering unit is used for matching the marks of the images to be rendered in the partial data set by each second thread with corresponding rendering graphics with the same marks, rendering all the rendering graphics in the sub-images, and obtaining rendering graphics of the sub-images; a kind of electronic device with high-pressure air-conditioning system
And the imaging unit is used for rendering the rendering graphs of all the sub-images through a plurality of first threads in parallel, and displaying rendering results on the corresponding positions of the rendering areas based on the rendering graphs.
8. A multi-threaded rendering system for multi-layer integrated circuit graphics as recited in claim 7, wherein: further comprises: and the cutting unit is used for cutting the rendering area outside the required rendering graphic range so as to cut all data outside the required rendering graphic range.
9. A multi-threaded rendering system for multi-layer integrated circuit graphics as recited in claim 7, wherein: the graphics rendering unit further includes:
the first node matching unit is used for matching the second thread with the rendering graph with the same mark in the root node by using the mark of the image to be rendered and part of data set to obtain the rendering graph of the root node;
the second node matching unit is used for entering the corresponding leaf node from the root node based on the index of the root node, and matching the corresponding leaf node with the rendering graph with the same mark by utilizing the mark of the image to be rendered to obtain the rendering graph in the leaf node;
and the matching cut-off unit is used for continuing to enter the corresponding next-stage leaf node from the leaf node based on the new index to perform matching, so as to obtain the rendering graph in the next-stage leaf node, and obtaining a plurality of rendering graphs in the multi-stage leaf node until all the leaf nodes corresponding to the index are matched.
10. An electronic device comprising a memory and a processor, characterized in that: a computer program stored in the memory, the computer program being arranged to perform the multi-threaded rendering method of a multi-layered integrated circuit graphic as claimed in any one of claims 1 to 6 when run;
the processor is arranged to execute a multi-threaded rendering method of the multi-layered integrated circuit graphics as claimed in any one of claims 1 to 6 by means of the computer program.
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