CN111610951A - MOS tube output editing transmission type multi-system and decimal bit-weight adder - Google Patents

Abstract

An output editing transmission type multi-system and decimal bit-weight adder of MOS tube composed of MOS tube, composed of different forms of multi-value addition module, the said multi-value addition module has output home position equal to 0 module, equal to 1 module, equal to 2 module … … equal to N module, the said module is composed of different connected arithmetic unit combination, the said unit is formed by arranging and combining the circuit of claim 3 of patent application 201711119713.x as unit; after each unit is selected according to carry system and added with two input addends, the units with same bit of sum value are arranged together to form operation modules with different scales, the grid electrode of each unit in the module forms a group of bit weight data input, the drain electrode of each unit in the module forms a group of bit weight data input, and the output of each fractal output carry 1 in the unit is connected together to be used as module carry output.

Description

MOS tube output editing transmission type multi-system and decimal bit-weight adder

Technical Field

The invention relates to the technical field of computers, in particular to an MOS tube output editing transmission type multi-system and decimal bit-weight adder which is one of basic hardware for realizing a multi-value computer "

Technical Field

In view of the fact that all computers and their related digital systems are binary, and the development is very slow because there is no key hardware supporting the multi-value calculation, and the implementation of the multi-value computer, especially the decimal computer, is almost zero, the present invention proposes a simple and effective method for implementing the multi-value calculation, especially the ten-value calculation, and a key circuit for implementing the arithmetic operation of adding, subtracting, multiplying and dividing the multi-value, especially the ten-value, and the logical operation thereof by using the binary hardware, which are called "quantization logic" and circuits thereof.

Disclosure of Invention

The quantization logic is a logic system which uses the mark information generated after the analog information quantization as an operator to perform logic operation, deduction and judgment

Simple understanding of quantization logic

The method of taking the mark value after continuous, fuzzy and chaos information quantization as the input and output to carry out logic operation is called quantization logic, the circuit for realizing the operation is called quantization logic circuit, and then the input front part of the quantization logic circuit is mostly quantizer or quantized weight line. The post output part is a quantization weight line or a quantization amplitude weight line.

The quantization logic uses the basic ideas of binary logic, multi-value logic and fuzzy logic, and uses a simple and effective binary orientation circuit to realize the key circuits of the multi-value and fuzzy logic, so that under the condition that a logic element is limited to two simple states, a multi-value and fuzzy logic operation circuit is also formed, and particularly, the problems of multi-value operation and register are fundamentally solved by a compatible operation and quantitative register method of the quantization logic, thereby opening up the updating future of new generation computing equipment. The operation method with a luxurious and various quantization logics can provide effective hardware support for the development of artificial intelligence.

Natural information is simulated and continuously changed, thinking can only generate cognition on object information with stable image and fixed attribute, and information which is not shaped and solidified cannot be recognized, so that a processing method for shaping and solidifying the simulated and continuously changed information is a basic method for priority of thinking operation.

Quantization is a method for processing information in analog-to-digital conversion, and comprises three steps of fixed point, sampling value and merging.

Quantization is also a method of thinking about processing information, and has three steps, demarcating, marking, aliasing

Quantification is also an expression of nature things gathering and distributing attributes, and any thing always shows its own attributes with characteristics different from other things, and the boundary is generated at the joint of the determined things with different attributes, and the expressions with different attributes form characteristics, and the extension of similar attributes is mixed into a whole.

Then we define: the method of analyzing and resolving things by using the comparative characteristics of the heterogeneous attributes and thoughts of things is called quantification. The operation method and the operation rule of the quantization thinking for the information of the real things are called quantization logic.

The main operation method of quantization is: multivariate quantization, multivalued quantization, multiple quantization

The basic rule of quantification is simple discretization, minimum stabilization, regular ordering and fixed point clearness of natural hundred-state information attributes to form a marking process with inclusion attributes with shallow meaning.

Quantization logic defines information as analog information, digital information. The digital information is defined as "amplitude right information" and "bit right information". The amplitude weight information is time-varying amplitude weight information, and the bit weight information is weight information of a spatially distributed position.

Wherein the definition of the analog information in the quantization logic:

the analog information consists of two parts, one is the presentation information, which is the amplitude weight information of successive time instants. The other is implicit information which is status information of 'existence' and 'nonexistence', the existence 'indicates that the information exists but no matter the amplitude value, the nonexistence' indicates that the information does not exist, and the nonexistence indicates that no information acts on the system.

Definition of digital information in quantization logic: digital information refers to information that is moderately quantized in quantization logic.

Definition of amplitude weight information in quantization logic:

the amplitude weight information is the information obtained by stepping the amplitude of analog information by a quantitative merging method, the merged ordered steps form a multi-valued digital sequence limited by a carry system, the value of each element in the sequence is an amplitude weight value, and the amplitude weight value is the expression information. The implicit information in the amplitude weight information is binary single-value information and is status information of 'presence' and 'absence', the 'presence' indicates that information is present but the amplitude weight value is not the same, the 'absence' indicates that no information is present, and the 'absence' indicates that no information acts on the system. The amplitude weight information is essentially the "dynamic weight value" information.

Definition of bit weight information in quantization logic:

the bit weight information is also composed of two parts, one is the representation information which is the only terminal with level output in the bit weight output line group, and the output and the information have mutually incompatible attributes. The second is implicit information, which is weight information determined by the spatial position of the level output line in the plurality of bit weight output lines. The bit weight information is two-state information but is binary one-valued logic information because of using two states of "present" and "absent", and the "absent" state indicates no connection (the same attribute as the disconnection of the switch). Further, none is different from a zero value, none is absent, there is no effect on the matter connected to the point, and zero is present, resulting in a zero effect on the matter connected to the point. This is the difference between zero effect and no effect. The actual weight information is "weight-containing value" information.

In brief, the following: in quantization logic, analog information, amplitude weight information and bit weight information all contain two kinds of information, namely, representation information and implicit information, one is 'weight' information, and the other is 'state' information. The "state" information has a logical attribute and the "weight" information has a metric attribute. In quantization logic, state operation and weight operation are separated, the state operation is logic operation, and the weight operation performs fractal numerical operation according to requirements and can also be used as multi-valued logic operation. When used as a logic operation, the weight operation has an operation relationship different from the conventional logic, such as: the logic operation relationship includes two structures of amplitude-weighted logic operation circuit and bit-weighted logic operation circuit. The conventional binary and logic is degenerated homonym and logic, and the binary or logic is degenerated homonym or logic.

The information obtained in the quantization logic using the "minimum orientation" rule is the "state" value information. The logical operation is only the minimum orientation operation and is the state value operation, so that only the logical operation of AND and OR is performed, and other operations are as follows: the operations of taking big, taking small, complementing, adding, subtracting, multiplying, dividing, comparing and the like are all 'weight' operations, the 'state' value logic operation judges the completeness of the operation condition, and the operation of the 'measurement' of the weight determines the operation values of various rule operations.

The quantization logic directly obtains the required information by taking 'quantization' as a means, the obtained information is directly converted into 'amplitude weight' or 'bit weight' digital information through a quantizer, the 'amplitude weight' or 'bit weight' digital information is convenient to operate and store, the amplitude weight information is favorable for transmission and exchange, and the bit weight information is favorable for operation and recording. The quantizer undertakes the conversion of the information.

In quantization logic, the conventional binary logic information is "two-weighted amplitude weight information". The quantization logic and the legacy logic are compatible with each other. The biggest difference between quantization logic and traditional logic is that logic state information and information weight value information are decomposed, the logic state information is basically the same as the traditional logic information, and the information weight value can break through binary limitation to realize multivalued operation. Meanwhile, the limitation that multi-value operation needs multi-value logic support can be broken through, and numerical operation and multi-value logic operation of any carry system can be realized in principle. All binary logic circuits can run quantized logic information, normally, a pull-down resistor needs to be connected to the input of each binary circuit, redundant logic values in the binary information are eliminated, and a single-value device with the same switching property is adopted in the aspect of output to prevent the redundant logic values from being output.

The key circuit for realizing quantization operation is a quantizer, the quantizer comprises an amplitude weight quantizer and a bit weight quantizer, the bit weight quantizer is a time-space conversion device for converting time information into space information, and the amplitude weight quantizer is a space-time conversion device for converting the space information into the time information. The spatial information characteristic is area distribution control information, and the temporal information characteristic is real-time random variation information.

The difference between the "bit right" information and the "amplitude right" information in circuit implementation is that the advantages of the "bit right" information are: the logic voltage requirement is simple, the logic swing can be made very small, so the requirement on device parameters is not high, the power consumption can be made very low, and the key points are clear state, high speed and extremely low error rate. However, the device consumption is large, the vacant resources are large, and the occupied space resources are large. The advantages of the "width right" information are: the device has the advantages of low consumption, few vacant resources and few occupied space resources, and the key points of the device are single-ended multivalued characteristics, high information content, higher requirements on device parameters, higher device working voltage and higher power consumption.

As can be seen from the basic features of quantization logic, quantization logic differs from conventional binary logic as follows:

1: the traditional binary logic is an integrated logic of logic state and information weight, and has no description of the state and the weight. The quantization logic separates the logic state from the information weight, so that the state value operation and the weight value operation are independent, and the digital multi-value operation by using the existing logic hardware is realized.

2: the traditional binary logic has no definition of amplitude weight and bit weight

The quantization logic divides the digital information into "amplitude weight information" and "bit weight information" and converts the information with a "quantizer".

3: the conventional view is that the analog information is time-continuous information and is raw information obtained naturally without processing.

The quantization logic considers that the analog information is continuous 'amplitude weight information', the 'amplitude weight information' contains amplitude weight information and state value logic information, and the logic state value information and the amplitude weight information can be separated.

4: the conventional view is that "switch" is a binary element, with on and off representing two logical values, respectively.

Quantization logic considers a "switch" to be a two-state, single-valued logic device because the "on and off" of a switch essentially consists of "connect" and "disconnect", where "connect" can be a logical value, but "disconnect" can only be a state and not a logical value. A state that is not associated with the system cannot be used as a logical value.

5: the basic idea of quantization logic does not conflict with the idea of conventional binary logic, which is one of quantization logic and is "binary amplitude weight" logic.

In quantization logic, the operation information has two types, namely amplitude weight information and bit weight information, the amplitude weight information is similar to the traditional binary information, but the value range is not limited to binary characteristics and tends to be multi-valued, obviously, the characteristic of the amplitude weight information is an optimal operation scheme in a binary state, if the selected value is too much, the stable space of the information amplitude is reduced, the external intrusion is easy to occur, and in addition, the influence of the internal operation environment of a device is added, so that the operation reliability of a circuit cannot be guaranteed. Therefore, in the quantization logic, the numerical operation is realized by depending on the transformation of information; the input of the information is analog or amplitude weight information, the information is converted into the bit weight information through a bit weight quantizer, various numerical operations and logic operations are realized by using the bit weight information, and the output bit weight information is converted into amplitude weight information through the amplitude weight quantizer and is output. The reason for selecting the numerical operation and the logical operation using the bit weight information is as follows: the bit weight information is 'information containing a weight state value', the 'information containing the weight state value' is 'state value' and is expression information, namely information of actual operation of the circuit, and the expression characteristics of the state value information are very similar to those of traditional binary information, so that all numerical operations are basically similar to binary logic operations, mature technology and reliable operation environment are occupied in design and implementation of a circuit architecture, and the circuit architecture can be immediately put into production and operation as long as a complete circuit architecture is constructed.

On the other hand, "quantization logic" theoretically solves the compatibility problem of multi-valued logic and binary logic, clears the barriers between computer carry systems, breaks through the barrier that circuit structures between carry systems are not universal from circuit design, enables the computer design to be free from the choice of carry systems, likes computers of which carry systems, can design computers of which carry systems, and from binary to decimal and more carry systems, the same principle, the same basic circuit and the same architecture are commonly owned, and a plurality of operation effects of the current binary computer can be achieved and surpassed. The selection of different carry systems is purely converted into the requirements of people's preference and real application, and is not limited by logic theory and circuit behavior. The 'quantization logic' circuit fuses circuits of each carry system, circuits of different carry systems can coexist in one circuit system, and the advantages of the circuits of different carry systems are used, so that the defects of the circuits of each carry system are avoided, and the combined circuit system is more ideal. The 'quantization logic' circuit perfectly solves the problem of unique binary options of the input and output information of the computer, widens the limitation of the input and output information types of the computer, enables the input of the input and output information to be directly input by using natural simulation information, can be effectively fused in a natural information system, and forms interaction with the natural information to facilitate the analysis and expression of the natural information, and enables the computer to be improved into higher-level equipment. Along with the number of the selected carry systems, the circuit scale can generate large change, the binary circuit is simplest, the resource utilization rate is highest, the decimal circuit scale is largest, and the resource utilization rate is lowest. The structure of the quantization logic circuit is relatively complex under the multi-system condition, particularly when the quantization logic circuit is applied to a decimal circuit, but I believe that a machine with performance superior to that of a binary computing device can be realized by continuous efforts under the support of the super-large scale integrated circuit technology.

The MOS tube output editing transmission type multi-system and decimal bit-weight adder is a preceding stage circuit for addition operation, can implement one-bit addition digital operation, adopts several one-bit addition operation circuit combinations, can implement direct operation of multi-bit addition, and is the core operation circuit of multi-system operator.

A one-bit multivalued digital adder composed of MOS tubes, MOS tube output editing transmission type multi-system and decimal bit-weight adder, composed of multivalued addition modules with different forms, the multivalued addition module has a module with output home position equal to 0, equal to 1, equal to 2, … … and equal to N, the module is composed of operation units connected in different ways, the unit is formed by arranging and combining units by the circuit of claim 3 of patent application 201711119713.x 'quantization logic multi-system arithmetic operator assigned fractal integrated unit circuit'; after each unit is selected according to a carry system and added with two input addends, the units with the same sum value in one position are arranged together to form an operation module with different scales, the grid electrodes of the units in the module form a group of input of bit weight data, the drain electrodes of the units in the module form a group of input of the bit weight data, the outputs of fractal output carry 1 in the units are connected together to be used as module carry output, the outputs of carry 0 in the units are connected together to form module carry 0 output, and the outputs of the unit home positions are connected together to form the module home position output; no matter what carry system is selected, the module output is only three; the module inputs are different according to the carry system of the selected circuit, the binary adder has two paths and two line inputs respectively, the ternary adder has two paths and three line inputs respectively, the quaternary adder has two paths and four line inputs respectively, the quinary adder has two paths and five line inputs respectively, the quinary adder has two paths and six line inputs respectively, the quinary adder has two paths and seven line inputs respectively, the octal adder has two paths and eight line inputs respectively, the quinary adder has two paths and nine line inputs respectively, and the decimal adder has two paths and ten line inputs … respectively; the grid electrode and the drain electrode of the MOS tube are edited and connected according to an addition table according to the requirement that the addition rule is the same as the home position output of the fractal diode; the binary adder shares two modules, namely a 0 module and a 1 module; the ternary adder shares three adding modules, namely a 0 module, a 1 module and a 2 module; the quaternary adder shares four adding modules, namely a 0 module, a 1 module, a 2 module and a 3 module; the quinary adder shares five adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module and a 4 module; the six-system adder shares six adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module and a 5 module; the seven-system adder shares seven adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module and a 6 module; the eight-system adder shares eight adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module and a 7 module; the nine-system adder shares nine adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module, a 7 module and an 8 module; the decimal adder shares ten adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module, a 7 module, an 8 module and a 9 module; the number of modules is increased in sequence as the carry system is increased.

The module is formed by combining and connecting addition operation units which are connected in different modes, and the units are formed by arranging and combining units which are formed by assigning a fractal integrated unit circuit to a circuit in claim 3 of an x 'quantization logic multilevel arithmetic operator' in patent application 201711119713; the unit combines the units with equal units of 'sum' obtained by adding two addends together and connects the output of the local position together, the output of the local position is the number with equal units of 'sum' of the addition operation of each unit, and the output of the carry position is connected corresponding to the lines of carry 0 and carry 1; the grid of each unit is used as the input of one-way addend bit weight, the drain of each unit is used as the input of the other-way addend, and the connection method of the inputs is to connect the corresponding two-way inputs to the bit weight input terminal according to the addition relation of the output sum.

The module is formed by arranging and combining units of circuits in claim 3, wherein the units are formed by endowing a fractal integrated unit circuit with a multilevel arithmetic operator of quantization logic in patent application 201711119713. x; the number of units used by the module is determined by the selection of a carry system, the binary adder uses two adding units, the ternary adder uses three adding units, the quaternary adder uses four adding units, the quinary adder uses five adding units, the hexaary adder uses six adding units, the heptaary adder uses seven adding units, the octal adder uses eight adding units, the nonal adder uses nine adding units, the decimal adder uses ten adding units, and the Nary adder uses N adding units.

A multi-bit multi-valued full adder composed of MOS transistors, namely a MOS transistor output editing transmission type multi-system and decimal bit weight adder, which is composed of a multi-bit multi-system full adder according to the mode of claim 1 of the patent application 201710024248.5, namely a multi-system arithmetic operator; said multi-bit binary full adder being composed of a plurality of one-bit binary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit ternary full adder is composed of a plurality of one-bit ternary adders in the manner described in claim 1 of patent application 201710024248.5 "multilevel arithmetic operator"; said multi-bit quaternary full adder is composed of a plurality of one-bit quaternary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-ary arithmetic operator"; said multi-bit quinary full adder being formed by a plurality of one-bit quinary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit hexa-ary full adder is composed of a plurality of one-bit hexa-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multinary arithmetic operator"; said multi-bit heptad full adder is composed of a plurality of one-bit heptad adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit octal full adder is composed of a plurality of one-bit octal adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit nine-ary full adder is composed of a plurality of one-bit nine-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-ary arithmetic operator"; said multi-digit decimal full adder is composed of a plurality of one-digit decimal adders in the manner described in claim 1 of patent application 201710024248.5 "multi-system arithmetic operator"; said multi-bit N-ary full adder is composed of a plurality of one-bit N-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator".

Drawings

FIG. 1(1) is a binary addition table

FIG. 1(2) is a ternary addition table

FIG. 1(3) is a quaternary addition table

FIG. 1(4) is a quinary addition table

FIG. 1(5) is a six-system addition table

FIG. 1(6) is a seven-system addition table

FIG. 1(7) is an eight-system addition table

FIG. 1(8) is a nine-system addition table

FIG. 1(9) is a decimal addition table

FIG. 2(1) is a block circuit of binary MOS output edit type bit weight adder with 0-bit output

FIG. 2(2) is a circuit of binary MOS output edit type bit weight adder with 1-bit output

FIG. 2(3) is a combined master control operation circuit of a one-bit binary MOS output-edited bit-weight adder module

FIG. 3(1) is a block circuit of the ternary MOS transistor output editing type bit weight adder with 0-bit output

FIG. 3(2) is a circuit of ternary MOS transistor output editing type bit weight adder with 1-bit output

FIG. 3(3) is a circuit of ternary MOS transistor output editing type bit weight adder with local bit output equal to 2 modules

FIG. 3(4) is a combined master control operation circuit of a one-bit ternary MOS tube output editing type bit-weight adder module

FIG. 4(1) is a block circuit of the output-edited bit-weight adder of the quaternary MOS transistor with 0-bit output

FIG. 4(2) is a circuit of a quaternary MOS transistor output editing type bit weight adder with 1-bit output

FIG. 4(3) is a circuit of the quaternary MOS transistor output edit type bit weight adder with local bit output equal to 2 modules

FIG. 4(4) is a circuit with the same bit output as the 3-module circuit of the output-editing type bit-weight adder of the quaternary MOS transistor

FIG. 4(5) is a combined master control operation circuit of a one-bit quaternary MOS output-edited bit-weight adder module

FIG. 5(1) is a block circuit of an output editing type bit weight adder of a five-system MOS transistor with a bit output equal to 0

FIG. 5(2) is a circuit of a five-system MOS transistor output editing type bit weight adder with 1-bit output

FIG. 5(3) is a circuit of the five-system MOS transistor output editing type bit weight adder with local bit output equal to 2 module

FIG. 5(4) is a circuit with the same bit output as the 3-module circuit of the output-editing type bit-weight adder of the five-system MOS transistor

FIG. 5(5) is a circuit of a five-system MOS transistor output editing type bit weight adder with 4-module output

FIG. 5(6) is a combined master control operation circuit of a one-bit five-system MOS tube output editing type bit-weight adder module

FIG. 6(1) is a block circuit of six-system MOS tube output editing type bit weight adder with 0-bit output

FIG. 6(2) is a circuit of six-system MOS transistor output editing type bit weight adder with 1-bit output

FIG. 6(3) is a circuit of six-system MOS transistor output edit type bit weight adder with local bit output equal to 2 module

FIG. 6(4) is a circuit with six-system MOS tube output editing type bit weight adder with 3-module output

FIG. 6(5) is a circuit of six-system MOS transistor output edit type bit weight adder with 4-module local output

FIG. 6(6) is a circuit of six-system MOS transistor output edit type bit weight adder with local bit output equal to 5 modules

FIG. 6(7) is a combined master control operation circuit of a one-bit six-system MOS tube output editing type bit-weight adder module

FIG. 7(1) is a circuit of a seven-system MOS transistor output editing type bit weight adder with 0-bit output

FIG. 7(2) is a circuit of a seven-system MOS transistor output editing type bit weight adder with 1-bit output

FIG. 7(3) is a circuit of seven-system MOS tube output editing type bit weight adder with local bit output equal to 2 module

FIG. 7(4) is a circuit of seven-system MOS tube output editing type bit weight adder with 3-module output

FIG. 7(5) is a circuit of seven-system MOS tube output editing type bit weight adder with 4-module output

FIG. 7(6) is a circuit of seven-system MOS tube output editing type bit weight adder with 5-module local output

FIG. 7(7) is a circuit of seven-system MOS tube output editing type bit weight adder with 6-module output

FIG. 7(8) is a combined master control operation circuit of a one-bit seven-system MOS tube output editing type bit-weight adder module

FIG. 8(1) is a block circuit of eight-system MOS output edit type bit weight adder with local bit output equal to 0

FIG. 8(2) is a circuit of eight-system MOS transistor output edit type bit weight adder with 1-bit output

FIG. 8(3) is a circuit of eight-system MOS transistor output edit type bit weight adder with local bit output equal to 2 module

FIG. 8(4) is a circuit with eight-system MOS output edit type bit weight adder with 3-module local output

FIG. 8(5) is a circuit of eight-system MOS transistor output edit type bit weight adder with 4-module local output

FIG. 8(6) is a circuit diagram of eight-system MOS transistor output edit type bit weight adder with 5-module local output

FIG. 8(7) is a circuit diagram of eight-system MOS output edit type bit weight adder with 6-module local output

FIG. 8(8) is a circuit with eight-system MOS output edit type bit weight adder with 7-module local output

FIG. 8(9) is a combined master control operation circuit of a one-bit eight-system MOS output-editing type bit-weight adder module

FIG. 9(1) is a block circuit of the output edit type bit weight adder of the nine-system MOS transistor with the output bit equal to 0

FIG. 9(2) is a circuit of a nine-system MOS transistor output editing type bit weight adder with 1-bit output

FIG. 9(3) is a circuit of the nine-system MOS transistor output edit type bit weight adder with local bit output equal to 2 module

FIG. 9(4) is a circuit with the output of the nine-system MOS transistor editing type bit weight adder being equal to the 3-module output

FIG. 9(5) is a circuit with 4 modules of output equal to the output of the nine-ary MOS transistor output edit type bit weight adder

FIG. 9(6) is a circuit diagram of a nine-system MOS transistor output editing type bit weight adder with 5-module local output

FIG. 9(7) is a circuit with 6-module circuit for the output of the nine-system MOS transistor editing type bit weight adder

FIG. 9(8) is a circuit with 7-module circuit for the output of the nine-system MOS transistor editing type bit weight adder

FIG. 9(9) is a circuit with 8-module circuit for the output of the nine-system MOS transistor editing type bit weight adder

FIG. 9(10) is a combined master control operation circuit of a one-bit nine-system MOS transistor output editing type bit weight adder module

FIG. 10(1) is a block circuit of decimal MOS transistor output edit type bit weight adder with 0-bit output

FIG. 10(2) is a circuit of decimal MOS transistor output edit type bit weight adder with 1-bit output

FIG. 10(3) is a circuit of decimal MOS transistor output edit type bit weight adder with 2-module output

FIG. 10(4) is a circuit with decimal MOS transistor output edit type bit weight adder with 3-module output

FIG. 10(5) is a circuit with decimal MOS transistor output edit type bit weight adder with 4-module output

FIG. 10(6) is a circuit diagram of decimal MOS transistor output edit type bit weight adder with 5-module output

FIG. 10(7) is a circuit diagram of decimal MOS transistor output edit type bit weight adder with 6-module output

FIG. 10(8) is a circuit with decimal MOS transistor output edit type bit weight adder with 7-module output

FIG. 10(9) is a circuit with decimal MOS transistor output edit type bit weight adder with 8-module output

FIG. 10(10) is a circuit diagram of decimal MOS transistor output edit type bit weight adder with 9-module output

FIG. 10(11) is a combined master control operation circuit of a decimal MOS transistor output editing type weight adder module

Detailed description of the preferred embodiments

Referring to fig. 2(1), 2(2), 2(3), the circuit of claim 3 in the two patent applications 201711119713.x "quantization logic multilevel arithmetic operator assigned fractal integrated unit circuit" is used as a unit circuit, the grid electrode of each MOS transistor is used as a group of bit weight input, the drain electrode of each MOS transistor is used as another group of bit weight input, the grid electrode and the drain electrode of the MOS transistor are edited and connected according to the addition table of fig. 1(1) according to the addition rule and the local output requirement of the fractal diode, thereby forming an addition operation module with the same output local, the local output is equal to a module 0, and the output is equal to a module 1. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 2(1) and the addition table described in fig. 1 (1). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 2(2) and the addition table described in fig. 1 (1). Finally, the input/output buses of the module whose output is equal to 0 and the module whose output is equal to 1 are connected together according to the corresponding line numbers according to the method of fig. 2(3) to be used as the bit weight input and output of the adder, which is the bit weight adder of the binary output editing type.

Referring to fig. 3(1), (3), (2), (3), and (4), the circuit of claim 3 in the three patent applications 201711119713.x "quantization logic multilevel arithmetic operator is assigned to fractal integrated unit circuit" as a unit circuit, and the gate of each MOS transistor is used as a group of bit weight input, the drain of each MOS transistor is used as another group of bit weight input, the gate and the drain of the MOS transistor are edited and connected according to the addition rule and the local output requirement of the fractal diode according to the addition table of fig. 1(2), thereby forming an addition operation module with the same output local, the local output is equal to 0 module, the output is equal to 1 module, and the output is equal to 2 modules. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 3(1) and the addition table described in fig. 1 (2). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 3(2) and the addition table described in fig. 1 (2). The output equals 2 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 3(3) and the addition table described in fig. 1 (2). Finally, the input/output buses of the modules whose outputs are equal to 0, 1 and 2 are correspondingly connected together according to the line numbers according to the method of fig. 3(4) to be used as the bit weight input and output of the adder, which is the one-bit ternary output editing type bit weight adder.

Referring to fig. 4(1), 4(2), 4(3), 4(4)4(5), the circuit of claim 3 in the four patent applications 201711119713.x "quantization logic multilevel arithmetic operator is assigned to fractal integrated unit circuit" is used as a unit circuit, the grid electrode of each MOS transistor is used as a group of bit weight input, the drain electrode of each MOS transistor is used as another group of bit weight input, the grid electrode and the drain electrode of the MOS transistor are edited and connected according to the addition table of fig. 1(3) according to the addition rule and the local output requirement of the fractal diode, so that an addition operation module with the same output local is formed, the local output is equal to a 0 module, the local output is equal to a 1 module, the local output is equal to a 2 module, and the local output is equal to a 2 module. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 4(1) and the addition table described in fig. 1 (3). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 4(2) and the addition table described in fig. 1 (3). The output equals 2 module edits the output bit right information according to the method described in fig. 4(3) and the addition table described in fig. 1(3) and connects to the corresponding output bit right bus, and the output equals 3 module edits the output bit right information according to the method described in fig. 4(4) and the addition table described in fig. 1(3) and connects to the corresponding output bit right bus. Finally, according to the method of fig. 4(5), the input/output buses of the modules whose outputs are equal to 0, 1, 2 and 3 are connected together by the line numbers to be used as the bit-right input and output of the adder, which is the bit-weight adder with the quaternary output and edit type.

Referring to fig. 5(1), 5(2), 5(3), 5(4)5(5), 5(6), the circuit of claim 3 in five patent applications 201711119713.x "quantization logic multilevel arithmetic operator assigned fractal integrated unit circuit" is used as a unit circuit, the grid electrode of each MOS transistor is used as a group of bit weight input, the drain electrode of each MOS transistor is used as another group of bit weight input, the grid electrode and the drain electrode of the MOS transistor are edited and connected according to the addition table of fig. 1(4) according to the addition rule and the local output requirement of the fractal diode, thereby forming an addition operation module with the same output local position, the local output is equal to a 0 module, the output is equal to a 1 module, the output is equal to a 2 module, the output is equal to a 3 module, and the output is equal to a 4 module. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 5(1) and the addition table described in fig. 1 (4). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 5(2) and the addition table described in fig. 1 (4). The output equal-to-2 module edits the output bit right information according to the method described in fig. 5(3) and the addition table described in fig. 1(4) and connects to the corresponding output bit right bus, the output equal-to-3 module edits the output bit right information according to the method described in fig. 5(4) and the addition table described in fig. 1(4) and connects to the corresponding output bit right bus, and the output equal-to-4 module edits the output bit right information according to the method described in fig. 5(5) and the addition table described in fig. 1(4) and connects to the corresponding output bit right bus. Finally, according to the method shown in fig. 5(6), the input/output bus of the module whose output is equal to 0, the output is equal to 1, the output is equal to 2, the output is equal to 3, and the input/output bus of the module whose output is equal to 4 are connected together by the line number to be used as the bit right input and output of the adder, which is the one-bit quinary output editing type bit right adder.

Referring to fig. 6(1), 6(2), 6(3), 6(4)6(5), 6(6), 6(7), the circuit of claim 3 in six patent applications 201711119713.x "quantization logic multilevel arithmetic operator is assigned to fractal integrated unit circuit" is used as unit circuit, and the grid of each MOS transistor is used as a group of bit weight input, the drain of each MOS transistor is used as another group of bit weight input, the grid and the drain of the MOS transistor are edited and connected according to the addition table of fig. 1(5) according to the addition rule and the local output requirement of the fractal diode, so as to form an addition operation module with the same output local position, the local output is equal to 0 module, the local output is equal to 1 module, the local output is equal to 2 module, the local output is equal to 3 module, the local output is equal to 4 module, and the local output is equal to 5 module. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 6(1) and the addition table described in fig. 1 (5). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 6(2) and the addition table described in fig. 1 (5). The output equal-to-2 module edits the output bit right information according to the method described in fig. 6(3) and the addition table described in fig. 1(5) and connects to the corresponding output bit right bus, the output equal-to-3 module edits the output bit right information according to the method described in fig. 6(4) and the addition table described in fig. 1(5) and connects to the corresponding output bit right bus, the output equal-to-4 module edits the output bit right information according to the method described in fig. 6(5) and the addition table described in fig. 1(5) and connects to the corresponding output bit right bus, and the output equal-to-5 module edits the output bit right information according to the method described in fig. 6(6) and the addition table described in fig. 1(5) and connects to the corresponding output bit right bus. Finally, according to the method shown in fig. 6(7), the input/output bus of the module whose output is equal to 0, the output is equal to 1, the output is equal to 2, the output is equal to 3, the output is equal to 4, and the input/output bus of the module whose output is equal to 5 is correspondingly connected together according to the line number to be used as the bit right input and output of the adder, which is the one-bit six-system output editing type bit right adder.

Referring to fig. 7(1), (7), (2), (7), (3), (7), (4), (7), (5), (7), (6), (7), (8), the circuit of claim 3 in seven patent applications 201711119713.x "quantization logic multilevel arithmetic operator is assigned to fractal integrated unit circuit" as unit circuit, and the grid of each MOS tube is used as a group of bit weight input, the drain of each MOS tube is used as another group of bit weight input, the grid and the drain of the MOS tube are edited and connected according to the addition rule and the local output requirement of the fractal diode according to the addition table of figure 1(6), therefore, an addition operation module with the same output position is formed, the position output is equal to a 0 module, the output is equal to a 1 module, the output is equal to a 2 module, the output is equal to a 3 module, the output is equal to a 4 module, the output is equal to a 5 module, and the output is equal to a 6 module. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 7(1) and the addition table described in fig. 1 (6). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 7(2) and the addition table described in fig. 1 (6). Editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 2 module according to the method described in FIG. 7(3) and the addition table described in FIG. 1(6), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 3 module according to the method described in FIG. 7(4) and the addition table described in FIG. 1(6), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 4 module according to the method described in FIG. 7(5) and the addition table described in FIG. 1(6), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 5 module according to the method described in FIG. 7(6) and the addition table described in FIG. 1(6), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 6 module according to the method described in FIG. 7(7) and the addition table described in FIG. 1(6), editing the output bit weight information and connecting to the corresponding output bit weight bus. Finally, according to the method shown in fig. 7(8), the output equals to 0 module, the output equals to 1 module, the output equals to 2 module, the output equals to 3 module, the output equals to 4 module, the output equals to 5 module, and the input/output buses of the output equals to 6 module are correspondingly connected together according to the line number to be used as the bit weight input and output of the adder, which is the one-bit seven-system output editing type bit weight adder.

Referring to fig. 8(1), 8(2), 8(3), 8(4), 8(5), 8(6), 8(7), 8(8), 8(9), the circuit of claim 3 in eight patent applications 201711119713.x "quantization logic multilevel arithmetic operator assigned fractal integrated unit circuit" is used as a unit circuit, and the gate of each MOS transistor is used as a group of bit weight input, the drain of each MOS transistor is used as another group of bit weight input, the gate and the drain of the MOS transistor are edited and connected according to the addition table of fig. 1(7) according to the addition rule and the requirement of the fractal diode's home output, so as to form an addition operation module with the same output home position, the home position output is equal to 0 module, the home position output is equal to 1 module, the present output is equal to 2 module, the present output is equal to 3 module, the present output is equal to 4 module, the present output is equal to 5 module, the output is equal to 6 modules, and the output is equal to 7 modules. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 8(1) and the addition table described in fig. 1 (7). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 8(2) and the addition table described in fig. 1 (7). Editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 2 module according to the method described in FIG. 8(3) and the addition table described in FIG. 1(7), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 3 module according to the method described in FIG. 8(4) and the addition table described in FIG. 1(7), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 4 module according to the method described in FIG. 8(5) and the addition table described in FIG. 1(7), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 5 module according to the method described in FIG. 8(6) and the addition table described in FIG. 1(7), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 6 module according to the method described in FIG. 8(7) and the addition table described in FIG. 1(7), editing the outputted bit-right information and connecting to the corresponding output bit-right bus, wherein the output equals 7 module edits the outputted bit-right information and connects to the corresponding output bit-right bus according to the method described in fig. 8(8) and the addition table described in fig. 1 (7). Finally, according to the method shown in fig. 8(9), the output equals to 0 module, the output equals to 1 module, the output equals to 2 module, the output equals to 3 module, the output equals to 4 module, the output equals to 5 module, the output equals to 6 module, and the input and output buses of the output equals to 7 module are correspondingly connected together according to the line number to be used as the bit right input and output of the adder, which is the one-bit eight-system output editing type bit right adder.

Referring to fig. 9(1), (9), (2), (9), (3), (9), (4), (9), (5), (9), (6), (9), (7), (9), (8), (9), (10), the circuit of claim 3 in nine patent applications 201711119713.x "quantization logic multilevel arithmetic operator assigned fractal integrated unit circuit" is used as a unit circuit, the grid electrode of each MOS transistor is used as a group of bit weight input, the drain electrode of each MOS transistor is used as another group of bit weight input, the grid electrode and the drain electrode of the MOS transistor are edited and connected according to the addition table of fig. 1(8) according to the addition rule and the requirement of the local output of the fractal diode, thereby forming an addition operation module with the same output local bit, the local bit output is equal to 0 module, the output is equal to 1 module, the output is equal to 2 module, the output is equal to 3 module, the output is equal to 4 module, the output is equal to 5 module, the output is equal to 6 modules, the output is equal to 7 modules, and the output is equal to 8 modules. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 9(1) and the addition table described in fig. 1 (8). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 9(2) and the addition table described in fig. 1 (8). Editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 2 module according to the method described in FIG. 9(3) and the addition table described in FIG. 1(8), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 3 module according to the method described in FIG. 9(4) and the addition table described in FIG. 1(8), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 4 module according to the method described in FIG. 9(5) and the addition table described in FIG. 1(8), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 5 module according to the method described in FIG. 9(6) and the addition table described in FIG. 1(8), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 6 module according to the method described in FIG. 9(7) and the addition table described in FIG. 1(8), editing the outputted bit-right information and connecting it to the corresponding output bit-right bus, the module for outputting equal to 7 edits the outputted bit-right information and connects it to the corresponding output bit-right bus according to the method described in fig. 9(8) and the addition table described in fig. 1(8), the module for outputting equal to 8 edits the outputted bit-right information and connects it to the corresponding output bit-right bus according to the method described in fig. 9(9) and the addition table described in fig. 1 (8). Finally, according to the method shown in fig. 9(10), the output equals to 0 module, the output equals to 1 module, the output equals to 2 module, the output equals to 3 module, the output equals to 4 module, the output equals to 5 module, the output equals to 6 module, the output equals to 7 module, and the input/output buses of the output equals to 8 module are correspondingly connected together according to the line number to be used as the bit right input and output of the adder, which is the one-bit nine-system output editing type bit right adder.

Referring to fig. 10(1), 10(2), 10(3), 10(4), 10(5), 10(6), 10(7), 10(8), 10(9), 10(10), 10(11), the circuit of claim 3 in ten patent applications 201711119713.x "quantization logic multilevel arithmetic operator assigned fractal integrated unit circuit" is used as a unit circuit, and the grid electrode of each MOS transistor is used as a group of bit weight input, the drain electrode of each MOS transistor is used as another group of bit weight input, the grid electrode and the drain electrode of the MOS transistor are edited and connected according to the addition table of fig. 1(9) according to the addition rule and the requirement of the local output of the fractal diode, so as to form an addition operation module with the same output local, the local output is equal to 0 module, the output is equal to 1 module, the output is equal to 2 module, the output is equal to 3 module, the output is equal to 4 module, an output is equal to 5 modules, an output is equal to 6 modules, an output is equal to 7 modules, an output is equal to 8 modules, and an output is equal to 9 modules. The output equals 0 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 10(1) and the addition table described in fig. 1 (9). The output equal to 1 module edits the output bit weight information and connects to the corresponding output bit weight bus according to the method described in fig. 10(2) and the addition table described in fig. 1 (9). Editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 2 module according to the method described in FIG. 10(3) and the addition table described in FIG. 1(9), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 3 module according to the method described in FIG. 10(4) and the addition table described in FIG. 1(9), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 4 module according to the method described in FIG. 10(5) and the addition table described in FIG. 1(9), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 5 module according to the method described in FIG. 10(6) and the addition table described in FIG. 1(9), editing the outputted bit right information and connecting it to the corresponding output bit right bus by the output equal 6 module according to the method described in FIG. 10(7) and the addition table described in FIG. 1(9), editing the outputted bit-right information and connecting it to the corresponding output bit-right bus, wherein the module with output equal to 7 edits the outputted bit-right information and connects it to the corresponding output bit-right bus according to the method described in fig. 10(8) and the addition table described in fig. 1(9), wherein the module with output equal to 8 edits the outputted bit-right information and connects it to the corresponding output bit-right bus according to the method described in fig. 10(9) and the addition table described in fig. 1(9), wherein the module with output equal to 9 edits the outputted bit-right information and connects it to the corresponding output bit-right bus according to the method described in fig. 10(10) and the addition table described in fig. 1 (9). Finally, according to the method shown in fig. 10(11), the output equals to 0 module, the output equals to 1 module, the output equals to 2 module, the output equals to 3 module, the output equals to 4 module, the output equals to 5 module, the output equals to 6 module, the output equals to 7 module, the output equals to 8 module, the input and output buses of the output equals to 8 module are correspondingly connected together by the line number to be used as the bit right input and output of the adder, which is the one-digit decimal output editing type bit right adder.

Claims (4)

1. An output editing transmission type multi-system and decimal bit-weight adder of MOS tube composed of MOS tube, composed of multi-value addition modules with different forms, the said multi-value addition module has output home position equal to 0 module, equal to 1 module, equal to 2 module … … equal to N module, the said module is composed of different connected arithmetic unit combination, the said unit is formed by arranging and combining the circuit of claim 3 of patent application 201711119713.x 'multi-system arithmetic operator of quantization logic meaning fractal integrated unit circuit'; after each unit is selected according to a carry system and added with two input addends, the units with the same sum value in one position are arranged together to form an operation module with different scales, the grid electrodes of the units in the module form a group of input of bit weight data, the drain electrodes of the units in the module form a group of input of the bit weight data, the outputs of fractal output carry 1 in the units are connected together to be used as module carry output, the outputs of carry 0 in the units are connected together to form module carry 0 output, and the outputs of the unit home positions are connected together to form the module home position output; no matter what carry system is selected, the module output is only three; the module inputs are different according to the carry system of the selected circuit, the binary adder has two paths and two line inputs respectively, the ternary adder has two paths and three line inputs respectively, the quaternary adder has two paths and four line inputs respectively, the quinary adder has two paths and five line inputs respectively, the quinary adder has two paths and six line inputs respectively, the quinary adder has two paths and seven line inputs respectively, the octal adder has two paths and eight line inputs respectively, the quinary adder has two paths and nine line inputs respectively, and the decimal adder has two paths and ten line inputs … respectively; the grid electrode and the drain electrode of the MOS tube are edited and connected according to an addition table according to the requirement that the addition rule is the same as the home position output of the fractal diode; the binary adder shares two modules, namely a 0 module and a 1 module; the ternary adder shares three adding modules, namely a 0 module, a 1 module and a 2 module; the quaternary adder shares four adding modules, namely a 0 module, a 1 module, a 2 module and a 3 module; the quinary adder shares five adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module and a 4 module; the six-system adder shares six adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module and a 5 module; the seven-system adder shares seven adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module and a 6 module; the eight-system adder shares eight adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module and a 7 module; the nine-system adder shares nine adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module, a 7 module and an 8 module; the decimal adder shares ten adding modules, namely a 0 module, a 1 module, a 2 module, a 3 module, a 4 module, a 5 module, a 6 module, a 7 module, an 8 module and a 9 module; the number of modules is increased in sequence as the carry system is increased.

2. The module of claim 1, wherein the modules are formed by combining and connecting addition units connected in different ways, and the units are formed by arranging and combining the circuits of claim 3 in patent application 201711119713.x "the multilevel arithmetic operator of quantization logic is assigned to a fractal integrated unit circuit"; the unit combines the units with equal units of 'sum' obtained by adding two addends together and connects the output of the local position together, the output of the local position is the number with equal units of 'sum' of the addition operation of each unit, and the output of the carry position is connected corresponding to the lines of carry 0 and carry 1; the grid of each unit is used as the input of one-way addend bit weight, the drain of each unit is used as the input of the other-way addend, and the connection method of the inputs is to connect the corresponding two-way inputs to the bit weight input terminal according to the addition relation of the output sum.

3. The module as claimed in claim 1, wherein the module is formed by arranging and combining units of the circuit as claimed in claim 3, wherein the fractal integrated unit circuit is assigned by a multilevel arithmetic operator of quantization logic of patent application 201711119713.x "; the number of units used by the module is determined by the selection of a carry system, the binary adder uses two adding units, the ternary adder uses three adding units, the quaternary adder uses four adding units, the quinary adder uses five adding units, the hexaary adder uses six adding units, the heptaary adder uses seven adding units, the octal adder uses eight adding units, the nonal adder uses nine adding units, the decimal adder uses ten adding units, and the Nary adder uses N adding units.

4. The output of the MOS transistor composed of MOS transistors is edited and transmitted by the multi-level and decimal-weight adder according to claim 1, the multi-level full adder is composed according to the method of claim 1 of patent application 201710024248.5 "multi-level arithmetic operator"; said multi-bit binary full adder being composed of a plurality of one-bit binary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit ternary full adder is composed of a plurality of one-bit ternary adders in the manner described in claim 1 of patent application 201710024248.5 "multilevel arithmetic operator"; said multi-bit quaternary full adder is composed of a plurality of one-bit quaternary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-ary arithmetic operator"; said multi-bit quinary full adder being formed by a plurality of one-bit quinary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit hexa-ary full adder is composed of a plurality of one-bit hexa-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multinary arithmetic operator"; said multi-bit heptad full adder is composed of a plurality of one-bit heptad adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit octal full adder is composed of a plurality of one-bit octal adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator"; said multi-bit nine-ary full adder is composed of a plurality of one-bit nine-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-ary arithmetic operator"; said multi-digit decimal full adder is composed of a plurality of one-digit decimal adders in the manner described in claim 1 of patent application 201710024248.5 "multi-system arithmetic operator"; said multi-bit N-ary full adder is composed of a plurality of one-bit N-ary adders in the manner described in claim 1 of patent application 201710024248.5 "multi-bit arithmetic operator".

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