CN111601056A - Large dynamic range semi-floating gate image sensor - Google Patents
Large dynamic range semi-floating gate image sensor Download PDFInfo
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- CN111601056A CN111601056A CN202010405198.7A CN202010405198A CN111601056A CN 111601056 A CN111601056 A CN 111601056A CN 202010405198 A CN202010405198 A CN 202010405198A CN 111601056 A CN111601056 A CN 111601056A
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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Abstract
The invention discloses a large-dynamic-range semi-floating gate image sensor which comprises a pixel array, a current processing column level circuit and a voltage processing column level circuit, wherein the pixel array comprises a plurality of pixels, each pixel comprises a semi-floating gate transistor and a first voltage conversion circuit, and the first voltage conversion circuit is used for converting a current signal output by the semi-floating gate transistor into a voltage signal and respectively sampling and outputting a reset voltage and a signal voltage, so that pixel-level related double sampling is realized, and reading noise is reduced. In the invention, a voltage column level processing circuit is added in the semi-floating gate image sensor, and a voltage conversion circuit is added in each pixel, so that the image sensor can give consideration to both large full-well charge capacity and high conversion gain, can image under both high background and low background, and greatly expands the application range of the semi-floating gate image sensor; in addition, Binning among pixels can be realized, and the dynamic range of the image sensor is further expanded.
Description
Technical Field
The invention relates to the field of image sensors, in particular to a large-dynamic-range semi-floating gate image sensor.
Background
Floating gate devices have been widely used in various types of nonvolatile memories since their first introduction, and in recent years, semi-floating gate devices are being increasingly used in image sensors. The function of the traditional 3T CMOS image sensor can be realized by the semi-floating gate device by using a simple 1T structure, so that the filling factor can be improved, and the integration level can be increased; the floating gate is used for storing photo-generated charges in the working process of the semi-floating gate 1T pixel, and MOS tube current which changes along with the light intensity can be output to represent image information; the current signal can be converted into a voltage signal by integrating the input current on the feedback capacitor through the column-level capacitor trans-impedance amplifier, and then the voltage signal is read out after being processed by other processing circuits.
The dynamic range is one of important performance parameters of the image sensor, is an index for representing the application environment range of the image sensor and is determined by the ratio of the full-trap charge to the readout noise. Under the condition of low background imaging, weak photoproduction signals can be read only by needing higher conversion gain and lower reading noise; under the condition of high background imaging, the effective photo-generated signals can be stored only by needing larger full-trap charge capacity, so that overflow is avoided. Therefore, it is often difficult to design a large dynamic range image sensor that requires simultaneous application to both low and high background imaging conditions.
For a semi-floating gate image sensor, the charge of a full well and conversion gain are directly related to the capacitance of a photodiode, so that the large full well and high gain are difficult to be considered simultaneously; in addition, regarding noise, the related art can realize column-level correlated double sampling operation of half-floating gate 1T pixel output current by placing a correlation circuit in a column-level circuit, but since correlated double sampling is not a pixel level, there is a certain limitation in eliminating KTC noise and fixed pattern noise.
Disclosure of Invention
The invention provides a large-dynamic-range semi-floating gate image sensor which is suitable for high background imaging and low background imaging.
The technical scheme of the invention is as follows:
a large dynamic range semi-floating gate image sensor comprises a pixel array, a current processing column level circuit and a voltage processing column level circuit, wherein the pixel array comprises a plurality of pixels, each pixel comprises a semi-floating gate transistor and a first voltage conversion circuit, the source electrode of the semi-floating gate transistor is grounded, the grid electrode of the semi-floating gate transistor is used for receiving a first pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor is used for receiving a second pixel control signal corresponding to the pixel, and the drain electrode of the semi-floating gate transistor is electrically connected with the current processing column level circuit through a pixel column level current bus corresponding to the pixel;
the drain electrode of the semi-floating gate transistor of each pixel is also electrically connected with a first voltage conversion circuit of the semi-floating gate transistor, the first voltage conversion circuit is also electrically connected with the voltage processing column-level circuit through a pixel column-level voltage bus corresponding to the pixel, and the first voltage conversion circuit is used for converting a current signal output by the semi-floating gate transistor into a voltage signal and respectively sampling and outputting a reset voltage and a signal voltage.
Further, the first voltage conversion circuit comprises a sampling control transistor, a level adjustment transistor, an output control transistor and a sampling capacitor, wherein the drain electrode of the sampling control transistor is electrically connected with the drain electrode of the semi-floating gate transistor, the grid electrode of the sampling control transistor is used for receiving a sampling control signal, the source electrode of the sampling control transistor is electrically connected with the positive plate of the sampling capacitor, the negative plate of the sampling capacitor is grounded, the drain electrode of the level adjustment transistor is connected with a power supply voltage VCC, the grid electrode of the level adjustment transistor is electrically connected with the positive plate of the sampling capacitor, the source electrode of the level adjustment transistor is electrically connected with the drain electrode of the output control transistor, the grid electrode of the output control transistor is used for receiving a row selection signal, and the source electrode of the sampling control transistor is electrically connected with.
Further, the conversion gain of the first voltage conversion circuit is determined by the capacitance value of the sampling capacitor.
Furthermore, the working process of the semi-floating gate transistor is divided into a pixel reset stage, a reset current output stage, an integration stage and a signal current output stage according to the time sequence;
at the initial moment of a pixel reset stage, a first pixel control signal corresponding to the pixel is at a high level, and a second pixel control signal, a sampling control signal and an output control signal corresponding to the pixel are all at a low level, so that the semi-floating gate transistor is reset;
at the initial moment of the reset current output stage, a second pixel control signal and a sampling control signal corresponding to the pixel are converted into high levels, so that the semi-floating gate transistor outputs the reset current, and the sampling capacitor is reset;
at the initial moment of the integration stage, a first pixel control signal and a sampling control signal corresponding to the pixel are converted into low levels, so that the semi-floating gate transistor is in an integration state; at the end of the integration stage, the output control signal corresponding to the pixel is firstly converted into a high level, then the sampling control signal corresponding to the pixel outputs a high level pulse, the reset voltage of the sampling capacitor is sampled, and the high level pulse is output to the voltage processing column-level circuit;
at the initial moment of the signal current output stage, a first pixel control signal corresponding to the pixel is converted into a high level, so that the semi-floating gate transistor outputs an optical response signal current, and the sampling capacitor converts the optical response signal current into an optical response signal voltage; then, the sampling control signal corresponding to the pixel outputs a high-level pulse again, samples the light response signal voltage and outputs the light response signal voltage to the voltage processing column stage circuit.
The pixel array comprises a plurality of pixel sub-arrays, each pixel sub-array comprises a second voltage conversion circuit and a plurality of pixels, each pixel comprises a semi-floating gate transistor, the source electrode of the semi-floating gate transistor of each pixel is grounded, the grid electrode of the semi-floating gate transistor is used for receiving a first pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor of each pixel in a first row of the pixel sub-arrays is used for receiving a second pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor of each pixel in a non-first row of the pixels of the pixel sub-arrays is electrically connected with the drain electrode of the semi-floating gate transistor of the pixel in the first row of the pixels, and the drain electrode of the semi-floating gate transistor of each row of the pixels in the pixel sub-arrays is also electrically connected with the semi-floating gate transistor of the pixel through a corresponding pixel row current bus and the voltage processing row level circuit The current processing column level circuit is electrically connected;
in each row of pixels of the pixel subarray, the drain of the semi-floating gate transistor of each pixel is electrically connected with a second voltage conversion circuit, the second voltage conversion circuit is also electrically connected with the voltage processing row level circuit through a pixel row level voltage bus corresponding to the pixel subarray, and the second voltage conversion circuit is used for accumulating current signals output by the pixels, converting the current signals into voltage signals, and respectively sampling and outputting the accumulated reset voltage and signal voltage.
Furthermore, the second voltage conversion circuit comprises a level adjustment transistor, an output control transistor, a sampling capacitor and a plurality of sampling control transistors, each sampling control transistor corresponds to a column of pixels of the pixel sub-array, the drain electrode of the semi-floating gate transistor of each column of pixels is electrically connected with the drain electrode of the corresponding sampling control transistor, the grid electrode of each sampling control transistor is used for receiving a sampling control signal, the source electrode of each sampling control transistor is electrically connected with the positive plate of the sampling capacitor, the negative plate of the sampling capacitor is grounded, the drain electrode of the level adjusting transistor is connected with a power supply voltage VCC, the grid electrode of the level adjusting transistor is electrically connected with the positive plate of the sampling capacitor, the source electrode of the level adjusting transistor is electrically connected with the drain electrode of the output control transistor, the grid electrode of the output control transistor is used for receiving a row selection signal, and the source electrode of the output control transistor is electrically connected with the voltage processing column level circuit through a corresponding pixel column level voltage bus.
Further, the conversion gain of the second voltage conversion circuit is determined by the capacitance value of the sampling capacitor.
Further, the pixel sub-array is a 2 × 2 array.
Has the advantages that: in the invention, a voltage column level processing circuit is added in the semi-floating gate image sensor, and a voltage conversion circuit is added in each pixel or pixel sub-array, so that the image sensor can give consideration to both large full-well charge capacity and high conversion gain, simultaneously realizes pixel level related double sampling, reduces read-out noise, can image under both high background and low background, and greatly expands the application range of the semi-floating gate image sensor; in addition, Binning among pixels can be realized, and the dynamic range of the image sensor is further expanded. .
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a circuit block diagram of one embodiment of the present invention;
FIG. 3 is a timing diagram of the control signals of FIG. 2;
fig. 4 is a circuit structure diagram of another embodiment of the present invention.
Detailed Description
In order to make the technical solutions in the embodiments of the present invention better understood and make the above objects, features and advantages of the embodiments of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the term "connected" is to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, or a communication between two elements, or may be a direct connection or an indirect connection through an intermediate medium, and a specific meaning of the term may be understood by those skilled in the art according to specific situations.
As shown in fig. 1 and 2, one embodiment of the large dynamic range semi-floating gate image sensor of the present invention includes a pixel array, a current processing column stage circuit for sampling, amplifying, etc. current signals output by the semi-floating gate image sensor pixel array, and a voltage processing column stage circuit for sampling, amplifying, etc. voltage signals output by the semi-floating gate image sensor pixel array.
The pixel array comprises a plurality of pixels, each pixel comprises a semi-floating gate transistor Tr and a first Voltage conversion circuit, the source electrode of the semi-floating gate transistor Tr is grounded, the grid electrode of the semi-floating gate transistor Tr is used for receiving a first pixel control signal VCG corresponding to the pixel, the drain electrode of the semi-floating gate transistor Tr is used for receiving a second pixel control signal VD corresponding to the pixel, the drain electrode of the semi-floating gate transistor Tr is further electrically connected with the Current processing Column stage circuit through a pixel Column stage Current Bus line Column Bus Current corresponding to the pixel, the drain electrode of the semi-floating gate transistor Tr of each pixel is further electrically connected with the first Voltage conversion circuit of each pixel, and the first Voltage conversion circuit is further electrically connected with the Voltage processing Column stage circuit through a pixel Column stage Voltage Bus line Column Bus Voltage corresponding to the pixel.
The first voltage conversion circuit is used for converting a current signal output by the semi-floating gate transistor Tr into a voltage signal and respectively sampling and outputting a reset voltage and a signal voltage; the first voltage conversion circuit includes a sampling control transistor Q1, a level adjustment transistor Q2, an output control transistor Q3, and a sampling capacitor Cap, the drain of the sampling control transistor Q1 is electrically connected to the drain of the semi-floating gate transistor Tr, the gate of the sampling control transistor Q1 is used for receiving a sampling control signal Sample, the source electrode of the sampling control transistor Q1 is electrically connected with the positive plate of a sampling capacitor Cap, the negative plate of the sampling capacitor Cap is grounded, the drain of the level adjusting transistor Q2 is connected with a supply voltage VCC, the grid is electrically connected with the positive plate of the sampling capacitor Cap, the source is electrically connected with the drain of the output control transistor Q3, the gate of the output control transistor Q3 is used for receiving a row selection signal Sel, the source is electrically connected with the Voltage processing Column stage circuit through a pixel Column stage Voltage Bus Column Bus Voltage, the voltage conversion gain of the first voltage conversion circuit is determined by the capacitance value of the sampling capacitor Cap.
The working principle of the embodiment is as follows:
as shown in fig. 1, each pixel of the pixel array sends the photoresponse Current to the Current processing Column-level circuit for processing through a pixel Column-level Current Bus Column Bus during the imaging process, and simultaneously converts the photoresponse Current into a Voltage signal, samples a reset Voltage and a signal Voltage respectively, and sends the Voltage signal to the Voltage processing Column-level circuit for processing through a pixel Column-level Voltage Bus Column Voltage; the operation of the image sensor will be described below by taking the operation of one pixel as an example.
As shown in fig. 2 and 3, when the image sensor operates, the operation process of the semi-floating gate transistor Tr of the pixel is divided into a pixel reset phase Trst, a reset current output phase Tr1, an integration phase Tint and a signal current output phase Tr2 in a time sequence, and the operation process of the first voltage conversion circuit includes a capacitance reset phase Trst1, a reset voltage output phase Tr3 and a signal voltage output phase Tr 4. The capacitance reset phase Trst1 and the reset current output phase Tr1 are the same phase.
At the initial time of the Trst stage, the first pixel control signal VCG corresponding to the pixel is at a high level, and the second pixel control signal VD corresponding to the pixel, the sampling control signal Sample, and the output control signal Sel are all at a low level, so that the half-floating-gate transistor Tr is reset;
at the initial time of the Tr1 stage, the second pixel control signal VD corresponding to the pixel is converted to a high level, so that the half floating gate transistor Tr outputs a reset Current, and the reset Current is sent to the Current processing Column stage circuit for processing through the pixel Column stage Current Bus Column Bus Current; meanwhile, the first voltage conversion circuit enters a Trst1 stage, a sampling control signal Sample corresponding to the pixel is converted into a high level, and the sampling capacitor Cap is reset by the reset current output by the semi-floating gate transistor Tr;
at the start time of Tint stage, the first pixel control signal VCG corresponding to the pixel is switched to low level to make the semi-floating gate transistor Tr in an integration state, and at the same time, the first voltage conversion circuit ends the Trst1 stage and the sampling control signal Sample corresponding to the pixel is switched to low level; at the end of Tint phase, the output control signal Sel corresponding to the pixel is switched to high level, and then the first voltage conversion circuit enters Tr3 phase, the sampling control signal Sample corresponding to the pixel is switched to high level, the reset voltage of the sampling capacitor Cap is sampled and output to the voltage processing column-level circuit as the first output voltage of the voltage conversion circuit, before the Tint phase is finished, the sampling control signal Sample corresponding to the pixel is switched to low level, and Tr3 phase is finished.
At the starting time of the Tr2 stage, the first pixel control signal VCG corresponding to the pixel is converted to a high level, so that the semi-floating gate transistor Tr outputs an optical response signal current, then the first voltage conversion circuit enters the Tr4 stage, the sampling control signal Sample corresponding to the pixel is converted to the high level, the optical response signal current output by the semi-floating gate transistor Tr charges the sampling capacitor Cap, so that the sampling capacitor Cap stores the optical response voltage signal, and the size of the conversion of the optical response signal current into the optical response voltage signal is determined by the capacitance value of the sampling capacitor Cap, therefore, the capacitance value of the sampling capacitor Cap can be set according to the actual situation, and thus, the high conversion gain can be realized through a small capacitor; meanwhile, the photoresponse voltage signal is sent to the voltage processing column stage circuit to serve as a second output voltage of the voltage conversion circuit, and the photoresponse voltage signal is matched with the first output voltage output to the voltage processing column stage circuit in the Tr3 stage to complete pixel-level related double sampling operation, so that reset noise is reduced. Before the end of the Tr2 phase, the sampling control signal Sample corresponding to the pixel is switched to low level, and the Tr4 phase is ended; after that, the Tr2 stage is ended, and the first pixel control signal VCG, the second pixel control signal VD, and the output control signal Sel corresponding to the pixel are all switched to the low level.
Each pixel of the invention can simultaneously output an optical response current signal and an optical response voltage signal, the current signal can realize large full-well capacity and is used for high background imaging, and the voltage signal can realize high conversion gain and low noise and is used for low background imaging; thereby achieving a large dynamic range.
Example 2
As shown in fig. 4, another embodiment of the large dynamic range semi-floating gate image sensor of the present invention includes a pixel array, a current processing column stage circuit for sampling, amplifying, etc. current signals output by the semi-floating gate image sensor pixel array, and a voltage processing column stage circuit for sampling, amplifying, etc. voltage signals output by the semi-floating gate image sensor pixel array.
The pixel array comprises a plurality of pixel sub-arrays, each of which comprises the second voltage conversion circuit and a plurality of pixels, the pixel sub-arrays are preferably 2 × 2 arrays, of course, the pixel sub-arrays can be more than 2 rows and/or more than 2 columns; the following description will be made taking as an example a Pixel sub-array including a Pixel (n, m), a Pixel (n +1, m), a Pixel (n, m +1), and a Pixel (n +1, m +1), where n denotes the number of rows and m denotes the number of columns; the four pixels of the Pixel sub-array respectively comprise a semi-floating gate transistor Tr, the sources of the semi-floating gate transistors Tr of the four pixels are all grounded, and the gates of the semi-floating gate transistors Tr of the four pixels are respectively used for receiving first Pixel control signals VCG (n, m) corresponding to the pixels of the mth column of the nth row, the gates of the semi-floating gate transistors Tr of the pixels Pixel (n +1, m) are used for receiving first Pixel control signals VCG (n +1, m) corresponding to the pixels of the mth column of the (n +1) th row, the gates of the semi-floating gate transistors Tr of the pixels Pixel (n, m +1) are used for receiving first Pixel control signals VCG (n, m +1) corresponding to the pixels of the mth column of the nth row, and the gates of the semi-floating gate transistors Tr of the pixels Pixel (n +1, m +1) are used for receiving first Pixel control signals VCG (n +1) corresponding to the pixels of the mth column of the (n +1) row and the Pixel control signals VCG (n +1) corresponding to the Pixel control signals Number VCG (n +1, m + 1);
the drains of the semi-floating gate transistors Tr of the two pixels in the mth Column are used for receiving a second pixel control signal VD (n, m) corresponding to the pixel in the mth row and the mth Column, and the drains of the two semi-floating gate transistors Tr of the two pixels in the mth Column are also electrically connected with the Current processing Column stage circuit through a pixel Column stage Current Bus Column Bus Current (m) corresponding to the pixel in the mth Column; the drains of the semi-floating gate transistors Tr of the two pixels in the (m +1) th Column are both used for receiving a second pixel control signal VD (n, m +1) corresponding to the pixels in the (n) th row and the (m +1) th Column, and the drains of the semi-floating gate transistors Tr of the two pixels in the (m +1) th Column are also electrically connected with the Current processing Column stage circuit through a pixel Column stage Current Bus Column Bus (m +1) in the (m +1) th Column; the second Voltage conversion circuit is electrically connected with the Voltage processing Column-level circuit through an m/2 Column pixel Column-level Voltage Bus Column Bus (m/2).
The second voltage conversion circuit is used for accumulating current signals output by each row of pixels of the pixel sub-array, converting the current signals into voltage signals, and respectively sampling and outputting the accumulated reset voltage and signal voltage; the second voltage conversion circuit comprises a sampling control transistor Q1(m), a sampling control transistor Q1(m +1), a level adjustment transistor Q2, an output control transistor Q3 and a sampling capacitor Cap, wherein the drains of the semi-floating gate transistors Tr of two pixels in the mth column are electrically connected with the drain of the sampling control transistor Q1(m), the drains of the semi-floating gate transistors Tr of two pixels in the (m +1) column are electrically connected with the drain of the sampling control transistor Q1(m +1), the gates of the sampling control transistor Q1(m) and the sampling control transistor Q1(m +1) are used for receiving a sampling control signal Sample, the sources of the sampling control transistor Q1(m) and the sampling control transistor Q1(m +1) are electrically connected with the positive plate of the sampling capacitor Cap, the negative plate of the sampling capacitor Cap is grounded, the drain of the level adjustment transistor Q2 is connected with a power supply voltage VCC, the grid electrode of the output control transistor Q3 is used for receiving a row selection signal Sel, the source electrode of the output control transistor Q3 is electrically connected with the Voltage processing Column stage circuit through an m/2 th Column pixel Column stage Voltage Bus Column Voltage (m/2), and the Voltage conversion gain of the second Voltage conversion circuit is determined by the capacitance value of the sampling capacitor Cap.
In this embodiment, the timings of the first pixel control signal VCG (n, m), the first pixel control signal VCG (n, m +1), the first pixel control signal VCG (n +1, m), and the first pixel control signal VCG (n +1, m +1) are all the same as the timing of the first pixel control signal VCG in embodiment 1, the timings of the second pixel control signal VD (n, m) and the second pixel control signal VD (n, m +1) are all the same as the timing of the second pixel control signal VD in embodiment 1, the timing of the sampling control signal Sample is the same as the sampling control signal Sample in embodiment 1, and the timing of the row selection signal Sel is the same as the row selection signal Sel in embodiment 1.
The operating principle of this embodiment is different from that of embodiment 1 in that the second voltage conversion circuit of this embodiment adds the photo-response signal currents in the Pixel (n, m), the Pixel (n +1, m), the Pixel (n, m +1) and the Pixel (n +1, m +1) in the sampling capacitor Cap, and then converts them into the photo-response voltage signal output, thereby completing the Binning (Binning is an image readout mode, and charges induced by adjacent pixels are added together and read out in a Pixel mode) of the output photo-response signal of the 2 × 2 Pixel array, and the other operating principles are the same as those of embodiment 1. The Binning operation can accumulate photoresponse current signals output by four semi-floating gate pixels, convert the photoresponse current signals into voltage signals and read the voltage signals, so that the sensitivity of the semi-floating gate image sensor is further increased, and imaging under a low background condition is realized.
The current processing column-level circuit and the voltage processing column-level circuit are both of the existing circuit structures, and are not described herein again; the undescribed parts of the present invention are consistent with the prior art, and are not described herein.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures made by using the contents of the present specification and the drawings can be directly or indirectly applied to other related technical fields, and are within the scope of the present invention.
Claims (8)
1. The large-dynamic-range semi-floating gate image sensor is characterized by comprising a pixel array, a current processing column-level circuit and a voltage processing column-level circuit, wherein the pixel array comprises a plurality of pixels, each pixel comprises a semi-floating gate transistor and a first voltage conversion circuit, the source electrode of the semi-floating gate transistor is grounded, the grid electrode of the semi-floating gate transistor is used for receiving a first pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor is used for receiving a second pixel control signal corresponding to the pixel, and the drain electrode of the semi-floating gate transistor is electrically connected with the current processing column-level circuit through a pixel column-level current bus corresponding to the pixel;
the drain electrode of the semi-floating gate transistor of each pixel is also electrically connected with a first voltage conversion circuit of the semi-floating gate transistor, the first voltage conversion circuit is also electrically connected with the voltage processing column-level circuit through a pixel column-level voltage bus corresponding to the pixel, and the first voltage conversion circuit is used for converting a current signal output by the semi-floating gate transistor into a voltage signal and respectively sampling and outputting a reset voltage and a signal voltage.
2. The large dynamic range semi-floating gate image sensor of claim 1, the first voltage conversion circuit comprises a sampling control transistor, a level adjusting transistor, an output control transistor and a sampling capacitor, the drain electrode of the sampling control transistor is electrically connected with the drain electrode of the semi-floating gate transistor, the grid electrode of the sampling control transistor is used for receiving a sampling control signal, the source electrode of the sampling control transistor is electrically connected with the positive plate of the sampling capacitor, the negative plate of the sampling capacitor is grounded, the drain electrode of the level adjusting transistor is connected with a power supply voltage VCC, the grid electrode of the level adjusting transistor is electrically connected with the positive plate of the sampling capacitor, the source electrode of the level adjusting transistor is electrically connected with the drain electrode of the output control transistor, the grid electrode of the output control transistor is used for receiving a row selection signal, and the source electrode of the output control transistor is electrically connected with the voltage processing column-level circuit through a pixel column-level voltage bus corresponding to the pixel.
3. The large dynamic range semi-floating gate image sensor of claim 2 in which the conversion gain of the first voltage conversion circuit is determined by the capacitance of the sampling capacitor.
4. The large dynamic range semi-floating gate image sensor of claim 2, wherein the operation process of the semi-floating gate transistor is divided into a pixel reset phase, a reset current output phase, an integration phase and a signal current output phase in time sequence;
at the initial moment of a pixel reset stage, a first pixel control signal corresponding to the pixel is at a high level, and a second pixel control signal, a sampling control signal and an output control signal corresponding to the pixel are all at a low level, so that the semi-floating gate transistor is reset;
at the initial moment of the reset current output stage, a second pixel control signal and a sampling control signal corresponding to the pixel are converted into high levels, so that the semi-floating gate transistor outputs the reset current, and the sampling capacitor is reset;
at the initial moment of the integration stage, a first pixel control signal and a sampling control signal corresponding to the pixel are converted into low levels, so that the semi-floating gate transistor is in an integration state; at the end of the integration stage, the output control signal corresponding to the pixel is firstly converted into a high level, then the sampling control signal corresponding to the pixel outputs a high level pulse, the reset voltage of the sampling capacitor is sampled, and the high level pulse is output to the voltage processing column-level circuit;
at the initial moment of the signal current output stage, a first pixel control signal corresponding to the pixel is converted into a high level, so that the semi-floating gate transistor outputs an optical response signal current, and the sampling capacitor converts the optical response signal current into an optical response signal voltage; then, the sampling control signal corresponding to the pixel outputs a high-level pulse again, samples the light response signal voltage and outputs the light response signal voltage to the voltage processing column stage circuit.
5. The large-dynamic-range semi-floating gate image sensor is characterized by comprising a pixel array, a current processing column level circuit and a voltage processing column level circuit, wherein the pixel array comprises a plurality of pixel sub-arrays, each pixel sub-array comprises a second voltage conversion circuit and a plurality of pixels, each pixel comprises a semi-floating gate transistor, the source electrode of the semi-floating gate transistor of each pixel is grounded, the grid electrode of the semi-floating gate transistor is used for receiving a first pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor of each pixel in a first row of pixels of the pixel sub-array is used for receiving a second pixel control signal corresponding to the pixel, the drain electrode of the semi-floating gate transistor of each pixel in a non-first row of pixels of the pixel sub-array is electrically connected with the drain electrode of the semi-floating gate transistor of the column of pixels in the first row of pixels, and the drain electrode of the semi-floating gate transistor of each column of the pixel in the pixel sub-array is also respectively connected with the drain electrode of The stage current bus is electrically connected with the current processing column stage circuit;
in each row of pixels of the pixel subarray, the drain of the semi-floating gate transistor of each pixel is electrically connected with a second voltage conversion circuit, the second voltage conversion circuit is also electrically connected with the voltage processing row level circuit through a pixel row level voltage bus corresponding to the pixel subarray, and the second voltage conversion circuit is used for accumulating current signals output by the pixels, converting the current signals into voltage signals, and respectively sampling and outputting the accumulated reset voltage and signal voltage.
6. The large dynamic range semi-floating gate image sensor of claim 5, wherein the second voltage conversion circuit comprises a level adjustment transistor, an output control transistor, a sampling capacitor and a plurality of sampling control transistors, each of the sampling control transistors corresponds to a column of pixels of the pixel sub-array, the drain of the semi-floating gate transistor of each column of pixels is electrically connected to the drain of the corresponding sampling control transistor, the gate of each sampling control transistor is used for receiving a sampling control signal, the source of each sampling control transistor is electrically connected to the positive plate of the sampling capacitor, the negative plate of the sampling capacitor is grounded, the drain of the level adjustment transistor is connected to a power supply voltage VCC, the gate of the level adjustment transistor is electrically connected to the positive plate of the sampling capacitor, the source of the level adjustment transistor is electrically connected to the drain of the output control transistor, and the gate of the output control transistor is used for receiving a row, the source electrodes are electrically connected with the voltage processing column-level circuit through corresponding pixel column-level voltage buses.
7. The large dynamic range semi-floating gate image sensor of claim 6 in which the conversion gain of the second voltage conversion circuit is determined by the capacitance of the sampling capacitor.
8. The large dynamic range semi-floating gate image sensor of claim 5, wherein said sub-array of pixels is a 2 x 2 array.
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