CN111596320B - High-performance anti-interference method and device - Google Patents
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
The invention discloses a high-performance anti-interference method and a high-performance anti-interference device, wherein the method comprises the following steps: receiving antenna array element signals, and preprocessing the antenna array element signals to obtain space domain signals with phase and amplitude information; according to the received M antenna array element space domain signals, each antenna array element space domain signalThe time domain delay is carried out on the antenna array element space domain signals, and each antenna array element forms P nodes, so that the M antenna array element space domain signals are converted into space-time signals X; generating a covariance matrix R of sampled data from the space-time signal XX (ii) a Covariance matrix R of sampled data by improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
According to constraint information a (theta) 0 ) And the inverse of the covariance matrix
Calculating a weight value; and filtering according to the weight information and the signals, and finally outputting an anti-interference filtering output signal Y. The invention adopts a hardware implementation mode based on FPGA and a floating point implementation mode to realize high calculation precision and flexible configuration on calculation time and resources, so that the engineering application is efficient and reasonable.
Description
Technical Field
The invention relates to the technical field of satellite navigation anti-interference, in particular to a high-performance anti-interference method and device.
Background
In the field of satellite navigation anti-interference, the array antenna is adopted for self-adaptive zeroing aiming at the compression-type interference, and the technology has a good interference suppression effect. In engineering, due to the fact that factors such as size, cost and the number of array antennas are limited, the combat requirements of complex environments cannot be met by using a simple airspace zeroing technology, and because the degree of freedom of the airspace zeroing technology is related to the number of the antennas, the number of interference which can be suppressed is limited by the number of the antennas. In the face of increasingly complex interference environments, the degrees of freedom in time domain and space domain are commonly used in a combined manner to improve the number of interference suppressions and the interference suppression capability, that is, the space-time joint and interference suppression technology. With the increase of the time domain order, the implementation complexity of the algorithm is higher and higher, so that the implementation of the algorithm becomes a focus of attention, and the LMS iterative algorithm is usually used to simplify the implementation complexity of the engineering, which is a commonly used method at present. However, the inherent disadvantages of the LMS are firstly that the weight calculation accuracy is poor and cannot approach a true solution, thereby affecting the anti-interference performance of the technique, and secondly, the algorithm has a slow convergence speed, is affected by the interference patterns and the number, and has no stable convergence time, thereby causing the anti-interference performance to be reduced in a dynamic scene.
In order to achieve the best performance of the space-time joint anti-interference technology, the processing mode of obtaining the weight by matrix inversion is the best. The method has the advantages that the weight calculation precision is high, the method approaches to a real solution, the convergence speed is stable, and the method is not influenced by interference patterns and numbers. However, in the implementation of the matrix inversion, the calculation time of the matrix inversion is poor along with the increase of the time domain order, so that the performance of the anti-interference technology is directly influenced, the requirement of engineering application cannot be met, and the application value of the matrix inversion is lost.
Disclosure of Invention
The technical problems to be solved by the invention are that the interference suppression performance of the currently common space-time joint anti-interference technology is poor and the precision is not high, and particularly the implementation mode of the related matrix inversion hardware is an implementation mode based on a DSP hardware platform, but the computation speed of the mode is slow, particularly the matrix dimension is larger and larger along with the increase of the time domain order, so that the anti-interference performance is influenced due to the difficulty in meeting the real-time requirement, and the engineering application of the implementation mode based on the DSP hardware platform is limited.
In order to break through the problem of a hardware-based large matrix inversion algorithm, the invention adopts a hardware implementation mode based on an FPGA (field programmable gate array), realizes high calculation precision by adopting a floating point implementation mode on the calculation precision, and flexibly configures calculation time and resources, so that engineering application is efficient and reasonable.
The invention is realized by the following technical scheme:
a high-performance anti-interference method comprises the following steps:
s1: receiving antenna array element signals, and preprocessing the antenna array element signals to obtain IQ space domain signals with phase and amplitude information;
s2: according to the M antenna array element space domain signals received in the step S1, time domain delay is carried out on each antenna array element space domain signal, and each antenna array element forms P nodes, so that the M antenna array element space domain signals are converted into space-time signals X = [ X ] 11 x 12 … x MP ]', where' denotes a turn rank operation;
s3: generating a covariance matrix R of the sampled data according to the space-time signal generated in the step S2 XX And sampling the data covariance matrix R XX Calculating (1);
s4: obtaining a covariance matrix R of the sampled data according to the step S3 XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
S5: according to constraint information a (theta) 0 ) And inverse of covariance matrix
And calculating the weight value by the following calculation formula:
in the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]′；a H (θ 0 ) Is a (theta) 0 ) The conjugation rank of (2);
s6: filtering according to the weight information and the signals, and finally outputting an anti-interference filtering output signal Y; wherein, the calculation formula of the filtering output signal Y is as follows:
in the formula
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 … x MP ]′。
The working principle is as follows:
the space-time joint anti-interference technology is theoretically realized by adopting an algorithm based on sampling covariance matrix inversion, the calculation result of the space-time joint anti-interference technology is most approximate to a real solution, on one hand, error influence factors caused by realization are greatly reduced, and on the other hand, the space-time joint anti-interference technology is different from an implementation mode of LMS open loop iteration, the implementation mode is a closed loop solving process, the convergence speed is stable, only depends on the calculation time delay of the algorithm, is not influenced by interference patterns and numbers, and avoids the influence factor of unstable convergence speed caused by external interference scene change. From the above analysis, the algorithm based on sampling covariance matrix inversion has the advantages of high solving precision, approaching to a theoretical result, stable convergence speed, stable performance in a dynamic change scene, and greatly improved interference suppression performance of the space-time joint anti-interference technology. Therefore, how to realize a hardware-based large matrix inversion algorithm is the key, and the calculation accuracy and the real-time performance of the algorithm are required to be met.
In order to make up for the defects of the technology, the FPGA is adopted to realize the matrix inversion algorithm, the bottleneck of engineering application is broken through, the high-precision and high-real-time performance is met, the performance of the space-time joint anti-interference technology is optimized, the anti-interference overall performance is improved, the engineering can be used, the problem that the conventional DSP is used for realizing the matrix inversion algorithm is broken through, the calculation speed has a huge advantage relative to the DSP along with the increase of the matrix dimension, and the FPGA can be designed to be stable in calculation precision, speed and hardware resources and have the advantage that the DSP cannot compare.
In order to break through the problem of a hardware-based large matrix inversion algorithm, the invention adopts a hardware implementation mode based on the FPGA, realizes high calculation precision by adopting a floating point implementation mode on the calculation precision, and flexibly configures the calculation time and resources, so that the engineering application is efficient and reasonable.
Further, the covariance matrix R of the sampled data in step S3 XX The calculation of (3) is to adopt sampling data discontinuous sampling points to carry out flow design processing and control the sampling data discontinuous sampling points by setting a distance parameter; wherein the sampling interval is set to M × P.
Further, step S3 comprises the following sub-steps:
step 3.1: performing cross-correlation multiplication processing on the space-time signals obtained in the step S2 to obtain a cross-correlation matrix formed at a sampling moment, wherein the calculation mode is X X X H Wherein X is H Represents the conjugate transition rank of X;
step 3.2: selecting L discontinuous sampling points at intervals set as M x P according to the cross-correlation matrix obtained in the step 3.1;
step 3.3: accumulating the sampling point data, and averaging to obtain an S = M × P dimensional covariance matrix R XX 。
Further, step S4 comprises the following sub-steps:
step 4.1: the covariance matrix R obtained in step S3 XX Converting into a lower triangular matrix, specifically comprising:
step 4.1.1: the covariance matrix R XX Splicing the real and imaginary parts of the data, SConverting the dimension complex matrix into a 2S dimension real matrix;
step 4.1.2: caching the spliced data in a block RAM memory in an FPGA programming device;
step 4.1.3: recombining the data cached by the RAM to obtain a lower triangular matrix of the 2S-dimensional real matrix;
step 4.2: performing a lower triangle inversion algorithm on the lower triangle matrix obtained in the step 4.1;
step 4.3: performing square matrix transformation processing on the inverse lower triangular matrix obtained in the step 4.2 to obtain an inverse matrix; the method specifically comprises the following steps:
step 4.3.1: caching the inverse lower triangular array data in an RAM memory;
step 4.3.2: the cache data is recombined to obtain the real part and the imaginary part of the square matrix, namely
Further, step 4.2 specifically comprises the following substeps:
step 4.2.1: converting the integer input data elements of the lower triangular matrix in the step 4.1 into floating point data, and storing the floating point data in a floating point matrix A; turning to step 4.2.3;
step 4.2.2: initializing a variable k [ N ] (N =1,2, \ 8230;, N), k [ N ] = 2S-N: (N-1); turning to step 4.2.3;
step 4.2.3: n parallel floating point inversion designs are adopted, wherein N represents parameters, flexible configuration is carried out according to hardware resources, and N is more than or equal to 1 and less than or equal to 2S are effective parameters; the method specifically comprises the following steps:
step 4.2.3.1: a variable k [ n ] distribution control that accepts the data of step 4.2.2 for the first iteration and accepts the data of step 4.2.6 for subsequent iterations;
step 4.2.3.2: updating data of N floating point input modules; for the 1 st data update, when the data of the step 4.2.1 is accepted in the first iteration as the N +1 th data update accepted in the 1 st data update in the subsequent iteration; updating the output of the (N-1) th floating point inversion module as the nth data for N =2,3., N + 1;
step 4.2.3.3: when the input data updating and variable k [ N ] (N =1,2, \ 8230; N) of the N floating point inversion modules are all updated, the N (N =1,2, \ 8230; N) inversion modules are subjected to inversion; turning to step 4.2.4;
step 4.2.4: performing floating point inversion processing, specifically:
step 4.2.4.1: matrix singular judgment: when A (1, 1) =0, a singularity flag is given, otherwise, the step 4.2.4.2 is carried out;
step 4.2.4.2: taking out input data A (1, 1), calculating p =1/A (1, 1), and finishing floating-point division; turning to step 4.2.4.3;
step 4.2.4.3: initializing a loop variable i, wherein i =2; the following is performed:
step 4.2.4.3.1: storing the matrix in a RAM memory, wherein q = A (i, 1), calculating qp = q × p, completing floating-point multiplication, and turning to step 4.2.4.3.2;
step 4.2.4.3.2: judging i and k, and calculating h; h = qp when i > = k; h = -qp when i < k; turning to step 4.2.4.3.3;
step 4.2.4.3.3: loop variable j is initialized, j =2; turning to step 4.2.4.3.3.1;
step 4.2.4.3.3.1: caching h in a RAM memory, and calculating qh, qh (i, j) = q h (j); turning to step 4.2.4.3.3.2;
step 4.2.4.3.3.2: storing the matrix and qh in a RAM memory, and calculating A (i-1, j-1), A (i-1, j-1) = A (i, j) + qh (i, j); step 4.2.4.3.3.3;
step 4.2.4.3.3.3: j = j +1, go to step 4.2.4.3.3.4;
step 4.2.4.3.3.4: judging j condition, and turning to step 4.2.4.3.3.1 when j < = i; otherwise, turning to the step 4.2.4.3.4;
step 4.2.4.3.4: i = i +1, go to step 4.2.4.3.5;
step 4.2.4.3.5: judging the condition of i, and turning to the step 4.2.4.3.1 when i < = 2S; otherwise, turning to the step 4.2.4.4;
step 4.2.4.4: initializing a loop variable m, wherein m =2; turning to step 4.2.4.4.1;
step 4.2.4.4.1: updating the matrix A (2S, m-1) = h (m), and turning to the step 4.2.4.4.2;
step 4.2.4.4.2: m = m +1, go to step 4.2.3.4.3;
step 4.2.4.4.3: judging the m condition, and turning to the step 4.2.4.4.1 when m < = 2S; otherwise, turning to the step 4.2.4.5;
step 4.2.4.5: updating the matrix A (2S, 2S) = p, and turning to the step 4.2.4.6;
step 4.2.4.6: outputting A, and turning to the step 4.2.5;
step 4.2.5: judging the condition of k [ N ] (N =1,2, \ 8230;, N), and turning to step 4.2.6 when k [ N ] = 1; otherwise, turning to the step 4.2.7;
step 4.2.6: k [ N ] = k [ N ] -1, N =1,2, \8230; turning to step 4.2.3.1;
step 4.2.7: the value of the (N + 1) th (N =1,2, \ 8230;, N) data update is output as the inverse lower triangle, and step 4.3 is performed.
On the other hand, the invention also provides a high-performance anti-interference device, which supports the high-performance anti-interference method and is a device for realizing the high-performance anti-interference method based on FPGA hardware; the device comprises a receiving and preprocessing module, a space-domain space-time signal processing single module, a covariance matrix generating module, a covariance matrix inversion module, a weight calculation and signal filtering processing module and an output module, wherein:
the receiving and preprocessing module is used for receiving the antenna array element signals and preprocessing the antenna array element signals to obtain IQ spatial domain signals with phase and amplitude information;
the space-to-space signal processing single module is used for carrying out time domain delay on the space domain signal of each antenna array element according to the space domain signals of the M antenna array elements received by the receiving and preprocessing module, and each antenna array element forms P nodes, so that the space domain signals of the M antenna array elements are converted into space-time signals X = [ X ] X 11 x 12 … x MP ]', where' denotes a turn rank operation;
the covariance matrix generation module is used for generating a sampling data covariance matrix R according to the space-time signals generated by the space-time signal processing single module XX And performing a covariance matrix R of the sampled data XX Calculating (1);
the covariance matrix inversion module is used for generating a covariance matrix R of the sampled data according to the covariance matrix XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
The weight calculation and signal filtering processing module is used for calculating the weight according to the external constraint information a (theta) 0 ) And the inverse of the covariance matrix obtained by the covariance matrix inverse module
To calculate the weight value, the calculation formula is
In the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]′；a H (q 0 ) Is a (theta) 0 ) The conjugation rank of (2);
and the filtering device is used for carrying out filtering processing according to the weight information and the signals, and the calculation formula of the filtering signal Y is as follows:
in the formula>
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 …x MP ]′；
And the output module is used for finally outputting the filtering signal Y processed by the weight calculation and signal filtering processing module and outputting the filtering signal Y after interference resistance.
Further, the covariance matrix inversion module comprises a lower triangular matrix unit, a lower triangular matrix inversion unit and an inverse lower triangular matrix square matrix unit, wherein:
the above-mentionedDown-conversion of a triangular matrix unit for transforming the covariance matrix R XX Splicing the real part and the imaginary part of the data, and converting the S-dimensional complex matrix into a 2S-dimensional real matrix; caching the spliced data in a block RAM memory in an FPGA programming device; recombining the data cached by the RAM to obtain a lower triangular matrix of the 2S-dimensional real matrix;
the lower triangular matrix inversion unit is used for converting integer data of the lower triangular matrix conversion unit into double-precision floating point data, adopts a design of parallel processing of N floating point inversion modules, and flexibly configures according to hardware resources, wherein N is more than or equal to 1 and less than or equal to 2S and is an effective parameter N; the method specifically comprises the steps of initializing a variable k [ N ] (N =1,2, \ 8230;, N), updating the variable k [ N ], judging the condition of k [ N ] =1, and controlling the updating and output control of input data of an output inverse lower triangular matrix and N floating point inversion modules;
the inverse lower triangular matrix to square matrix unit is used for caching the inverse lower triangular matrix data in the RAM memory and recombining the cached data to obtain the real part and the imaginary part of the square matrix, namely the real part and the imaginary part of the square matrix
And the RAM is used for storing the antenna array element signal data and the intermediate processing stage data.
The method adopts the following six key design points:
(1) The sampling covariance matrix is formed by adopting discontinuous sampling data, so that the resource is reduced, and data statistics in a longer time can be obtained at the same time, thus the characteristic of the sampling data covariance matrix is closer to the theoretical array covariance matrix, and the anti-interference performance is better.
(2) The sampling interval is set to M x P, the time domain order and the streamline design of the algorithm are considered, the calculation of one row of elements of the covariance matrix is completed at each sampling moment, the continuity of the data in time is basically kept, and the discontinuity of the data is not increased due to the time domain delay though the data is similar to the separated data.
(3) According to the characteristic of symmetry of a covariance matrix formed by sampling data, the inversion in the scheme adopts lower triangular operation to replace the operation of the whole matrix, so that the operation amount is reduced, the calculation processing speed is improved, and the purpose of enhancing the real-time property is achieved.
(4) It can be seen from fig. 5 that the design of parallel processing is adopted, flexible configuration can be performed according to hardware resources, N being greater than or equal to 1 and less than or equal to 2S are all configurations of effective parameters N, the closer the value of N is to 2S, the higher the parallelism is, the higher the processing speed is, but the greater the resource consumption is. Therefore, the scheme can flexibly configure the parameter N according to the resource condition of hardware, and compromise between resources and speed is achieved.
(5) The conversion of the matrix into the lower triangular matrix and the conversion of the lower triangular matrix into the square matrix are realized by adopting the design of the RAM, and meanwhile, the matrix is converted into a required data form according to the requirement by adopting the serial-parallel data conversion design, so that the flexible and changeable design can be realized, and the design can be modified according to the resource condition.
(6) And the floating point inversion design is adopted, the accuracy of inversion calculation is ensured, and the calculation error is consistent with MATLAB. The interference resistance is prevented from being influenced by errors generated by traditional FPGA integer data processing, and the interference resistance is further ensured.
According to the high-performance anti-interference method realized based on hardware after the processing of the six points, the bottleneck problem of real-time property of engineering application is broken through, the real-time property is met, the weight value approaches to a theoretical result, the calculation error is consistent with MATLAB, and therefore the anti-interference performance of the scheme achieves the effect of consistent MATLAB simulation. The design adopts an array covariance matrix based on a sampling data covariance matrix to replace the theory, so that a plurality of sampling points are needed to enable the characteristic of the sampling data covariance matrix to be better, the scheme is formed by adopting discontinuous data, the discontinuous interval is set to be M x P, the storage resource of hardware can be reduced as much as possible, simultaneously, more sample points are provided as much as possible, and the time continuity is basically kept, so that the characteristic of the sampling data covariance matrix approaches the characteristic of a theoretical value. And secondly, the problems of resources and speed are solved by setting a parallelism parameter in the implementation, so that different hardware can be flexibly configured, and the engineering application flexibility is high. Therefore, the scheme achieves the optimal result no matter in calculation error, data characteristic and calculation processing time, and the anti-interference performance of the algorithm is close to the theoretical result. The high-performance anti-interference method realized based on hardware can be applied to the same type or other products, and the technical means cannot be avoided.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the method and the device break through the bottleneck problem of real-time property of engineering application, achieve the effect of meeting the real-time property and enabling the weight to approach the theoretical result, and the calculation error of the method and the device is consistent with MATLAB, so the anti-interference performance of the scheme achieves the effect of consistent MATLAB simulation. The design adopts an array covariance matrix based on a sampling data covariance matrix to replace the theory, so that a plurality of sampling points are needed to enable the characteristic of the sampling data covariance matrix to be better, the scheme is formed by adopting discontinuous data, the discontinuous interval is set to be M x P, the storage resource of hardware can be reduced as much as possible, simultaneously, more sample points are provided as much as possible, and the time continuity is basically kept, so that the characteristic of the sampling data covariance matrix approaches the characteristic of a theoretical value. And secondly, the problems of resources and speed are solved by setting a parallelism parameter in the implementation, so that different hardware can be flexibly configured, and the engineering application flexibility is high. Therefore, the scheme of the invention achieves the optimal calculation error, data characteristic and calculation processing time, and the anti-interference performance of the algorithm is close to the theoretical result.
2. The invention adopts a hardware implementation mode based on FPGA, realizes high calculation precision by adopting a floating point implementation mode on the calculation precision, and flexibly configures the calculation time and resources, thereby ensuring that the engineering application is efficient and reasonable.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a flow chart of a high-performance anti-interference method according to the present invention.
Fig. 2 is a flow chart of an implementation of covariance matrix generation according to the present invention.
FIG. 3 is a flowchart of the inverse implementation of the covariance matrix of the present invention.
FIG. 4 is a flow chart of the implementation of the lower triangular matrix according to the present invention.
FIG. 5 is a flowchart illustrating an implementation of the lower triangular inversion algorithm of the present invention.
FIG. 6 is a flowchart illustrating an implementation of the floating-point inversion algorithm of the present invention.
Fig. 7 is a flow chart of the implementation of the inverse lower triangular matrix to square matrix according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
As shown in fig. 1 to fig. 7, a flowchart of a specific implementation of the high-performance anti-interference method according to the present invention is shown in fig. 1; the whole implementation steps are as follows:
step 1: receiving antenna array element signals, and preprocessing the antenna array element signals to obtain IQ space domain signals with phase and amplitude information; and (6) turning to the step 2.
Step 2: according to the M antenna array element space domain signals received in the step 1, time domain delay is carried out on each antenna array element space domain signal, and each antenna array element forms P nodes, so that the M antenna array element space domain signals are converted into space-time signals X = [ X ] 11 x 12 … x MP ]', where' denotes a turn rank operation; and (6) turning to the step 3.
And 3, step 3: generating a sampling data covariance matrix R according to the space-time signal generated in the step 2 XX And performing a covariance matrix R of the sampled data XX Calculating (1); the covariance matrix generation flow chart is shown in fig. 2. Go to step 3.1.
Step 3.1: performing cross-correlation multiplication processing on the space-time signals obtained in the step (2) to obtain a cross-correlation matrix formed at a sampling moment, and calculating the cross-correlation matrix in a calculation modeIs X X H Wherein X is H Represents the conjugate transition rank of X; go to step 3.2.
Step 3.2: selecting L discontinuous sampling points at intervals set as M x P according to the cross-correlation matrix obtained in the step 3.1; go to step 3.3.
Step 3.3: after data accumulation, averaging is carried out to obtain the covariance matrix R with the dimension of S = M × P XX Go to step 4.
And 4, step 4: obtaining a covariance matrix R of the sampled data according to the step 3 XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
A flow chart of the covariance matrix inversion algorithm is shown in fig. 3. Go to step 4.1.
Step 4.1: the covariance matrix is subjected to a down-triangle process, which is a flowchart, as shown in fig. 4. Go to step 4.2.
Step 4.1.1: and splicing the real part and the imaginary part of the covariance matrix data, and changing the S-dimensional complex matrix into a 2S-dimensional real matrix. Go to step 4.1.2.
Step 4.1.2: and caching the spliced data in a block RAM in the FPGA. Go to step 4.1.3.
Step 4.1.3: and recombining the data cached by the RAM to obtain a lower triangular matrix of the 2S-dimensional real matrix. Step 4.2
And 4.2: and (5) performing a lower triangle inversion algorithm on the lower triangle matrix, wherein the algorithm processing flow is shown in figure 5. Go to step 4.2.1.
Step 4.2.1: and converting the integer input data elements into floating point data, and storing the floating point data in the floating point matrix A. Go to step 4.2.3.
Step 4.2.2: the variable k [ N ] (N =1,2, \8230;, N) is initialized, k [ N ] =2S-N (N-1). Go to step 4.2.3.
Step 4.2.3: n parallel floating point inversion designs are provided, wherein N represents parameters, the parameters can be flexibly configured according to hardware resources, and N is more than or equal to 1 and less than or equal to 2S and is an effective parameter. Go to step 4.2.3.1.
Step 4.2.3.1: the variable k n distributes control accepting data from step 4.2.2 for the first iteration and accepting data from step 4.2.6 for subsequent iterations. Go to step 4.2.3.2.
Step 4.2.3.2: and updating data of the N floating point input modules. For the 1 st data update, the data of step 4.2.1 is accepted on the first iteration as the N +1 th update data for the 1 st data update on the following iteration. For N =2,3., N +1, the output of the N-1 floating point inversion module is updated as the nth data. Go to step 4.2.3.3.
Step 4.2.3.3: when the input data update of N floating point inversion modules and the variable k [ N ] (N =1,2, \8230;, N) are all updated, the step 4.2.4 is carried out on the nth (N =1,2, \8230;, N) inversion module.
Step 4.2.4: floating point inversion processing, a flow chart of floating point inversion processing, is shown in fig. 6. Go to step 4.2.4.1.
Step 4.2.4.1: and matrix singular judgment. When a (1, 1) =0, a singularity flag is given, otherwise, step 4.2.4.2 is switched to.
Step 4.2.4.2: the input data a (1, 1) is fetched, p =1/a (1, 1) is calculated, and floating-point division is completed. Go to step 4.2.4.3.
Step 4.2.4.3: loop variable i is initialized, i =2. Go to step 4.2.4.3.1.
Step 4.2.4.3.1: storing the matrix in RAM, q = A (i, 1), calculating qp = q × p, and completing the floating-point multiplication. Go to step 4.2.4.3.2.
Step 4.2.4.3.2: and judging i and k, and calculating h. H = qp when i > = k; h = -qp when i < k; . Go to step 4.2.4.3.3.
Step 4.2.4.3.3: loop variable j is initialized, j =2. Go to step 4.2.4.3.3.1.
Step 4.2.4.3.3.1: caching h in a RAM, and calculating qh, qh (i, j) = q h (j). Go to step 4.2.4.3.3.2.
Step 4.2.4.3.3.2: the matrices and qh are stored in RAM, and A (i-1, j-1), A (i-1, j-1) = A (i, j) + qh (i, j) are calculated. Go to step 4.2.4.3.3.3.
Step 4.2.4.3.3.3: j = j + 1. Go to step 4.2.4.3.3.4.
Step 4.2.4.3.3.4: judging j condition, and turning to step 4.2.4.3.3.1 when j < = i; otherwise, go to step 4.2.4.3.4.
Step 4.2.4.3.4: i = i +1. Go to step 4.2.4.3.5
Step 4.2.4.3.5: and judging the condition of i, and turning to the step 4.2.4.3.1 when i < = 2S. Otherwise, go to step 4.2.4.4
Step 4.2.4.4: loop variable m is initialized, m =2. Go to step 4.2.4.4.1.
Step 4.2.4.4.1: update matrix a (2s, m-1) = h (m). Go to step 4.2.4.4.2
Step 4.2.4.4.2: m = m +1. Go to step 4.2.3.4.3
Step 4.2.4.4.3: and m conditions judge that when m < =2S, the step 4.2.4.4.1 is carried out. Otherwise, go to step 4.2.4.5
Step 4.2.4.5: update matrix a (2s, 2s) = p. Go to step 4.2.4.6
Step 4.2.4.6: and outputting A. Go to step 4.2.5
Step 4.2.5: judging the condition of k [ N ] (N =1,2, \ 8230;, N), and turning to step 4.2.6 when k [ N ] = 1; otherwise go to step 4.2.7.
Step 4.2.6: k [ N ] = k [ N ] -1, N =1,2, \ 8230;, N. Go to step 4.2.3.1
Step 4.2.7: the value of the (N + 1) th (N =1,2, \ 8230;, N) data update is output as the inverse lower triangle. Step 4.3
Step 4.3: and (5) performing square matrix conversion processing on the inverse lower triangular matrix to obtain an inverse matrix, wherein a processing flow chart is shown in figure 7. Go to step 4.3.1.
Step 4.3.1: and caching the reverse lower triangular array data in a RAM. Go to step 4.3.2.
Step 4.3.2: the buffer data is recombined to obtain the real part and the imaginary part of the square matrix, namely
And (5) turning to the step.
S5: according to constraint information a (theta) 0 ) And the inverse of the covariance matrix
And calculating the weight value by the following calculation formula:
in the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]；a H (θ 0 ) Is a (theta) 0 ) The conjugation rank of (2); and 6, turning to the step 6.
S6: filtering according to the weight information and the signals, and finally outputting an anti-interference filtering output signal Y; wherein, the calculation formula of the filtering output signal Y is as follows:
in the formula
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 … x MP ]′。
When in implementation: FIG. 1 is a flow chart of a high-performance anti-interference method based on hardware implementation, which explains the whole processing flow, and the invention first preprocesses through AD sampling signals to obtain IQ signals with amplitude and phase; second, the covariance matrix R of the sampled data XX The calculation of (3) is carried out by adopting sampling data discontinuous sampling points to carry out flow design processing and controlling by setting space parameters, so that the hardware resources are less, and the formed R XX The purpose of good data characteristics. Then, according to R XX The inversion of the lower triangular processing is adopted to achieve the purpose of full data inversion, and the calculation processing time is reduced; specifically, R is XX Performing down-triangle conversion, performing down-triangle matrix inversion, and performing square matrix conversion on the result of the down-triangle inversion to obtain
Furthermore, known constraint information a (θ) is utilized according to equation (1) 0 ) Sum covarianceInverse of a matrix>
Calculating the weight w opt . Finally, the obtained weight w is utilized according to the formula (2) opt And calculating the anti-interference filtered signal.
FIG. 2 is a flowchart of covariance matrix generation, and it can be seen from the diagram that space-time cross-correlation multiplication is performed on space-time signals to obtain a cross-correlation matrix at a moment, then data accumulation is performed on the cross-correlation matrices of L sampling points, and finally an accumulation result is averaged to obtain an estimated value R of an S-dimensional covariance matrix XX Then R is added XX And outputting in parallel according to rows.
Fig. 3 is a flowchart of the covariance matrix inversion algorithm, and it can be seen from the diagram that the covariance matrix is firstly converted into a lower triangular matrix by using the symmetry of the covariance matrix, then the lower triangular matrix inversion algorithm is performed, and finally the inverted lower triangular matrix is converted into a square matrix.
Fig. 4 is a flowchart for implementing the lower triangular matrix, which describes the whole process flow, specifically including the following process flows:
1. covariance matrix R to be output by row XX The real part and the imaginary part of the data are positioned at a lower part and the real part is positioned at a higher part according to the imaginary part, and data splicing is carried out to realize that the S-dimensional complex matrix is changed into a 2S-dimensional real matrix;
2. performing RAM data caching on the spliced 2S-dimensional real number matrix data, and realizing data registration by controlling read-write addresses;
3. and (4) controlling the address of the data by the registered data, reading the required data, and outputting the data of the lower triangular matrix according to the row flow.
Fig. 5 is a flowchart of an implementation of the lower triangular inversion algorithm, which describes the entire process flow, specifically including the following process flows:
1. converting the integer data into double-precision floating point data;
2. the design of parallel processing of N floating point inversion modules is adopted, flexible configuration can be carried out according to hardware resources, N is more than or equal to 1 and less than or equal to 2S, and the N is an effective parameter N, wherein the key part is as follows: initialization of a variable k [ N ] (N =1,2, \ 8230;, N), update of the variable k [ N ], and condition judgment of k [ N ] =1, and control of update and output of input data of the output inverse lower triangular matrix and the N floating point inversion modules.
FIG. 6 is a flowchart of an implementation of a floating point inversion algorithm. The key part comprises matrix singular judgment, namely detection A (1, 1) =0, control of storage and reading of a floating-point matrix, initialization of cyclic variables I, j and m and judgment of updating and ending marks, processing of data by floating-point division, floating-point multiplication and floating-point addition, and iterative updating of the floating-point matrix A.
Fig. 7 is a flowchart of implementing inverse lower angle matrix-to-square matrix. It can be seen from the figure that the inverse lower triangular matrix is firstly cached in the RAM, then the data is taken out according to the read-write control, and finally the data is recombined to output the inverse matrix.
The invention adopts a hardware implementation mode based on FPGA, realizes high calculation precision by adopting a floating point implementation mode on the calculation precision, and flexibly configures the calculation time and resources so as to ensure that the engineering application is efficient and reasonable.
Example 2
As shown in fig. 1 to fig. 7, the present embodiment is different from embodiment 1 in that the present embodiment provides a high-performance anti-interference apparatus, which supports the high-performance anti-interference method of embodiment 1, and is an apparatus for implementing the high-performance anti-interference method of embodiment 1 based on FPGA hardware; the device comprises a receiving and preprocessing module, a space-domain space-time signal processing single module, a covariance matrix generating module, a covariance matrix inversion module, a weight calculation and signal filtering processing module and an output module, wherein:
the receiving and preprocessing module is used for receiving the antenna array element signals and preprocessing the antenna array element signals to obtain IQ space domain signals with phase and amplitude information;
the space-to-space signal processing single module is used for carrying out time domain delay on the space domain signal of each antenna array element according to the M antenna array element space domain signals received by the receiving and preprocessing module, and each antenna array element space domain signal is subjected to time domain delayP nodes are formed by the antenna array elements, so that space-domain signals of the M antenna array elements are converted into space-time signals X = [ X = [) 11 x 12 … x MP ]', where' denotes a turn rank operation;
the covariance matrix generation module is used for generating a sampling data covariance matrix R according to the space-time signals generated by the space-time signal processing single module XX And performing a covariance matrix R of the sampled data XX Calculating (1);
the covariance matrix inversion module is used for generating a covariance matrix R of the sampled data according to the covariance matrix obtained by the covariance matrix generation module XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
The weight calculation and signal filtering processing module is used for calculating the weight according to the external constraint information a (theta) 0 ) And the inverse of the covariance matrix obtained by the covariance matrix inversion module
To calculate the weight value, the calculation formula is
In the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]′；a H (θ 0 ) Is a (theta) 0 ) The conjugation rank of (2);
and the filtering device is used for carrying out filtering processing according to the weight information and the signals, and the calculation formula of the filtering signal Y is as follows:
in the formula>
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 …x MP ]′；
And the output module is used for finally outputting the filtering signal Y processed by the weight calculation and signal filtering processing module and outputting the filtering signal Y after interference resistance.
Specifically, the covariance matrix inversion module includes a lower triangular matrix unit, a lower triangular matrix inversion unit and an inverse lower triangular matrix square matrix unit, wherein:
the down-conversion triangular matrix unit is used for converting the covariance matrix R XX Splicing the real part and the imaginary part of the data, and converting the S-dimensional complex matrix into a 2S-dimensional real matrix; caching the spliced data in a block RAM memory in an FPGA programming device; recombining the data cached by the RAM memory to obtain a lower triangular matrix of the 2S-dimensional real matrix;
the lower triangular matrix inversion unit is used for converting integer data of the lower triangular matrix conversion unit into double-precision floating point data, adopts a design of parallel processing of N floating point inversion modules, and flexibly configures according to hardware resources, wherein N is more than or equal to 1 and less than or equal to 2S and is an effective parameter N; the method specifically comprises the steps of initializing a variable k [ N ] (N =1,2, \ 8230;, N), updating the variable k [ N ], judging the condition of k [ N ] =1, and controlling the updating and output control of input data of an output inverse lower triangular matrix and N floating point inversion modules;
the inverse lower triangular matrix to square matrix unit is used for caching the inverse lower triangular matrix data in the RAM memory and recombining the cached data to obtain the real part and the imaginary part of the square matrix, namely the real part and the imaginary part of the square matrix
/>
The device for realizing the high-performance anti-interference method based on hardware breaks through the bottleneck problem of real-time property of engineering application, meets the real-time property, enables the weight value to approach the theoretical result, and has the calculation error consistent with MATLAB, so the anti-interference performance of the scheme achieves the effect of consistent MATLAB simulation. The design of the invention adopts the array covariance matrix based on the covariance matrix of the sampled data to replace the theory, so that a plurality of sampling points are needed to ensure that the characteristic of the covariance matrix of the sampled data is better, the scheme is formed by adopting discontinuous data, the discontinuous interval is set as M P, the storage resource of hardware can be reduced as much as possible, simultaneously, more sample points are provided as much as possible, and the continuity in time is basically kept, so that the characteristic of the covariance matrix of the sampled data approaches the characteristic of the theoretical value. And secondly, the problems of resources and speed are solved by setting a parallelism parameter in the implementation, so that different hardware can be flexibly configured, and the engineering application flexibility is high. Therefore, the scheme achieves the optimal result no matter in calculation error, data characteristic and calculation processing time, and the anti-interference performance of the algorithm is close to the theoretical result. The high-performance anti-interference method realized based on hardware can be applied to the same type or other products, and the technical means cannot be avoided.
The invention adopts a hardware implementation mode based on FPGA, realizes high calculation precision by adopting a floating point implementation mode on the calculation precision, and flexibly configures the calculation time and resources, thereby ensuring that the engineering application is efficient and reasonable.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A high-performance anti-interference method is characterized by comprising the following steps:
s1: receiving antenna array element signals, and preprocessing the antenna array element signals to obtain IQ space domain signals with phase and amplitude information;
s2: according to the M antenna array element space domain signals received in the step S1, time domain delay is carried out on each antenna array element space domain signal, and each antenna array element forms P nodes, so that the M antenna array element space domain signals are converted into space-time signals X = [ X ] 11 x 12 … x MP ]', whereinPerforming a rotation rank indication operation;
s3: generating a sampling data covariance matrix R according to the space-time signal generated in the step S2 XX And performing a covariance matrix R of the sampled data XX Calculating (1);
s4: obtaining a covariance matrix R of the sampled data according to the step S3 XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
S5: according to the constraint information a (theta) 0 ) And the inverse of the covariance matrix
And calculating the weight value by the following calculation formula:
in the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]′；a H (θ 0 ) Is a (theta) 0 ) The conjugation rank of (2);
s6: filtering according to the weight information and the signals, and finally outputting an anti-interference filtering output signal Y; wherein, the calculation formula of the filtering output signal Y is as follows:
in the formula
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 … x MP ]′；
Step S4 includes the following substeps:
step 4.1: the covariance matrix R obtained in step S3 XX Converting into a lower triangular matrix; the method specifically comprises the following steps:
step 4.1.1: the covariance matrix R XX Splicing the real part and the imaginary part of the data, and converting the S-dimensional complex matrix into a 2S-dimensional real matrix;
step 4.1.2: caching the spliced data in a block RAM memory in an FPGA programming device;
step 4.1.3: recombining the data cached by the RAM to obtain a lower triangular matrix of the 2S-dimensional real matrix;
step 4.2: performing a lower triangle inversion algorithm on the lower triangle matrix obtained in the step 4.1;
step 4.3: performing square matrix transformation processing on the inverse lower triangular matrix obtained in the step 4.2 to obtain an inverse matrix; the method specifically comprises the following steps:
step 4.3.1: caching the inverse lower triangular array data in an RAM memory;
step 4.3.2: the cache data is recombined to obtain the real part and the imaginary part of the square matrix, namely
Step 4.2 specifically comprises the following substeps:
step 4.2.1: converting integral input data elements of the lower triangular matrix in the step 4.1 into floating point data, and storing the floating point data in a floating point matrix A; turning to step 4.2.2;
step 4.2.2: the variable k [ n ]; n =1,2, \ 8230;, N; initialization, k [ N ] =2S-N (N-1); turning to step 4.2.3;
step 4.2.3: n parallel floating point inversion designs are adopted, wherein N represents parameters, flexible configuration is carried out according to hardware resources, and N is more than or equal to 1 and less than or equal to 2S are effective parameters; the method specifically comprises the following steps:
step 4.2.3.1: a variable k [ n ] distribution control that accepts the data of step 4.2.2 for the first iteration and accepts the data of step 4.2.6 for subsequent iterations;
step 4.2.3.2: updating data of N floating point input modules; for the 1 st data update, when the data of the step 4.2.1 is accepted in the first iteration as the N +1 th data update accepted in the 1 st data update in the subsequent iteration; updating the output of the N-1 floating point inversion module as the nth data for N =2,3., N + 1;
step 4.2.3.3: when the input data of the N floating point inversion modules are updated, a sum variable k [ N ]; n =1,2, \8230, N; after all the updating is finished, the nth inversion module is used; turning to step 4.2.4;
step 4.2.4: performing floating point inversion processing, specifically:
step 4.2.4.1: matrix singular judgment: when A (1, 1) =0, a singularity mark is given, otherwise, the step 4.2.4.2 is carried out;
step 4.2.4.2: taking out input data A (1, 1), calculating p =1/A (1, 1), and finishing floating-point division; turning to step 4.2.4.3;
step 4.2.4.3: initializing a loop variable i, wherein i =2; the following is performed:
step 4.2.4.3.1: storing the matrix in a RAM memory, wherein q = A (i, 1), calculating qp = q × p, completing floating-point multiplication, and turning to step 4.2.4.3.2;
step 4.2.4.3.2: judging i and k, and calculating h; h = qp when i > = k; h = -qp when i < k; step 4.2.4.3.3 is carried out;
step 4.2.4.3.3: loop variable j is initialized, j =2; turning to step 4.2.4.3.3.1;
step 4.2.4.3.3.1: caching h in a RAM memory, and calculating qh, qh (i, j) = q h (j); turning to step 4.2.4.3.3.2;
step 4.2.4.3.3.2: storing the matrix and qh in a RAM memory, and calculating A (i-1, j-1), A (i-1, j-1) = A (i, j) + qh (i, j); turning to step 4.2.4.3.3.3;
step 4.2.4.3.3.3: j = j +1, go to step 4.2.4.3.3.4;
step 4.2.4.3.3.4: judging j condition, and turning to step 4.2.4.3.3.1 when j < = i; otherwise, turning to the step 4.2.4.3.4;
step 4.2.4.3.4: i = i +1, go to step 4.2.4.3.5;
step 4.2.4.3.5: judging the condition of i, and turning to the step 4.2.4.3.1 when i < = 2S; otherwise, turning to the step 4.2.4.4;
step 4.2.4.4: initializing a loop variable m, wherein m =2; turning to step 4.2.4.4.1;
step 4.2.4.4.1: updating the matrix A (2S, m-1) = h (m), and turning to the step 4.2.4.4.2;
step 4.2.4.4.2: m = m +1, go to step 4.2.3.4.3;
step 4.2.4.4.3: judging the m condition, and turning to the step 4.2.4.4.1 when m < = 2S; otherwise, turning to the step 4.2.4.5;
step 4.2.4.5: updating the matrix A (2S, 2S) = p, and turning to the step 4.2.4.6;
step 4.2.4.6: outputting A, and turning to the step 4.2.5;
step 4.2.5: judging the condition of k [ N ], N =1,2, \ 8230; go to step 4.2.6 when k [ n ] = 1; otherwise, turning to the step 4.2.7;
step 4.2.6: k [ N ] = k [ N ] -1, N =1,2, \8230; turning to step 4.2.3.1;
step 4.2.7: outputting the value of the N +1 th data update as an inverse lower triangle, N =1,2, \8230;, N; go to step 4.3.
2. The method of claim 1, wherein the covariance matrix R of the sampled data in step S3 XX The calculation of (3) is to adopt sampling data discontinuous sampling points to carry out flow design processing and control the sampling data discontinuous sampling points by setting a distance parameter; wherein the sampling interval is set to M × P.
3. A high performance interference rejection method according to claim 2, wherein step S3 comprises the sub-steps of:
step 3.1: performing cross-correlation multiplication processing on the space-time signals obtained in the step S2 to obtain a cross-correlation matrix formed at a sampling moment, wherein the calculation mode is X X X H Wherein X is H Represents the conjugate transition rank of X;
step 3.2: selecting L discontinuous sampling points at intervals set as M x P according to the cross-correlation matrix obtained in the step 3.1;
step 3.3: accumulating the sampling point data, and averaging to obtain an S = M × P dimensional covariance matrix R XX 。
4. A high performance interference rejection apparatus supporting a high performance interference rejection method according to any one of claims 1 to 3, the apparatus being an apparatus for implementing said high performance interference rejection method based on FPGA hardware; the device comprises a receiving and preprocessing module, a space-domain space-time signal processing single module, a covariance matrix generating module, a covariance matrix inversion module, a weight calculation and signal filtering processing module and an output module, wherein:
the receiving and preprocessing module is used for receiving the antenna array element signals and preprocessing the antenna array element signals to obtain IQ spatial domain signals with phase and amplitude information;
the space-to-space signal processing single module is used for carrying out time domain delay on the space-domain signal of each antenna array element according to the M antenna array element space-domain signals received by the receiving and preprocessing module, and each antenna array element forms P nodes, so that the M antenna array element space-domain signals are converted into space-time signals X = [ X ] to 11 x 12 … x MP ]', where' denotes a turn rank operation;
the covariance matrix generation module is used for generating a sampling data covariance matrix R according to the space-time signals generated by the space-time signal processing single module XX And performing a covariance matrix R of the sampled data XX Calculating (1);
the covariance matrix inversion module is used for generating a covariance matrix R of the sampled data according to the covariance matrix XX The covariance matrix R of the sampled data is obtained by adopting an improved covariance matrix inversion algorithm XX Performing an inversion operation to obtain
The weight calculation and signal filtering processing module is used for calculating the weight according to the external constraint information a (theta) 0 ) And the inverse of the covariance matrix obtained by the covariance matrix inverse module
To calculate the weight value, the calculation formula is
In the formula w opt Is the weight of the signal to be filtered; a (theta) 0 ) To constrain the information, a (θ) 0 )＝[1 0 ... 0]′；a H (θ 0 ) Is a (theta) 0 ) The conjugation rank of (2);
and the filtering device is used for carrying out filtering processing according to the weight information and the signals, and the calculation formula of the filtering signal Y is as follows:
in the formula
Is the conjugate rank of the weight of the signal to be filtered, X is a space-time signal, and X = [ X = [ [ X ] 11 x 12 … x MP ]′；
And the output module is used for finally outputting the filtering signal Y processed by the weight calculation and signal filtering processing module and outputting the filtering signal Y after interference resistance.
5. The apparatus of claim 4, wherein the covariance matrix inversion module comprises an inverse lower triangular matrix unit, a lower triangular matrix inversion unit, and an inverse lower triangular matrix inverse square matrix unit, and wherein:
the down-conversion triangular matrix unit is used for converting the covariance matrix R XX Splicing the real part and the imaginary part of the data, and converting the S-dimensional complex matrix into a 2S-dimensional real matrix; caching the spliced data in a block RAM memory in an FPGA programming device; recombining the data cached by the RAM to obtain a lower triangular matrix of the 2S-dimensional real matrix;
the lower triangular matrix inversion unit is used for converting integer data of the lower triangular matrix conversion unit into double-precision floating point data, adopts a design of parallel processing of N floating point inversion modules, and flexibly configures according to hardware resources, wherein N is more than or equal to 1 and less than or equal to 2S and is an effective parameter N; specifically, the method comprises the steps of comparing variables k [ n ]; n =1,2, \ 8230;, N; initializing, updating a variable k [ N ], judging a condition of k [ N ] =1, and controlling updating and output control of input data of an output inverse lower triangular matrix and N floating point inversion modules;
the inverse lower triangular matrix to square matrix unit is used for caching inverse lower triangular matrix data in the RAM memory and recombining the cached data to obtain a real part and an imaginary part of a square matrix, namely
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