CN111585431A - Power modulation device - Google Patents

Power modulation device Download PDF

Info

Publication number
CN111585431A
CN111585431A CN202010097807.7A CN202010097807A CN111585431A CN 111585431 A CN111585431 A CN 111585431A CN 202010097807 A CN202010097807 A CN 202010097807A CN 111585431 A CN111585431 A CN 111585431A
Authority
CN
China
Prior art keywords
signal
converter
controller
voltage
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010097807.7A
Other languages
Chinese (zh)
Other versions
CN111585431B (en
Inventor
纳迪姆·赫拉特
迈克尔·R·卡伊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qorvo US Inc
Original Assignee
Qorvo US Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/775,554 external-priority patent/US11233481B2/en
Application filed by Qorvo US Inc filed Critical Qorvo US Inc
Publication of CN111585431A publication Critical patent/CN111585431A/en
Application granted granted Critical
Publication of CN111585431B publication Critical patent/CN111585431B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
    • H03F1/0238—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply using supply converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H04W52/0235—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where the received signal is a power saving command
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

A modulated power device is disclosed that includes a tracking amplifier having an amplifier output terminal coupled to an output voltage node and an envelope input terminal configured to receive an envelope signal of a radio frequency signal. The multi-level voltage converter has a switched voltage terminal coupled to the output voltage node and a converter control input terminal configured to receive a converter control signal. The control signal multiplexer has: a converter control output terminal coupled to the converter control input terminal, a first converter signal input terminal configured to receive a first converter control signal corresponding to a lower envelope modulation bandwidth, a second converter signal input terminal configured to receive a second converter control signal corresponding to a higher envelope modulation bandwidth, and a converter control signal selector terminal configured to receive a control selector signal for selecting between the first converter control signal and the second converter control signal.

Description

Power modulation device
RELATED APPLICATIONS
This application claims the benefit of provisional patent application serial No. 62/807,095, filed on 2019, 2, month 18, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The technology of the present disclosure relates generally to power management in wireless communication devices.
Background
Mobile communication devices have become increasingly popular in today's society. The popularity of these mobile communication devices is driven to some extent by the many functions that are now implemented on such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile multimedia centers that can enhance the user experience.
The redefined user experience requires wireless communication technologies to provide higher data rates, such as Long Term Evolution (LTE). To achieve higher data rates in mobile communication devices, complex power amplifiers may be employed to increase the output power of Radio Frequency (RF) signals transmitted by the mobile communication devices (e.g., to maintain sufficient energy per bit). However, an increase in RF signal output power may result in increased power consumption and heat dissipation of the mobile communication device, thereby compromising overall performance and user experience.
Envelope tracking and average power tracking are power management techniques designed to increase the efficiency level of a power amplifier, thereby helping to reduce power consumption and heat dissipation in a mobile communication device. Envelope tracking employs a system that continuously tracks the amplitude envelope of RF signals transmitted by mobile communication devices. The envelope tracking system will constantly adjust the supply voltage applied to the power amplifier to ensure that the RF power amplifier can operate at a higher efficiency for a given instantaneous output power requirement of the RF signal. In this regard, the efficiency of the envelope tracking system may affect the overall power consumption and performance of the mobile communication device. In contrast, average power tracking adjusts the supply voltage of the RF power amplifier according to the output power of the transmitter.
While average power tracking has relatively low modulation bandwidth requirements, the envelope tracking requirements of modern LTE wireless devices require relatively wide power supply modulation bandwidths. Therefore, there is a need for a modulation power management apparatus that provides varying power supply modulation bandwidth requirements.
Disclosure of Invention
An apparatus is disclosed that includes a tracking amplifier having: an amplifier output terminal and a feedback input terminal, both coupled to the output voltage node, and an envelope input terminal configured to receive an envelope signal of the radio frequency signal. The apparatus further includes a multi-level voltage converter having a switched voltage terminal coupled to the output voltage node and a converter control input terminal configured to receive a converter control signal. The multi-level voltage converter is configured to receive the battery voltage and generate a switched voltage at a switched voltage terminal in response to the converter signal. Further comprising a control signal multiplexer having: a converter control output terminal coupled to the converter control input terminal, a first converter signal input terminal configured to receive a first converter control signal corresponding to a lower envelope modulation bandwidth below a modulation bandwidth threshold, a second converter signal input terminal configured to receive a second converter control signal corresponding to a higher envelope modulation bandwidth above the modulation bandwidth threshold, and a converter control signal selector terminal configured to receive a control signal selector signal for selecting between the first converter control signal and the second converter control signal.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
Drawings
The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram of a first embodiment of a power modulation apparatus in the form of an envelope tracking integrated circuit configured to provide modulated power to a load, such as a radio frequency power amplifier.
Fig. 2 is a schematic diagram of a second embodiment of a power modulation apparatus in the form of a modified version of the envelope tracking integrated circuit of fig. 1 and a distributed envelope tracking integrated circuit that is further configured to provide modulated power to a load, such as a radio frequency power amplifier.
FIG. 3 is a simplified schematic diagram of a first controller, which in an exemplary embodiment is a start-stop controller.
Fig. 4 is a simplified schematic diagram of a second converter controller, which in an exemplary embodiment is a pulse width modulator type controller.
Fig. 5 is a simplified schematic diagram of a multi-level voltage converter, which in an exemplary embodiment is of the multi-level charge pump type.
Detailed Description
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as extending "over" or "above" another element, it can extend directly over or "above" the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms, such as "below … …" or "above … …" or "above" or "below" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic diagram of a first embodiment of a power modulation apparatus in the form of an Envelope Tracking Integrated Circuit (ETIC)10 configured to provide modulated power to a load such as a radio frequency power amplifier 12. Power for operating the radio frequency power amplifier 12 is provided through a power supply terminal 14 coupled to a power supply voltage output terminal 16 of the ETIC 10.
During operation, a radio frequency signal, such as depicted in fig. 1 as a modulated sinusoid, is applied to the RF input terminal 18 of the radio frequency power amplifier 12. The radio frequency power amplifier 12 amplifies a radio frequency signal output from the RF output terminal 20.
For efficient operation of the RF power amplifier, the supply voltage VCCModulated by the ETIC 10, which in the exemplary embodiment has three supply voltage modulation modes during operation. The first mode is a first envelope tracking mode (ET1) associated with a lower modulation bandwidth below a predetermined modulation bandwidth threshold. The second mode is a second envelope tracking mode (ET2) associated with a higher modulation bandwidth above the predetermined modulation bandwidth threshold. The third mode is an average power tracking mode (APT) that modulates the supply voltage V as a function of the average RF signal powerCC. The APT mode is typically used when the amplified RF signal has a relatively low peak-to-average power ratio, as compared to a relatively high peak-to-average power ratio during operation of either the first envelope tracking mode ET1 or the second envelope tracking mode ET 2.
As shown in fig. 1, the envelope signal derived from the radio frequency signal is shown as a dashed sinusoid, which follows the modulation of the radio frequency signal. When operating in the first envelope tracking mode ET1 or the second envelope tracking mode ET2, the ETIC 10 is configured to modulate the supply voltage V by tracking the envelope signalCC。
In this regard, the ETIC 10 includes a tracking amplifier 22 having a tracking output terminal 24 and a feedback input terminal 28, both coupled to an output voltage node 30, which in turn is coupled to the supply voltage output terminal 16. FeedbackThe input terminal 28 is configured to receive a follow-up supply voltage VCCTracking the feedback signal. In some cases, the tracking feedback may be filtered before reaching the feedback input terminal 28.
Compensating capacitor CCompensation 1Coupled between tracking output terminal 24 and output voltage node 30 to provide a compensation voltage that adds to the output voltage at output voltage node 30. A ground switch SW1 is coupled between tracking output terminal 24 and ground GND to selectively couple a compensation capacitor C to tracking output terminal 24 when ETIC 10 is operating in APT modeCompensation 1To ground to form a compensation capacitor CCompensation 1Re-used as a filter capacitor.
The tracking amplifier 22 further comprises an envelope input terminal 26 configured to receive an envelope signal of the radio frequency signal. It should be understood that the envelope signal may be processed through various filters, such as anti-aliasing filters, before being input to the envelope input terminal 26. In some prior art disclosures, the envelope signal is referred to as VRAMPA signal. It should be understood that the envelope signal VRAMPMay be processed by an adaptive frequency equalizer (not shown) to compensate for impedance-induced tracking errors and undergo anti-aliasing filtering before reaching the envelope input terminal 26.
The ETIC 10 also includes a multi-level voltage converter 32 having a switched voltage terminal 34 coupled to the output voltage node 30 and a converter control input terminal 36 configured to receive a converter control signal CSX. In this exemplary embodiment, the multilevel voltage converter 32 is configured to receive the battery voltage VBATAnd generates a switching voltage at the switching voltage terminal 34 in response to the converter control signal CSX. An inductor L1 is coupled between the switching voltage terminal 34 and the output voltage node 30, with the inductor L1 configured to filter high frequency components from the switching voltage.
The ETIC 10 further includes a control signal multiplexer 38 having a converter control output terminal 40 coupled to the converter control input terminal 36. The first converter signal input terminal 42 of the control signal multiplexer 38 is configured to receive a first converter control signal CS1 corresponding to a lower envelope modulation bandwidth below the modulation bandwidth threshold. The second converter signal input terminal 44 is configured to receive a second converter control signal CS2 corresponding to a higher envelope modulation bandwidth above the modulation bandwidth threshold. The converter control signal selector terminal 46 is configured to receive a control signal selector signal SS1 for selecting between the first converter control signal CS1 and the second converter control signal CS 2.
The first converter controller 48 generates a first converter control signal CS 1. The first converter controller 48 has a first converter signal output terminal 50 coupled to the first converter signal input terminal 42. The first converter controller 48 has a first mode feedback terminal 52 configured to receive the ET1 feedback signal when the ETIC 10 is operating in the first envelope tracking mode ET 1.
In the exemplary embodiment of FIG. 1, the first converter controller 48 is a start-stop controller. Thus, the first converter control signal CS1 oscillates relatively abruptly between opposite sides of the dead band of the set point received at the first mode feedback terminal 52. In some cases of envelope tracking, start-stop control may be preferred at lower envelope modulation bandwidths below a predetermined modulation bandwidth threshold, which may be, for example, 10 MHz. However, at higher envelope modulation bandwidths above, for example, 20MHz, other types of controllers need to be used to maintain the efficiency provided by envelope tracking.
In this regard, simulations and experiments conducted with respect to the present disclosure have shown that a Pulse Width Modulation (PWM) type controller configured for APT may be reused for the second envelope tracking mode ET 2. Thus, in the exemplary embodiment of fig. 1, the second converter controller 54 is configured as a PWM-type controller that generates the second converter control signal CS 2. The second converter controller 54 has a second converter signal output terminal 56 coupled to the second converter signal input terminal 44. The second converter controller 54 has a second mode feedback terminal 58 configured to receive feedback when the ETIC 10 is operating in one of a second envelope tracking mode ET2 and an APT mode.
Returning to operation of the first converter controller 48, the ET1 feedback signal is the filtered signal FS1 and the voltage sense signal V1 added together at a first summing node 60 located between the first filter output node 62 and the first mode feedback terminal 52Sensing 1The sum of (a) and (b). Voltage sensing signal VSensing 1And a current sense signal ISensing 1In proportion, the current sense signal is proportional to the current flowing through the tracking output terminal 24. A current-to-voltage converter 64 coupled between the tracking output terminal 24 and the first summing node 60 is configured to convert the current sense signal ISensing 1Converted into a voltage sensing signal VSensing 1。
Filtered signal FS1 is output by type III loop filter 66 coupled between the outputs of first filter output node 62 and second summing node 68. When the ETIC 10 is operating in the envelope tracking mode ET1 or ET2, the second summing node 68 outputs a target voltage VObject 1And a compensation voltage VCompensation 1First differential signal DS1 between, or to output supply voltage V when ETIC 10 is operating in APT modeCC. Target voltage VObject 1Is generated by a digital-to-analog converter 70 having an analog output terminal 72 coupled to a first input of the second summing node 68 and a digital input 74 configured to receive a digital value from an external processor, such as a baseband digital processor (not shown). Target voltage VObject 1Is an analog voltage representation of the digital value received at digital input 74. A type III loop filter is defined as having three poles and two zeros, where one of the three poles is located at the origin of the pole-zero plot.
The feedback signal multiplexer 76 has a feedback output terminal 78 coupled to a second input of the second summing junction 68. The first feedback signal input terminal 80 of the feedback signal multiplexer 76 is configured to receive the compensation voltage VCompensation 1The compensation voltage is the compensation capacitor C when the ETIC 10 is operating in either of the envelope tracking modes ET1 or ET2Compensation 1The voltage of (c). The second feedback signal input terminal 82 is configured to receive a supply voltage VCCFor use as feedback when the ETIC 10 is operating in APT mode. Feedback signal selectionThe converter terminal 84 is configured to receive a feedback signal selector signal SS2 for use in compensating a voltage V used as feedback for envelope tracking modes ET1 and ET2 when the ETIC 10 is operating in APT modeCompensation 1And a supply voltage V used as feedbackCCTo select between.
Fig. 2 is a schematic diagram of a second embodiment of a power modulation apparatus in the form of a modified version of the ETIC 10 of fig. 1 and a Distributed Envelope Tracking Integrated Circuit (DETIC)86 that is further configured to provide modulated power to a load, such as the radio frequency power amplifier 12 (fig. 1). In this second exemplary embodiment, the ETIC 10 is modified to include a first controller multiplexer 88 configured to select between a first internal control signal generated internally by the ETIC 10 and a first external control signal generated externally to the ECIC 10 by the DETIC 86. The ETIC 10 is further modified to include a second controller multiplexer 90 configured to select between a second internal control signal generated internally by the ETIC 10 and a second external control signal generated externally to the ETIC 10 by the detac 86.
The first controller multiplexer 88 has a first internal signal terminal 92 coupled to the output of the first summing junction 60 and a first external signal terminal 94 coupled to an external control signal input terminal 96. The first controller signal selector terminal 98 is configured to receive a first controller signal selector signal SS3 for selecting between a first internal control signal and a first external control signal.
Furthermore, the second controller multiplexer 90 has a second internal signal terminal 100 coupled to the first filter output node 62 and a second external signal terminal 102 coupled to the external control signal input terminal 96. The second controller signal selector terminal 104 is configured to receive a second controller signal selector signal SS4 for selecting between a second internal control signal and a second external control signal.
The DETIC 86 includes a second tracking amplifier 106 having a second tracking output terminal 108 and a second feedback input terminal 110 that pass through a second of the DETIC 86A node connection terminal 112 and a second node connection terminal 114 of the ETIC 10 are both coupled to the output voltage node 30. The second tracking output terminal 108 and the second feedback input terminal 110 are also coupled to a second supply voltage output terminal 116. The second feedback input terminal 110 is configured to receive the follow-up supply voltage VCCThe modulated second tracking feedback signal. In some cases, the second tracking feedback may be filtered before reaching the second feedback input terminal 110.
Second compensation capacitor CCompensation 2Coupled between second tracking output terminal 108 and second supply voltage output terminal 116 to provide a second compensation voltage V that adds to the output voltage at output voltage node 30Compensation 2. A second ground switch SW2 is coupled between the second tracking output terminal 108 and ground GND for selectively coupling the second compensation capacitor C when the ETIC 10 is operating in the APT modeCompensation 2Is grounded to ground and the second compensating capacitor CCompensation 2Reused as compensation capacitor C in ETIC 10Compensation 1A second filter capacitor connected in parallel.
The second tracking amplifier 106 further comprises a second envelope input terminal 118 configured to receive an envelope signal of the radio frequency signal (fig. 1). It should be understood that the envelope signal may be processed through various filters, such as anti-aliasing filters, before being input to the second envelope input terminal 118. It should be understood that the envelope signal VRAMPMay be processed by an adaptive frequency equalizer (not shown) to compensate for impedance-induced tracking errors and undergo anti-aliasing filtering before reaching the second envelope input terminal 118.
The DETIC 86 further includes an external control signal multiplexer 120 having an external control output terminal 122 coupled to an external control output terminal 124, which is in turn coupled to the external control signal input terminal 96 of the ETIC 10. The first external control signal terminal 126 of the external control signal multiplexer 120 is configured to receive a first external control signal EC1 corresponding to a lower envelope modulation bandwidth below the modulation bandwidth threshold. The second external control signal terminal 128 is configured to receive a second external control signal EC2 corresponding to a higher envelope modulation bandwidth above the modulation bandwidth threshold. The external control signal selector terminal 130 is configured to receive a control signal selector signal SS5 for selecting between a first external control signal EC1 and a second external control signal EC 2.
The DETIC 86 also includes a first sub-controller 132 configured to generate a first external control signal EC1 that is selectively routable to the first converter controller 48 of the ETIC 10. In the exemplary embodiment of fig. 2, the first converter controller 48 of the ETIC 10 remains a start-stop controller. Accordingly, the first sub-controller 132 in the exemplary embodiment of FIG. 2 is referred to as a start-stop sub-controller. The first sub-controller 132 differs from the first converter controller 48 in that the first sub-controller 132 is not configured to directly control the multi-level voltage converter 32. Alternatively, the first external control signal EC1 may be selectively routed to the first mode feedback terminal 52 to become the first mode ET1 feedback signal used to drive the first converter controller 48.
The first external control signal EC1 is the second filtered signal FS2 and the second voltage sense signal V added together at a third summing node 134 between the second filter output node 136 and the first external control signal terminal 126Sensing 2The sum of (a) and (b). Second voltage sensing signal VSensing 2And a second current sense signal ISensing 2In proportion, the second current sense signal is proportional to the current flowing through the second tracking output terminal 108. A current-to-voltage converter 138 coupled between the second tracking output terminal 108 and the third summing node 134 is configured to convert the second current sense signal ISensing 2Converted into a second voltage sensing signal VSensing 2。
The second filtered signal FS2 is output by a second type III loop filter 140 coupled between the output of the second filter output node 136 and a fourth summing node 142. When the DETIC 86 operates in the first envelope tracking mode ET1, the fourth summing node 142 outputs a second target voltage VObject 2And a second compensation voltage VCompensation 2In between the second differential signal DS 2. Second target electricityPressure VObject 2Is generated by a second digital-to-analog converter 144 having an analog output terminal 146 coupled to a first input of the fourth summing node 142 and a second digital input 148 configured to receive digital values from an external processor, such as a baseband digital processor (not shown). Second target voltage VObject 2Is an analog voltage representation of the digital value received at the second digital input 148. The second digital-to-analog converter 144 is shown in dashed lines to highlight that the second target voltage V may be generated by reusing the digital-to-analog converter 70Object 2Instead of the second digital-to-analog converter 144.
The DETIC 86 further includes a second sub-controller 150 configured to generate a second external control signal EC2 that is selectively routable to the second converter controller 54 of the ETIC 10. In the exemplary embodiment of fig. 2, the second converter controller 54 of the ETIC 10 is still a pulse width modulator type controller. Therefore, the sub-controller 150 in the exemplary embodiment of FIG. 2 is referred to as a pulse width modulation sub-controller. The second sub-controller 150 differs from the second converter controller 54 in that the second sub-controller 150 is not configured to directly control the multi-level voltage converter 32. Alternatively, the second external control signal EC2 may be selectively routed to the second mode feedback terminal 58 to become the second mode ET2 feedback signal used to drive the second converter controller 54.
The third filtered signal FS3 is output by the third type III loop filter 152 that is coupled between the outputs of the third filter output node 154 and the fifth summing node 156. When the DETIC 86 operates in the first envelope tracking mode ET1, the fourth summing node 142 outputs a second target voltage VObject 2And a second compensation voltage VCompensation 2In between the second differential signal DS 2.
FIG. 3 is a simplified schematic diagram of the first converter controller 48, which in an exemplary embodiment is a start-stop controller. In this regard, the first converter controller 48 includes a first threshold comparator 158, a second threshold comparator 160, and a third threshold comparator 162 configured to compare the first mode ET1 signal with a first reference voltage V, respectivelyREF1A second reference voltage VREF2And a third reference voltage VREF3A comparison is made.
The state machine logic 164 receives the voltage signal levels V generated by the first, second and third threshold comparators 158, 160, 162, respectivelyCMP1、VCMP2And VCMP3. The state machine logic 164 is configured to be based on the corresponding VCMP1、VCMP2And VCMP3The voltage signal level and a current state, which may be one of a buck state, a boost state, a battery state, and a ground state of the multilevel voltage converter 32, generate the first converter control signal CS 1. The state machine logic 164 may be implemented, for example, by conventional logic cells and/or field programmable gate arrays.
Fig. 4 is a simplified schematic diagram of the second converter controller 54, which in the exemplary embodiment is a pulse width modulator type controller. The second converter controller 54 includes a sawtooth oscillator 166 that generates a positive slope sawtooth wave shown in solid lines and a negative slope sawtooth wave shown in dashed lines.
The fourth threshold comparator 168 is configured to compare the positive slope sawtooth waveform to a second pattern ET2 feedback signal when the ETIC 10 is operating in a second envelope tracking mode ET2 associated with a higher modulation bandwidth above the predetermined modulation bandwidth threshold. The fourth threshold comparator 168 is configured to output a buck control signal associated with the buck operation of the multilevel voltage converter 32.
The fifth threshold comparator 170 is configured to compare the negatively sloped sawtooth with the second mode ET2 feedback signal when the ETIC 10 is operating in the second envelope tracking mode ET2 associated with a higher modulation bandwidth above the predetermined modulation bandwidth threshold. The fifth threshold comparator 170 is configured to output a boost control signal associated with the boost operation of the multilevel voltage converter 32. The arbitration logic 172 is configured to pass the buck and boost control signals through the second converter signal output terminal 56 depending on which of the buck or boost is required for a particular state of the multilevel voltage converter 32.
Fig. 5 is a simplified schematic diagram of the multi-level voltage converter 32, which in an exemplary embodiment is of the multi-level charge pump type. In particular, the multi-level voltage converter 32 includes a multi-level charge pump switch matrix 174 coupled to the battery voltage VBATAnd ground GND. It further includes a first flying capacitor C coupled to the multi-stage charge pump switch matrix 174FLY1And a second flying capacitor CFLY2. The multi-stage charge pump switch matrix 174 is configured to operate at a battery voltage VBATAnd ground GND with a first flying capacitor C selectively coupled in various arrangementsFLY1And a second flying capacitor CFLY2To selectively couple the battery voltage V in accordance with a converter control signal CSX applied to a converter control input terminal 36BATAnd (4) reducing or increasing the pressure.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (20)

1. An apparatus, comprising:
a tracking amplifier having a tracking output terminal and a feedback input terminal both coupled to an output voltage node, and an envelope input terminal configured to receive an envelope signal of a radio frequency signal;
a multi-level voltage converter having a switched voltage terminal coupled to the output voltage node and a converter control input terminal configured to receive a converter control signal; and
a control signal multiplexer having: a converter control output terminal coupled to the converter control input terminal, a first converter signal input terminal configured to receive a first one of the converter control signals corresponding to a lower envelope modulation bandwidth below a modulation bandwidth threshold, a second converter signal input terminal configured to receive a second one of the converter control signals corresponding to a higher envelope modulation bandwidth above the modulation bandwidth threshold, and a converter control signal selector terminal configured to receive a control signal selector signal for selecting between the first one of the converter control signals and the second one of the converter control signals.
2. The device of claim 1, further comprising:
a first converter controller configured to generate the first of the converter control signals during a first envelope tracking mode corresponding to the lower envelope modulation bandwidth below the modulation bandwidth threshold; and
a second converter controller configured to generate the second one of the converter control signals during a second envelope tracking mode corresponding to the higher envelope modulation bandwidth above the modulation bandwidth threshold.
3. The apparatus of claim 2, wherein the second converter controller is configured to generate a third one of the converter control signals during an average power tracking mode.
4. The apparatus of claim 2, wherein the first converter controller is a start-stop controller.
5. The apparatus of claim 2, wherein the second converter controller is a pulse width modulation type controller.
6. The apparatus of claim 2, wherein the first converter controller is a start-stop controller and the second converter controller is a pulse width modulation type converter.
7. The apparatus of claim 2, further comprising a current-to-voltage converter coupled between the tracking output terminal of the tracking amplifier and a first summing node having a first mode feedback terminal coupled to the first converter controller, wherein the current-to-voltage converter is configured to convert a current sense signal proportional to a current flowing through the tracking output terminal to a voltage sense signal.
8. The apparatus of claim 7, further comprising a loop filter coupled between outputs of the first and second summing nodes, wherein the loop filter is configured to output a filtered version of a first differential signal generated at the output of the second summing node.
9. The device of claim 8, wherein a first envelope tracking feedback signal output to the first converter controller is a sum of the voltage sense signal and the filtered version of the first differential signal.
10. The apparatus of claim 8, wherein the second converter controller is configured to receive the filtered version of the first differential signal and generate the second one of the converter control signals during the second envelope tracking mode.
11. The device of claim 10, further comprising a compensation capacitor coupled between the tracking output terminal and the output voltage node to provide a compensation voltage that adds to an output voltage at the output voltage node.
12. The device of claim 11, further comprising a ground switch coupled between the tracking output terminal and ground, wherein the ground switch is configured to selectively ground a plate of the compensation capacitor coupled to the tracking output terminal when operating in an average power tracking mode.
13. The device of claim 11, further comprising a feedback signal multiplexer having:
a first feedback input terminal configured to receive a compensation voltage signal proportional to a voltage across the compensation capacitor;
a second feedback terminal configured to receive an output voltage signal proportional to a supply voltage at the output voltage node;
a feedback selector terminal configured to receive a feedback select signal that selects the compensation voltage signal when operating in the first envelope tracking mode or the second envelope tracking mode; and
a feedback output terminal coupled to an input of the second summing node, wherein a selected one of the compensation voltage signal and the output voltage signal is output at the feedback output terminal.
14. The apparatus of claim 13, wherein the feedback selector terminal is further configured to receive a feedback selection signal that selects the output voltage signal when operating in an average power tracking mode.
15. The apparatus of claim 13, wherein the first differential signal output to the loop filter is a difference between a target voltage signal and a selected one of the compensation voltage signal and the output voltage signal.
16. The device of claim 1, further comprising an inductor coupled between the switched voltage terminal and the output voltage node, wherein the inductor is configured to filter a switched voltage.
17. The device of claim 7, further comprising:
a first controller multiplexer having an output coupled to the first mode feedback terminal of the first converter controller, a first internal signal terminal coupled to the output of the first summing node, a first external signal terminal, and a first controller signal selector terminal configured to receive a first controller signal selector signal for selecting between a first internal control signal and a first external control signal; and
a second controller multiplexer having an output coupled to the second mode feedback terminal of the second converter controller, a second internal signal terminal coupled to the input of the first summing node, a second external signal terminal coupled to the first external signal terminal, and a second controller signal selector terminal configured to receive a second controller signal selector signal for selecting between a second internal control signal and a second external control signal.
18. The apparatus of claim 17, wherein the tracking amplifier, the multi-level voltage converter, the control signal multiplexer, the first converter controller, the first controller multiplexer, the second converter controller, and the second controller multiplexer are integrated into an envelope tracking integrated circuit having an external control signal input terminal coupled to the first and second external signal terminals.
19. The device of claim 18, further comprising:
a second tracking amplifier having a second tracking output terminal and a second feedback input terminal both coupled to the output voltage node, and a second envelope input terminal configured to receive the envelope signal of the radio frequency signal;
an external control signal multiplexer having: an external control output terminal coupled to the external control signal input terminal of the envelope tracking integrated circuit, a first external control signal terminal configured to receive a first one of the external converter control signals corresponding to a lower envelope modulation bandwidth below a modulation bandwidth threshold, a second external control signal terminal configured to receive a second one of the external converter control signals corresponding to a higher envelope modulation bandwidth above the modulation bandwidth threshold, and an external control signal selector terminal configured to receive an external control signal selector signal for selecting between the first one of the external converter control signals and the second one of the external converter control signals;
a first sub-controller configured to receive a tracking feedback signal from the second tracking amplifier and generate a first one of the external converter control signals based on a second target voltage and the tracking feedback signal; and
a second sub-controller configured to receive a compensated voltage signal from the second tracking amplifier and generate a second one of the external converter control signals based on a second target voltage and the compensated voltage signal.
20. The apparatus of claim 19, wherein the second tracking amplifier, the external control signal multiplexer, the first sub-controller, and the second sub-controller are integrated into a distributed envelope tracking integrated circuit.
CN202010097807.7A 2019-02-18 2020-02-17 modulated power device Active CN111585431B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962807095P 2019-02-18 2019-02-18
US62/807,095 2019-02-18
US16/775,554 US11233481B2 (en) 2019-02-18 2020-01-29 Modulated power apparatus
US16/775,554 2020-01-29

Publications (2)

Publication Number Publication Date
CN111585431A true CN111585431A (en) 2020-08-25
CN111585431B CN111585431B (en) 2023-10-13

Family

ID=72043690

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010097807.7A Active CN111585431B (en) 2019-02-18 2020-02-17 modulated power device

Country Status (1)

Country Link
CN (1) CN111585431B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266366A1 (en) * 2003-06-24 2004-12-30 Ian Robinson Multi-mode amplifier system
US20070036212A1 (en) * 2005-05-06 2007-02-15 Silicon Laboratories Inc. Digital Controller Based Power Factor Correction Circuit
US20130072139A1 (en) * 2011-09-21 2013-03-21 Samsung Electronics Co. Ltd. Apparatus and method for processing reduced bandwidth envelope tracking and digital pre-distortion
US20140361837A1 (en) * 2011-02-01 2014-12-11 Mediatek Singapore Pte. Ltd. Integrated circuit wireless communication unit and method for providing a power supply
EP2909928A1 (en) * 2012-10-19 2015-08-26 Telefonaktiebolaget LM Ericsson (Publ) Apparatus and method for load modulating an amplifier
US20170005619A1 (en) * 2015-07-01 2017-01-05 Qorvo Us, Inc. Envelope tracking power converter circuitry
US20170006543A1 (en) * 2015-07-01 2017-01-05 Rf Micro Devices, Inc. Dual-mode envelope tracking power converter circuitry
US20180152144A1 (en) * 2016-11-25 2018-05-31 Samsung Electronics Co., Ltd. Supply modulator and communication device including the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266366A1 (en) * 2003-06-24 2004-12-30 Ian Robinson Multi-mode amplifier system
US20070036212A1 (en) * 2005-05-06 2007-02-15 Silicon Laboratories Inc. Digital Controller Based Power Factor Correction Circuit
US20140361837A1 (en) * 2011-02-01 2014-12-11 Mediatek Singapore Pte. Ltd. Integrated circuit wireless communication unit and method for providing a power supply
US20130072139A1 (en) * 2011-09-21 2013-03-21 Samsung Electronics Co. Ltd. Apparatus and method for processing reduced bandwidth envelope tracking and digital pre-distortion
EP2909928A1 (en) * 2012-10-19 2015-08-26 Telefonaktiebolaget LM Ericsson (Publ) Apparatus and method for load modulating an amplifier
US20170005619A1 (en) * 2015-07-01 2017-01-05 Qorvo Us, Inc. Envelope tracking power converter circuitry
US20170006543A1 (en) * 2015-07-01 2017-01-05 Rf Micro Devices, Inc. Dual-mode envelope tracking power converter circuitry
US20180152144A1 (en) * 2016-11-25 2018-05-31 Samsung Electronics Co., Ltd. Supply modulator and communication device including the same

Also Published As

Publication number Publication date
CN111585431B (en) 2023-10-13

Similar Documents

Publication Publication Date Title
US11233481B2 (en) Modulated power apparatus
US10985702B2 (en) Envelope tracking system
TWI832856B (en) Switching regulator, power supply circuit and method of operating switching regulator
EP1638204B1 (en) Power amplifier and transmitter
US11349436B2 (en) Envelope tracking integrated circuit
CA2684917C (en) Power supplies for rf power amplifier
KR101797068B1 (en) Average current mode control of multi-phase switching power converters
US10044272B2 (en) Supply modulator including switched-mode power supplier and transmitting device including the same
KR20220037439A (en) Multimode Power Management Device
WO2016155346A1 (en) Open loop digital pwm envelope tracking system with dynamic boosting
US20080003950A1 (en) Controlling switching mode power supply of power amplifier
US11522456B2 (en) Supply modulator for power amplifier
US20140225674A1 (en) Bi-directional power supply signal based linear amplifier
CN103731107A (en) Control circuit and method for controlling an operation of a power amplifier
CN1592089A (en) Amplifier and radio frequency power amplifier using the same
US9813088B2 (en) Supply modulators with voltage and frequency partitioning
US10992264B2 (en) Envelope tracking circuit and related apparatus
WO2016019334A1 (en) Adaptive envelope tracking for biasing radio frequency power amplifiers
CN114978056A (en) Distributed power management apparatus
JP2009504080A (en) Power control of amplifier in wireless modem device
EP1530303A1 (en) Power control in a mobile communication system
US20220286092A1 (en) Multi-amplifier envelope tracking apparatus
US11088658B2 (en) Envelope tracking amplifier apparatus
CN111585431B (en) modulated power device
US20230006543A1 (en) Power noise filter and supply modulator including the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: North Carolina

Applicant after: QORVO US, Inc.

Address before: North Carolina

Applicant before: QORVO US, Inc.

GR01 Patent grant
GR01 Patent grant