CN111580750B - Method for solving STT-RAM cache write failure - Google Patents
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Abstract
The invention provides a method for solving STT-RAM cache write failure, which balances the error correction capability and the storage cost of an error correction code. S1, when initiating data writing operation, after determining the target cache block to be written, reading out the old data bitwise of the target cache block and comparing the old data bitwise with the new data bitwise, calculating and counting the total data bit number n of the STT-RAM unit corresponding to the current data bit, which will be switched from 0 to 1; s2, comparing n with a threshold value K th If n is greater than K th Error correction is carried out by adopting the extended error correction code, if n is less than or equal to K th If so, error correction is carried out by adopting a default error correction code; s3, when writing the cache block, setting the flag bit of the target cache block label, and marking the error correction code type of the target cache block; and S4, when the cache block data is read, the flag bit of the cache block label is read at the same time, the adopted error correction code type is determined according to the flag bit, and the cache block is sent to the corresponding error correction code decoder for error correction.
Description
Technical Field
The invention relates to a method for solving STT-RAM cache write failure.
Background
Compared with the traditional SRAM memory, the Spin Transfer Torque RAM (STT-RAM) as a novel memory has the advantages of low static energy consumption, high storage density, high reading speed, good compatibility with CMOS technology and the like, so the STT-RAM is expected to become the next-generation on-chip cache of a computer. STT-RAM also has significant disadvantages, including write failures. STT-RAM memory cells are primarily Magnetic Tunnel Junctions (MTJs) that include primarily a reference layer and a free layer. The magnetization direction of the reference layer is fixed horizontally, while the magnetization direction of the free layer is either in the same direction as the reference layer or in the opposite direction. When the magnetization directions of the reference layer and the free layer are opposite or the same, the magnetic tunnel junction presents two resistance states of low or high, which respectively represent logic values 0 or 1. Thus, writing data to the STT-RAM cell essentially changes the magnetization direction of the free layer.
When writing data, if the new data is different from the original data of the STT-RAM memory cell, the magnetization direction of the free layer needs to be changed. Mainly injecting a write current I into an STT-RAM cell write And hold t write The magnetization direction of the free layer is changed in time, but the magnetization direction may not be changed, i.e., there is a certain possibility of failure in the write operation, which is called a write failure. Probability of write failure of a single STT-RAM cellHowever, if the number of data bits of the data written into the cache block is large, the number of data bits in which write failure may occur is also large. In addition, the probability of occurrence of a write failure of an STT-RAM memory cell from a logic value 0 to 1 is 100 times greater than that of a write failure from 1 to 0. Therefore, the number of write-fail data bits of the cache block is proportional to the number of data bits for switching from logic values 0 to 1 between old and new data.
The traditional solution to write failure is to use error correction codes. As long as the number of error data bits which fail to be written in the cache block does not exceed the error correction capability of the error correction code, the write operation is successful; if the number of different data bits between the new data and the old data to be written is large, the number of write failure error bits appearing in the cache block is too large, the error data cannot be corrected by the error correcting code, and the normal operation of the program is influenced. The main reason for the above problems is that the data bit number of the error correcting code of the cache block is fixed, and the error correcting capability is constant; and the different bit numbers of the new data and the old data of the cache block are obviously different. Different cache blocks, different write update states, and error correction codes with different error correction capabilities need to be set. If the error correcting codes with strong error correcting capability are adopted, the storage cost is overlarge; if error correction codes with default error correction capability are adopted, the error correction capability is insufficient.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a method for solving the cache write failure of STT-RAM, which balances the error correction capability of an error correction code and the storage cost.
The technical scheme adopted by the invention for solving the problems is as follows: a method for solving the problem of STT-RAM cache write failure is characterized in that: the method comprises the following steps:
s1, when a data writing operation is initiated, after a target cache block to be written is determined, old data bitwise and new data bitwise of the target cache block are read out and compared, and the total data bit n for counting the switching of 0 to 1 of an STT-RAM unit corresponding to the current data bit is calculated;
s2, comparing n with a threshold value K th If n is greater than K th Then error correction is carried out by adopting the extended error correcting code, if n is less than or equal to K th Then using default error correction codeCorrecting errors;
s3, when writing the cache block, setting the flag bit of the target cache block label, and marking the error correction code type of the target cache block;
and S4, when the cache block data is read, the flag bit of the cache block label is read at the same time, the adopted error correction code type is determined according to the flag bit, and the cache block is sent to the corresponding error correction code decoder for error correction.
The invention calculates and counts the total data bit n of switching from 0 to 1 of an STT-RAM unit corresponding to the current data bit, and comprises the following steps: reading old data in a target cache block, inverting the old data, performing bitwise AND operation on the old data and corresponding new data, if the output value is 1, indicating that the STT-RAM unit corresponding to the current data bit is switched from 0 to 1, and taking the output of each bit as the input of a Hamming distance calculator, wherein the output of the Hamming distance calculator is the total data bit number n of the STT-RAM unit corresponding to the current data bit, which is switched from 0 to 1. The whole calculation circuit is a combinational circuit, so no extra delay is introduced.
Threshold value K of the invention th The calculation steps are as follows: calculating threshold value K th When the system allows the upper limit of the probability of the occurrence of the write failure of the cache block to be e, the error correction capability of the error correction code of the cache block is k data bits, the number of the data bits of the cache block with the write failure is m, and when m is greater than k, the current write operation fails, so that the failure probability of the write operation is P (m is greater than or equal to (k +1)), and the following requirements are met:
P(m≥(k+1))<e,
because the default error correcting code adopts 1-bit error correction, K is 1, and the minimum m value met by calculation according to the Chernov probability formula is K th 。
The default error correcting code and the extended error correcting code of the invention are both oriented to a cache block with 64bytes, wherein the default error correcting code adopts a SECDED code with 1-bit error correction and 2-bit error detection, and the length of occupied data is 11 bits; the extended error correcting code adopts 4EC5ED codes with 4 bits of error correction and 5 bits of error detection, and the data length is 41 bits.
For the extended error correcting code, the upper limit of the probability of write failure of a cache block allowed by a system is e, the error correcting capability of the cache block is k data bits, the number of the data bits of the cache block with write failure is m, the failure probability of write operation is P (m is more than or equal to (k +1)), and the following requirements are met:
P(m≥(k+1))<e,
aiming at the size of a cache block being 64Bytes, calculating according to a Cherov probability formula to obtain the maximum value of k being 4; to meet the requirements of the system, in the worst case, the extended error correction code only needs to have the capability of correcting 4-bit error data.
For a default error correcting code and an extended error correcting code, the actually updated data bits in a cache block are far smaller than the capacity of 512 bits of the cache block, and the number of write failure data bits of most cache blocks is less than or equal to 1; 80% of the cache blocks in the cache set can be allocated default error correction codes and 20% of the cache blocks can be allocated extended error correction codes.
The step S3 of the present invention specifically includes: when the total data bit number n of the STT-RAM unit corresponding to the current data bit of the target cache block and switching from 0 to 1 is more than K th When the target cache block adopts the extended error correction code, new data is sent to an extended error correction code encoder to generate an error correction code, and meanwhile, the flag bit value of the cache block label is set to be 1; when the total data bit number n of the STT-RAM unit corresponding to the current data bit of the target cache block and switching from 0 to 1 is less than or equal to K th And then, the target cache block adopts a default error correcting code, new data is sent to a default error correcting code encoder to generate an error correcting code, and meanwhile, the flag bit value of the cache block label is set to be 0.
In step S4, if the flag bit has a value of 0, the flag bit is sent to the default ecc decoder to correct possible erroneous data bits; if the flag bit has a value of 1, the data is sent to an ECC decoder to correct a possible erroneous data bit.
Compared with the prior art, the invention has the following advantages and effects: the invention distributes error correcting code resources according to the different bit numbers of new and old data when the cache block writes data, distributes default error correcting codes for the written cache blocks with less different bit numbers, and distributes extended error correcting codes for the written cache blocks with more different bit numbers, the default error correcting code data bit number is less, the error correcting capability is weak, the extended error correcting code data bit number is more, the error correcting capability is strong, thereby obtaining balance between the error correcting capability and the storage cost of the error correcting code.
Drawings
FIG. 1 is a schematic diagram of an embodiment of the invention for calculating a total data bit for counting the switching of 0 to 1 occurring to an STT-RAM cell corresponding to a current data bit.
Fig. 2 is a flowchart of step S2 according to an embodiment of the present invention.
Fig. 3 is a flowchart of step S4 according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below by way of examples with reference to the accompanying drawings, which are illustrative of the present invention and are not to be construed as limiting the present invention.
Referring to fig. 1-3, an embodiment of the present invention includes the steps of:
and S1, when a data writing operation is initiated, after a target cache block to be written is determined, reading out old data bits of the target cache block, comparing the old data bits with new data, and calculating and counting the total data bit number n of switching from 0 to 1 of an STT-RAM unit corresponding to the current data bit.
The step of calculating the total data bit n for switching from 0 to 1 of the STT-RAM unit corresponding to the current data bit is as follows:
reading old data in a target cache block, negating the old data, performing AND operation with corresponding new data according to bits, if the output value is 1, indicating that the STT-RAM unit corresponding to the current data bit is switched from 0 to 1, and taking the output of each bit as the input of a Hamming distance calculator, wherein the output of the Hamming distance calculator is the total data bit number n of the STT-RAM unit corresponding to the current data bit, which is switched from 0 to 1. The whole calculation circuit is a combinational circuit, so no extra delay is introduced.
S2, comparing n with a threshold value K th : if n is greater than K th Then error correction is carried out by adopting the extended error correcting code, if n is less than or equal to K th Then a default error correction code is used for error correction.
Assuming that the hamming distance of the current cache block is n, that is, the total data bit number of switching from 0 to 1 of the STT-RAM unit corresponding to the current data bit is n, and the error correction capability of the error correction code of the cache block is k bits, when the data bit number m of the write failure is greater than k, the current write operation fails. Therefore, the probability of failure of a write operation is P (m ≧ (k + 1)). If the probability of write failure per memory cell is q, the expectation of a write error in switching n data bits is μ — nq. The upper limit of the probability of write failure of the cache block allowed by the system is e, so that the following requirements are met:
P(m≥(k+1))<e (1)
according to the knov probability formula:
combining equations (1) and (2) yields:
where k +1 is (1+ δ) μ, the maximum value of k may be calculated such that the probability of write failure of the cache block under a write update is less than the upper limit that can be tolerated by the system, given the value of n.
Threshold value K th The calculating steps are as follows: calculating threshold value K th When the system allows the upper limit of the probability of the occurrence of the write failure of the cache block to be e, the error correction capability of the error correction code of the cache block is k data bits, the number of the data bits of the cache block with the write failure is m, and when m is greater than k, the current write operation fails, so that the failure probability of the write operation is P (m is greater than or equal to (k +1)), and the following requirements are met:
P(m≥(k+1))<e,
since the default error correction code adopts 1-bit error correction, k is taken to be 1, and according to the knov probability formula:
the minimum m value satisfied by calculation is K th 。
The default error correcting code and the extended error correcting code both face to a cache block with the size of 64bytes, wherein the default error correcting code adopts a SECDED code with 1-bit error correction and 2-bit error detection, and the length of occupied data is 11 bits; the extended error correction code adopts 4EC5ED codes with 4-bit error correction and 5-bit error detection, and the occupied data length is 41 bits.
For the extended error correcting code, the upper limit of the probability of write failure of a cache block allowed by a system is e, the error correction capability of the cache block is k data bits, the number of the data bits of the cache block with write failure is m, the failure probability of write operation is P (m ≧ k +1)), and the following requirements are met:
P(m≥(k+1))<e,
for a cache block size of 64Bytes, according to the knov probability formula:
the maximum value of k obtained by calculation is 4, and the extended error correction code only has the capability of correcting 4-bit error data under the worst condition to meet the requirements of the system.
For the default error correcting code and the extended error correcting code, the actually updated data bits in the cache block are far smaller than the capacity of 512 bits of the cache block, and the number of write failure data bits of most cache blocks is smaller than or equal to 1; 80% of the cache blocks in the cache set can be allocated default error correction codes and 20% of the cache blocks can be allocated extended error correction codes.
S3, setting a flag bit of the target cache block tag when writing the cache block, and identifying an error correction code type of the target cache block, the specific steps are:
when the cache block is written, the total data bit number n of switching from 0 to 1 of the STT-RAM unit corresponding to the current data bit of the target cache block is more than K th When the target cache block is marked, an extended error correction code is adopted, new data is sent to an extended error correction code encoder to generate an error correction code, and meanwhile, the flag bit value of a cache block label is set to be 1; when the total data bit number n of the STT-RAM unit corresponding to the current data bit of the target cache block and switching from 0 to 1 is less than or equal to K th And then, marking the target cache block by adopting a default error correcting code, sending the new data to a default error correcting code encoder to generate an error correcting code, and setting the flag bit value of the cache block label to be 0.
S4, when reading the cache block data, reading the flag bit of the cache block label, determining the type of the adopted error correction code according to the flag bit of the cache block label, and sending the cache block to the corresponding error correction code decoder for error correction; wherein if the flag bit has a value of 0, sending the data to a default ECC decoder to correct possible erroneous data bits; if the flag bit has a value of 1, the data is sent to an ECC decoder to correct a possible erroneous data bit.
In addition, it should be noted that the specific embodiments described in the present specification may be different in the components, the shapes of the components, the names of the components, and the like, and the above description is only an illustration of the structure of the present invention. Equivalent or simple changes in the structure, characteristics and principles of the invention are included in the protection scope of the patent. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.
Claims (7)
1. A method for solving the problem of STT-RAM cache write failure is characterized in that: the method comprises the following steps:
s1, when a data writing operation is initiated, after a target cache block to be written is determined, reading out old data of the target cache block, comparing the old data with new data according to bit, and calculating and counting the number n of data bits of the STT-RAM unit corresponding to the current data bit, wherein the STT-RAM unit is to be switched from 0 to 1;
s2, comparing n with a threshold value K th If n is greater than K th Error correction is carried out by adopting the extended error correction code, if n is less than or equal to K th If so, error correction is carried out by adopting a default error correction code;
calculating threshold value K th When the system allows the cache block to have the probability upper limit of occurrence of write failure, the upper limit of the probability of occurrence of write failure of the cache block is e, the error correction capability of an error correction code of the cache block is k data bits, the number of the data bits of the cache block with write failure is m, and when m is larger than k, the current write operation fails, so that the failure probability of the write operation is
To satisfy:
since the default error correcting code adopts 1-bit error correction, K =1 is taken, and the minimum m value met by calculation according to the Chenoff probability formula is K th ；
S3, when writing the cache block, setting the flag bit of the target cache block label, and marking the error correction code type of the target cache block;
and S4, when the cache block data is read, the flag bit of the cache block label is read at the same time, the adopted error correction code type is determined according to the flag bit, and the cache block is sent to the corresponding error correction code decoder for error correction.
2. The method of addressing STT-RAM cache write failures of claim 1, wherein: the step of calculating the data bit number n of the switching from 0 to 1 of the STT-RAM unit corresponding to the current data bit is as follows: reading old data in a target cache block, negating the old data, performing AND operation with corresponding new data according to bits, if the output value is 1, indicating that the STT-RAM unit corresponding to the current data bit is switched from 0 to 1, and taking the output of each bit as the input of a Hamming distance calculator, wherein the output of the Hamming distance calculator is the total data bit number n of the STT-RAM unit corresponding to the current data bit, which is switched from 0 to 1.
3. The method of addressing STT-RAM cache write failures of claim 1, wherein: the default error correcting code and the extended error correcting code both face to a cache block with the size of 64bytes, wherein the default error correcting code adopts a SECDED code with 1-bit error correction and 2-bit error detection, and the length of occupied data is 11 bits; the extended error correction code adopts 4EC5ED codes with 4-bit error correction and 5-bit error detection, and the occupied data length is 41 bits.
4. The method of addressing STT-RAM cache write failures of claim 1, wherein: for the extended error correction code, the upper limit of the probability of write failure of the cache block allowed by the system is e, the error correction capability of the cache block is k data bits,the number of bits of write failure data in the cache block is m, and the failure probability of the write operation is
To satisfy:
aiming at the size of a cache block being 64Bytes, calculating according to a Cherov probability formula to obtain the maximum value of k being 4; to meet the requirements of the system, in the worst case, the extended error correction code only needs to have the capability of correcting 4-bit error data.
5. The method of addressing STT-RAM cache write failures of claim 1, in which: for the default error correcting code and the extended error correcting code, the actually updated data bits in the cache block are smaller than the 512-bit capacity of the cache block, and the write failure data bit number of most cache blocks is smaller than or equal to 1; 80% of the cache blocks in the cache set can be allocated default error correction codes and 20% of the cache blocks can be allocated extended error correction codes.
6. The method of addressing STT-RAM cache write failures of claim 1, wherein: the specific step of step S3 is: when the total data bit number n of the STT-RAM unit corresponding to the current data bit of the target cache block and switching from 0 to 1 is more than K th When the target cache block adopts the extended error correction code, new data is sent to an extended error correction code encoder to generate an error correction code, and meanwhile, the flag bit value of the cache block label is set to be 1; when the total data bit number n of the STT-RAM unit corresponding to the current data bit of the target cache block and switching from 0 to 1 is less than or equal to K th And then, the target cache block adopts a default error correcting code, new data is sent to a default error correcting code encoder to generate an error correcting code, and meanwhile, the flag bit value of the cache block label is set to be 0.
7. The method of addressing STT-RAM cache write failures of claim 1, in which: in step S4, if the flag bit has a value of 0, the flag bit is sent to the default ecc decoder to correct possible erroneous data bits; if the flag bit has a value of 1, the data is sent to an ECC decoder to correct a possible erroneous data bit.
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| CN110660422A (en) * | 2018-06-29 | 2020-01-07 | 上海磁宇信息科技有限公司 | Cache system used in cooperation with error correction magnetic random access memory |
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| AU2020103371A4 (en) | 2021-01-28 |
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