CN111580639A - SSD (solid State disk) adaptive load clock adjusting method and device and computer equipment - Google Patents

SSD (solid State disk) adaptive load clock adjusting method and device and computer equipment Download PDF

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Publication number
CN111580639A
CN111580639A CN202010372685.8A CN202010372685A CN111580639A CN 111580639 A CN111580639 A CN 111580639A CN 202010372685 A CN202010372685 A CN 202010372685A CN 111580639 A CN111580639 A CN 111580639A
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Prior art keywords
clock
hardware module
module
load
activity
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Inventor
王猛
徐伟华
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Shenzhen Union Memory Information System Co Ltd
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Shenzhen Union Memory Information System Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The application relates to a method and a device for adjusting an SSD (solid State disk) adaptive load clock, computer equipment and a storage medium, wherein the method comprises the following steps: the system is powered on, and each hardware module is initialized and works in default clock configuration; monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state; feeding back the load state of the current hardware module to a clock regulation system; and the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement. According to the invention, the load condition of each hardware module is monitored in real time, and the working clock of each module is dynamically adjusted, so that the optimal load clock ratio can be achieved, the SSD power consumption is effectively reduced, and the system endurance time can be greatly improved.

Description

SSD (solid State disk) adaptive load clock adjusting method and device and computer equipment
Technical Field
The invention relates to the technical field of solid state disks, in particular to a method and a device for adjusting an SSD (solid state drive) adaptive load clock, a computer device and a storage medium.
Background
With the price drop of the solid state disk, the solid state disk is more and more popular, the NVMe SSD is called SSD for short, the development is more rapid due to the superior performance of the SSD, and various computer manufacturers make the NVMe SSD into the hard disk, so that better experience is provided for users from the aspects of reliability and performance.
Currently, with the evolution of PC interface specifications, from SATA to PCIe, the supportable rate is higher and higher, and with the increase of the speed of the NAND interface, the access performance that the SSD can provide is also from 500MB/s earlier to 3.5GB/s now. With the increase in speed, the increase in SSD power consumption comes in. In the current notebook application scenario, as a mobile worker, considerable attention is paid to the cruising ability of a battery, and how to improve the cruising ability to the greatest extent is a very concern of a whole machine design manufacturer. The SSD is used as a key device, and how to optimize the power consumption plays a decisive role in improving the power consumption of the whole machine. However, in existing SSDs, the SSD cannot enter the corresponding power saving mode unless the host explicitly tells the SSD to enter a particular low power consumption state. In a non-low power consumption state, the SSD must operate in a full-speed mode regardless of saturation of operation, resulting in a waste of power consumption.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method and an apparatus for adjusting an SSD adaptive load clock, a computer device and a storage medium, which can reduce SSD power consumption.
A method of adjusting an SSD adaptive load clock, the method comprising:
the system is powered on, and each hardware module is initialized and works in default clock configuration;
monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state;
feeding back the load state of the current hardware module to a clock regulation system;
and the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement.
In one embodiment, the step of monitoring the utilization rate of each hardware module and determining whether the current hardware module is in a full load state or a light load state includes:
inquiring the command/data volume of the PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by the host interface to obtain the FE _ ACTIVITY _ PERCENT percentage;
inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
and inquiring the non-idle time of the system on each Core of the CPU to obtain the CPU _ ACTIVITY _ PERCENT percentage.
In one embodiment, after the step of monitoring the utilization rate of each hardware module and determining whether the current hardware module is in a full load state or a light load state, the method further includes:
and periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
In one embodiment, the step of the clock adjusting system dynamically adjusting the working clock of the corresponding module according to the load status of the current hardware module further includes:
the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
An apparatus for adjusting an SSD adaptive load clock, the apparatus comprising:
the initialization module is used for electrifying the system, initializing each hardware module and working in default clock configuration;
the load monitoring module is used for monitoring the utilization rate of each hardware module and judging whether the current hardware module is in a full load state or a light load state;
the feedback module is used for feeding back the load state of the current hardware module to the clock regulation system;
and the clock adjusting module is used for dynamically adjusting the working clock of the corresponding module according to the load state of the current hardware module through the clock adjusting system so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement.
In one embodiment, the load monitoring module is further configured to:
inquiring the command/data volume of the PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by the host interface to obtain the FE _ ACTIVITY _ PERCENT percentage;
inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
and inquiring the non-idle time of the system on each Core of the CPU to obtain the CPU _ ACTIVITY _ PERCENT percentage.
In one embodiment, the feedback module is further configured to:
and periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
In one embodiment, the clock adjustment module is further configured to:
the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
The adjusting method and device of the SSD self-adaptive load clock, the computer equipment and the storage medium initialize each hardware module and work in default clock configuration; monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state; feeding back the load state of the current hardware module to a clock regulation system; and the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement. According to the invention, the load condition of each hardware module is monitored in real time, and the working clock of each module is dynamically adjusted, so that the optimal load clock ratio can be achieved, the SSD power consumption is effectively reduced, and the system endurance time can be greatly improved.
Drawings
FIG. 1 is a block diagram of a conventional SSD system frame;
FIG. 2 is a block diagram of an SSD system frame, in one embodiment;
FIG. 3 is a schematic flow chart of a method for adjusting an SSD adaptive load clock in one embodiment;
FIG. 4 is a schematic flow chart of a method for adjusting the SSD adaptive load clock in another embodiment;
FIG. 5 is a schematic diagram of an exemplary interaction process for SSD adaptive load clock throttling;
FIG. 6 is a block diagram of an SSD adaptive load clock regulation device in one embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
As shown in fig. 1, a schematic diagram of a framework of an SSD system in the conventional technology at present specifically includes:
PCIe/NVMe hardware Module: and carrying out physical connection/protocol data transmission with the host.
A CPU module: the firmware for controlling the operation of the system generally has a plurality of cores, and for example, a typical system generally has three cores, which respectively perform the following operations: and the front-end module interacts with the PCIe/NVMe hardware module to perform command processing/data transmission management. And the mapping table management module is used for completing mapping distribution/query and other operations from the host logical address to the NAND physical address. And the rear-end module interacts with the NFC hardware module to complete operations such as NAND read-write erasing.
NFC hardware module: physical connection/protocol data transfer with NAND.
DRAM: the storage of data needing quick access generally comprises a logic-to-physical mapping table, a read-write buffer and the like.
During the operation of the SOC, each hardware module needs a certain clock input, and generally, the faster the clock is, the higher the performance is, but the higher the power consumption is. It follows that in existing SSDs, the SSD cannot enter the corresponding power saving mode unless the host explicitly tells the SSD to enter a particular low power state. In a non-low power consumption state, the SSD must operate in a full-speed mode regardless of saturation of operation, resulting in a waste of power consumption.
In one embodiment, as shown in fig. 3, there is provided a method for adjusting an SSD adaptive load clock, the method comprising:
step 302, electrifying the system, initializing each hardware module and working in default clock configuration;
step 304, monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state;
step 306, feeding back the load state of the current hardware module to the clock regulation system;
and 308, the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement.
In the present embodiment, a method for adjusting the SSD adaptive load clock is provided, which can be applied to the system architecture shown in fig. 2. The system framework introduces two key modules on the basis of the traditional SSD framework. And the load monitoring module is used for monitoring the utilization rate state of each hardware module so as to judge whether the module is in a full load state or a light load state at present. And the clock adjusting system is used for acquiring the utilization rate of each hardware module of the load monitoring module and dynamically adjusting the working clock of the corresponding module, so that the power consumption overhead is minimum on the premise of meeting the current host computer requirement.
Specifically, referring to the interaction process schematic diagram of SSD adaptive load clock adjustment shown in fig. 5, the method for adjusting the SSD adaptive load clock provided in this embodiment includes the following steps:
and S0, powering on the system.
And S1, initializing each module and working in default clock configuration.
S2, the load monitoring module queries the utilization rate of the key hardware resource.
And S3, the load monitoring module reports the current load condition of each module to the clock regulation system.
And S4, the clock adjusting system dynamically adjusts the working clock of each module according to the load condition.
S2-S4 are repeatedly performed to implement adaptive load clock adjustment of the runtime.
In one embodiment, a method for adjusting an SSD adaptive load clock is provided, in which a step of a clock adjusting system dynamically adjusting a working clock of a corresponding module according to a load state of a current hardware module further includes: the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
Specifically, in this embodiment, when the module is monitored to be in the low load/utilization state, the working clock of the module with the low load/utilization may be dynamically adjusted, so that the power consumption overhead is minimum on the premise of meeting the current host requirement, thereby achieving the effect of optimizing the SSD power consumption.
In the above embodiment, each hardware module is initialized and operates in a default clock configuration; monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state; feeding back the load state of the current hardware module to a clock regulation system; and the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement. According to the scheme, the load condition of each hardware module is monitored in real time, the working clock of each module is dynamically adjusted, the optimal load clock ratio can be achieved, the SSD power consumption is effectively reduced, and the system endurance time can be greatly prolonged.
In one embodiment, as shown in fig. 4, a method for adjusting an SSD adaptive load clock is provided, in which the step of monitoring the utilization rate of each hardware module and determining whether the current hardware module is in a full load state or a light load state includes:
step 402, inquiring command/data volume of a PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by a host interface to obtain FE _ ACTIVITY _ PERCENT percentage;
step 404, inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
step 406, inquiring non-idle time of a system on each Core of the CPU to obtain CPU _ ACTIVITY _ PERCENT percentage;
and step 408, periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
In this embodiment, a method for adjusting an SSD adaptive load clock is provided, where the method may monitor the utilization status of each hardware module through a load monitoring module to determine whether the module is currently in a full load state or a light load state.
Specifically, the command/data volume of the PCIe/NVMe hardware module in unit time is inquired and compared with the maximum throughput which can be supported by the host interface to obtain an FE _ ACTIVITY _ PERCENT percentage value, and the value is 0-100% and is used for marking the load percentage of the front-end module.
And inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT, wherein the BE _ ACTIVITY _ PERCENT takes a value of 0-100% and is used for marking the load percentage of the rear-end module.
And inquiring the non-idle time of the system on each Core of the CPU to obtain CPU _ ACTIVITY _ PERCENT, and taking a value of 0-100% for marking the load percentage of the CPU module.
And periodically inquiring the load percentage of each module, and feeding the load percentage back to the clock regulation system.
In this embodiment, the ACTIVITY status of peripherals such as a host interface/CPU/NAND and the like is monitored during the SSD operation, and the utilization rate of a key hardware resource is queried through the load monitoring module, where the resource utilization rate includes FE _ active _ policy/BE _ active _ policy/CPU _ active _ policy. The load monitoring module reports the current load condition of each module to the clock adjusting system so as to realize that the clock adjusting system dynamically adjusts the working clock of each module according to the load condition, thereby optimizing the SSD power consumption.
It should be understood that although the various steps in the flow charts of fig. 3-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 3-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 6, there is provided an SSD adaptive load clock regulation apparatus 600, the apparatus comprising:
the initialization module 601 is used for powering on a system, initializing each hardware module and working in default clock configuration;
a load monitoring module 602, configured to monitor utilization rates of the hardware modules, and determine whether a current hardware module is in a full load state or a light load state;
a feedback module 603, configured to feed back the load status of the current hardware module to a clock adjustment system;
the clock adjusting module 604 is configured to dynamically adjust the working clock of the corresponding module according to the load state of the current hardware module through the clock adjusting system, so as to achieve the minimum power consumption and cost on the premise of meeting the current host requirement.
In one embodiment, the load monitoring module 602 is further configured to:
inquiring the command/data volume of the PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by the host interface to obtain the FE _ ACTIVITY _ PERCENT percentage;
inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
and inquiring the non-idle time of the system on each Core of the CPU to obtain the CPU _ ACTIVITY _ PERCENT percentage.
In one embodiment, the feedback module 603 is further configured to:
and periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
In one embodiment, the clock adjustment module 604 is further configured to:
the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
For specific limitations of the adjusting device for the SSD adaptive load clock, reference may be made to the above limitations of the adjusting method for the SSD adaptive load clock, which are not described herein again.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 7. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of adjusting an SSD adaptive load clock.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method of adjusting an SSD adaptive load clock, the method comprising:
the system is powered on, and each hardware module is initialized and works in default clock configuration;
monitoring the utilization rate of each hardware module, and judging whether the current hardware module is in a full load state or a light load state;
feeding back the load state of the current hardware module to a clock regulation system;
and the clock adjusting system dynamically adjusts the working clock of the corresponding module according to the load state of the current hardware module so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement.
2. The method according to claim 1, wherein the step of monitoring the utilization of each hardware module and determining whether the current hardware module is in a full load state or a light load state comprises:
inquiring the command/data volume of the PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by the host interface to obtain the FE _ ACTIVITY _ PERCENT percentage;
inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
and inquiring the non-idle time of the system on each Core of the CPU to obtain the CPU _ ACTIVITY _ PERCENT percentage.
3. The method according to claim 2, wherein after the step of monitoring the utilization of each hardware module and determining whether the current hardware module is in a full load state or a light load state, the method further comprises:
and periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
4. The method for adjusting the SSD adaptive load clock according to any one of claims 1 to 3, wherein the step of the clock adjusting system dynamically adjusting the working clock of the corresponding module according to the load status of the current hardware module further comprises:
the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
5. An apparatus for adjusting an SSD adaptive load clock, the apparatus comprising:
the initialization module is used for electrifying the system, initializing each hardware module and working in default clock configuration;
the load monitoring module is used for monitoring the utilization rate of each hardware module and judging whether the current hardware module is in a full load state or a light load state;
the feedback module is used for feeding back the load state of the current hardware module to the clock regulation system;
and the clock adjusting module is used for dynamically adjusting the working clock of the corresponding module according to the load state of the current hardware module through the clock adjusting system so as to realize the minimum power consumption and expenditure on the premise of meeting the current host computer requirement.
6. The apparatus of claim 5, wherein the load monitoring module is further configured to:
inquiring the command/data volume of the PCIe/NVMe hardware module in unit time, and comparing the command/data volume with the maximum throughput which can be supported by the host interface to obtain the FE _ ACTIVITY _ PERCENT percentage;
inquiring the command/data volume of the NFC hardware module in unit time, and comparing the command/data volume with the maximum throughput which can BE supported by the NAND interface to obtain BE _ ACTIVITY _ PERCENT percentage;
and inquiring the non-idle time of the system on each Core of the CPU to obtain the CPU _ ACTIVITY _ PERCENT percentage.
7. The apparatus of claim 6, wherein the feedback module is further configured to:
and periodically inquiring the FE _ ACTIVITY _ PERCENT percentage, the BE _ ACTIVITY _ PERCENT percentage and the CPU _ ACTIVITY _ PERCENT percentage of each hardware module, and feeding back to the clock regulation system.
8. The apparatus of any of claims 5-7, wherein the clock adjustment module is further configured to:
the clock adjusting system dynamically adjusts the working clock of the corresponding hardware module aiming at the hardware module with low load and low utilization rate so as to achieve the optimal load clock ratio.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
CN202010372685.8A 2020-05-06 2020-05-06 SSD (solid State disk) adaptive load clock adjusting method and device and computer equipment Pending CN111580639A (en)

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