CN111562491A - Programmable logic array FPGA function testing device - Google Patents
Programmable logic array FPGA function testing device Download PDFInfo
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- CN111562491A CN111562491A CN202010470439.6A CN202010470439A CN111562491A CN 111562491 A CN111562491 A CN 111562491A CN 202010470439 A CN202010470439 A CN 202010470439A CN 111562491 A CN111562491 A CN 111562491A
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- 238000012360 testing method Methods 0.000 title claims abstract description 80
- 238000001514 detection method Methods 0.000 claims description 14
- 238000001816 cooling Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000011990 functional testing Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000005855 radiation Effects 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 2
- 238000011161 development Methods 0.000 abstract description 4
- 230000007306 turnover Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012946 outsourcing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
Abstract
The invention discloses a programmable logic array FPGA function testing device, which comprises a test controller, a power supply and a testing device, wherein the power supply is connected with the test controller and supplies power to the test controller; the testing device is composed of a front plate, a bottom plate, a rear plate, an upper plate and two side plates. The programmable logic array FPGA function testing device provided by the invention has the advantages that the size of the testing device is well reduced, the difficulty of FPGA function testing is simplified, the investment cost required by an enterprise to perform FPGA function testing can be effectively reduced, the FPGA function testing can be popularized in the industry better, the leakage probability of business secrets of the enterprise is reduced, and the development of the enterprise is protected better.
Description
Technical Field
The invention belongs to the field of testing, and particularly relates to a programmable logic array FPGA function testing device.
Background
The existing FPGA function test equipment is large in size, poor in convenience and high in setting cost, popularization of FPGA function test is not facilitated, and in order to reduce the cost of FPGA function test, a plurality of enterprises carry out outsourcing test on the FPGA function test, so that development of the enterprises and protection of commercial confidentiality are not facilitated.
Disclosure of Invention
The invention aims to overcome the problems and provide the FPGA function testing device for the programmable logic array, so that the volume of the testing device is well reduced, the difficulty of FPGA function testing is simplified, the cost required by an enterprise to perform FPGA function testing can be effectively reduced, the FPGA function testing can be popularized in the industry better, the leakage probability of business secrets of the enterprise is reduced, and the development of the enterprise is protected better.
The purpose of the invention is realized by the following technical scheme:
the programmable logic array FPGA function test device comprises a test controller, a power supply and a test device, wherein the power supply is connected with the test controller and supplies power to the test controller; the testing device is composed of a front plate, a bottom plate, a rear plate, an upper plate and two side plates.
Preferably, the contact edge positions of the front plate and the bottom plate are connected through loose-leaf sheets, the contact edge positions of the side plates and the bottom plate are connected through loose-leaf sheets, the contact edge positions of the rear plate and the bottom plate are connected through loose-leaf sheets, the upper plate and the rear plate are vertically arranged, and the contact edge positions are fixed into a whole.
Preferably, an FPGA fixing plate is arranged on the upper side face of the bottom plate, the FPGA fixing plate is fixed on the bottom plate through a screw, a limiting sleeve is further sleeved on the screw and located between the FPGA fixing plate and the bottom plate, and the length of the limiting sleeve is at least 2 CM; the bottom plate is also provided with four corner tables, the four corner tables are cubic, and the four corner tables are respectively arranged at the four corners of the upper side surface of the bottom plate; the FPGA fixing plate is plate-shaped, and a plurality of through holes which are strip-shaped or round hole-shaped and penetrate through the FPGA fixing plate are further arranged on the FPGA fixing plate.
Preferably, the front plate is arranged in front of the bottom plate, at least one cooling fan is arranged on the front plate, and protective nets are arranged on the front side and the rear side of each cooling fan; the heat radiation fan is electrically connected with the test controller.
Preferably, the two side plates are respectively symmetrically arranged at the left side and the right side of the bottom plate, at least one wire inlet is arranged on each side plate, and the distance between each wire inlet and the bottom plate is 2 CM.
Preferably, the rear plate is arranged behind the bottom plate, the rear plate is provided with an air outlet, and the air outlet is further provided with a dust screen.
Preferably, the upper plate is arranged on the edge of the upper side of the rear plate, and a limiting card and a temperature detection structure are further arranged on the upper plate; the limiting clamping piece is a metal sheet with an L-shaped section, one side of the limiting clamping piece is fixed on the edge of the upper side surface of the upper plate, and the other side of the limiting clamping piece extends downwards from the edge of the upper side surface of the upper plate until the limiting clamping piece extends out of the lower side surface of the upper plate; the front side edge, the left side edge and the right side edge of the upper plate are respectively provided with at least one limiting card.
Preferably, the temperature detection structure is an infrared scanner, the infrared scanner is perpendicular to the upper plate, and the front end of the infrared scanner penetrates through the upper plate; the infrared scanner is electrically connected with the test controller.
As another preferred mode, the temperature detecting structure is a heat conducting fin, the heat conducting fins are arranged on the upper plate in an array mode, and the heat conducting fins penetrate through the upper plate; and the upper end of the heat conducting sheet is provided with a temperature sensor electrically connected with the test controller.
Further, the specific use method is as follows:
firstly, presetting an automatic test program in a test controller;
fixing the tested FPGA on the FPGA fixing plate;
thirdly, connecting a connecting wire of the test controller with an interface of the FPGA after penetrating through a wire inlet arranged on the side plate;
firstly, the front plate and the two side plates are turned upwards and kept vertical, and then the rear plate is turned upwards to enable the side edges of the limiting clamping pieces to be clamped on the outer side surfaces of the front plate and the two side plates;
fifthly, starting an automatic test program preset in the test controller;
sixthly, the test controller receives feedback information of the tested FPGA;
in the testing process, the testing controller collects the heating condition of the tested FPGA through the temperature detection structure, and starts the cooling fan when the heating of the tested FPGA exceeds a preset value;
and seventhly, the test controller collects the feedback information, the heating condition and the running condition of the cooling fan and displays the feedback information, the heating condition and the running condition of the cooling fan in a table mode.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) the temperature detection structure can be an infrared scanner or a heat conducting fin, and provides more choices for products, so that users can select different structures to match according to self requirements or economic conditions, and the application range of the products is greatly improved.
(2) The invention well reduces the volume of the testing device, simplifies the difficulty of FPGA function test, can effectively reduce the investment cost required by an enterprise to carry out the FPGA function test, can well popularize the FPGA function test in the industry, reduces the leakage probability of business secrets of the enterprise and better protects the development of the enterprise.
Drawings
FIG. 1 is a block diagram of the present invention.
Figure 2 is a front view of one configuration of the present invention.
FIG. 3 is an expanded view of one configuration of the present invention.
Fig. 4 is a front view of another configuration of the present invention.
Fig. 5 is a top view of another structure of the present invention.
Fig. 6 is an expanded view of another configuration of the present invention.
Description of reference numerals: 1. a front plate; 2. a base plate; 3. a side plate; 4. a back plate; 5. an upper plate; 6. a limiting card; 7. an infrared scanner; 8. a heat radiation fan; 9. an air outlet; 10. a wire inlet; 11. a loose-leaf sheet; 12. a corner platform; 13. an FPGA fixing plate; 14. a heat conductive sheet.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1 to 4, the functional test device for a programmable logic array FPGA includes a test controller, a power supply connected to the test controller and supplying power to the test controller, and a test device connected to the test controller and configured to set the FPGA; the testing device is composed of a front plate 1, a bottom plate 2, a rear plate 4, an upper plate 5 and two side plates 3.
The testing device is a cuboid when in use, and in order to facilitate the assembly and the disassembly of the tested FPGA, the testing device selects an expandable structure to be set so as to facilitate the completion of the test.
The contact edge position department of front bezel 1 and bottom plate 2 is connected through loose-leaf piece 11, and the contact edge position department of curb plate 3 and bottom plate 2 is connected through setting up loose-leaf piece 11, and the contact edge position department of back plate 4 and bottom plate 2 is connected through loose-leaf piece 11, and upper plate 5 sets up perpendicularly and contact edge position department is solid as an organic whole with back plate 2.
The loose-leaf piece is prior art, connects through the loose-leaf piece and can make two article that the loose-leaf piece both ends are connected can overturn, and its connection is simple the upset convenient.
The upper side surface of the bottom plate 2 is provided with an FPGA fixing plate 13, the FPGA fixing plate 13 is fixed on the bottom plate 2 through a screw, a limiting sleeve is sleeved on the screw and positioned between the FPGA fixing plate 13 and the bottom plate 2, and the length of the limiting sleeve is at least 2 CM; the bottom plate 2 is also provided with four corner platforms 12, the four corner platforms 12 are cubic, and the four corner platforms are respectively arranged at the four corners of the upper side surface of the bottom plate 2; the FPGA fixed plate 13 is plate-shaped, and a plurality of through holes which are strip-shaped or round hole-shaped and penetrate through the FPGA fixed plate 13 are further arranged on the FPGA fixed plate 13.
The limiting sleeve can be used for regulating and controlling the distance between the FPGA fixing plate and the bottom plate, the length of the limiting sleeve can be adjusted according to different requirements, the gap is reserved between the FPGA fixing plate and the bottom plate, wiring of a connecting line can be facilitated, and the influence of line coverage on the tested FPGA on heating measurement of the tested FPGA and improvement of the heat dissipation effect of the tested FPGA are avoided.
The corner table is arranged to limit the turnover angles of the front plate, the rear plate and the two side plates, so that the situation that the tested FPGA is extruded due to the fact that the turnover angles of the front plate, the rear plate and the two side plates are too large is avoided, and the tested FPGA is better protected from being damaged due to extrusion.
The front plate 1 is arranged in front of the bottom plate 2, at least one radiating fan 8 is arranged on the front plate 1, and protective nets are arranged on the front side and the rear side of each radiating fan 8; the heat dissipation fan 8 is electrically connected with the test controller.
The cooling fan and the protective net are conventional technologies and are generally applied to the field of setting of a computer host and the like, and the setting can be completed by a person skilled in the art without creative labor, so that the detailed description is omitted.
The two side plates 3 are respectively symmetrically arranged at the left side and the right side of the bottom plate 2, at least one wire inlet 10 is arranged on the side plates 3, and the distance between the wire inlet 10 and the bottom plate 2 is 2 CM.
The inlet wire sets up the purpose and provides a passageway for the business turn over of connecting wire, highly prescribes a limit to it sets up in order to make the connecting wire get into the clearance between FPGA fixed plate and the bottom plate that can be better after getting into, avoids the connecting wire to damage because of buckling, has further improved the stability of product use, reduces the appearance of product service failure.
The rear plate 4 is arranged behind the bottom plate 2, an air outlet 9 is arranged on the rear plate 4, and a dust screen is further arranged on the air outlet 9.
The air outlet is arranged to provide an output channel for airflow blown by the cooling fan, so that the tested FPGA can be well cooled.
The upper plate 5 is arranged on the edge of the upper side of the rear plate 4, and the upper plate 5 is also provided with a limiting card 6 and a temperature detection structure; the limiting clamping piece 6 is a metal sheet with an L-shaped section, one side of the limiting clamping piece 6 is fixed on the edge of the upper side surface of the upper plate 5, and the other side of the limiting clamping piece 6 extends downwards from the edge of the upper side surface of the upper plate 5 until the limiting clamping piece extends out of the lower side surface of the upper plate 5; the front edge, the left edge and the right edge of the upper plate 5 are respectively provided with at least one limit card 6.
The purpose of setting up of spacing card is to avoid the product to rise or operating personnel mistake when using because of inside atmospheric pressure touches reasons such as and expand passively, has improved the stability that the product used.
The temperature detection structure is an infrared scanner 7, the infrared scanner 7 is perpendicular to the upper plate 5, and the front end of the infrared scanner 7 penetrates through the upper plate 5; the infrared scanner 7 is electrically connected with the test controller.
The infrared scanner is the prior art, and its setting purpose is to carry out image acquisition to the FPGA that is surveyed to carry out the analysis according to the image acquisition to the condition of generating heat of the FPGA that is surveyed, in order to accomplish the statistics of calorific capacity of the FPGA that is surveyed.
Example 2
The present embodiment is different from embodiment 1 only in that, as shown in fig. 5 and 6, the temperature detection structure is a heat conduction sheet 14, the heat conduction sheets 14 are arranged in an array on the upper plate 5, and the heat conduction sheets 14 penetrate through the upper plate 5; the upper end of the heat conducting fin 14 is provided with a temperature sensor electrically connected with a test controller.
The conducting strip adopts the copper-aluminum alloy to make, need set up heat conduction silica gel layer in order to prevent that the FPGA that is surveyed from taking place the short circuit at the least significant end of conducting strip. Compared with an infrared scanner, the cost of the temperature detection structure can be greatly reduced by adopting a heat conducting sheet mode.
Example 3
The specific using method comprises the following steps:
firstly, presetting an automatic test program in a test controller;
the automatic test program is the prior art in the field, and a person skilled in the art can set a corresponding test program according to the tested FPGA to complete the detection thereof, which is not described herein again.
Secondly, fixing the tested FPGA on the FPGA fixing plate 13;
the through holes arranged on the FPGA fixing plate are reserved fixing positions of the tested FPGA, a person skilled in the art can fix the tested FPGA on different through holes through screws according to the tested FPGA, the specific fixing mode is the prior art in the art, and the person skilled in the art can fix the tested FPGA according to the above contents without creative labor.
Thirdly, connecting a connecting wire of the test controller with an interface of the FPGA after passing through a wire inlet 10 arranged on the side plate 3;
because the distance of incoming line and bottom plate is 2CM, and limit sleeve's length is 2CM at least, so make the connecting wire of getting into can not be buckled just get into the clearance between FPGA fixed plate and the bottom plate, very big
Fourthly, firstly, the front plate 1 and the two side plates 3 are turned upwards and kept vertical, and then the rear plate 4 is turned upwards and the side edges of the limiting clamping pieces 6 are clamped on the outer side surfaces of the front plate 1 and the two side plates 3;
in order to improve the use effect of the limiting card, the contact surface of the limiting card and the front plate and the contact surface of the two side plates can be set to be slope, so that the friction between the limiting card and the front plate and the friction between the limiting card and the two side plates are reduced, and the structural integrity of a product is better protected.
Fifthly, starting an automatic test program preset in the test controller;
sixthly, the test controller receives feedback information of the tested FPGA;
in the testing process, the testing controller collects the heating condition of the tested FPGA through the temperature detection structure, and starts the cooling fan 8 when the heating of the tested FPGA exceeds a preset value;
and seventhly, the test controller collects the feedback information, the heating condition and the running condition of the cooling fan and displays the feedback information, the heating condition and the running condition of the cooling fan in a table mode.
As described above, the present invention can be preferably realized.
Claims (10)
1. Programmable logic array FPGA functional test device, its characterized in that: the FPGA test system comprises a test controller, a power supply and a test device, wherein the power supply is connected with the test controller and supplies power to the test controller; the testing device is composed of a front plate (1), a bottom plate (2), a rear plate (4), an upper plate (5) and two side plates (3).
2. The FPGA functional test device of claim 1, wherein: the contact edge position department of front bezel (1) and bottom plate (2) is connected through loose-leaf piece (11), and the contact edge position department of curb plate (3) and bottom plate (2) is connected through setting up loose-leaf piece (11), and the contact edge position department of back plate (4) and bottom plate (2) is connected through loose-leaf piece (11), and upper plate (5) set up perpendicularly and contact edge position department is solid as an organic whole with back plate (2).
3. The FPGA functional test device of claim 2, wherein: the upper side surface of the bottom plate (2) is provided with an FPGA fixing plate (13), the FPGA fixing plate (13) is fixed on the bottom plate (2) through a screw, a limiting sleeve is sleeved on the screw and positioned between the FPGA fixing plate (13) and the bottom plate (2), and the length of the limiting sleeve is at least 2 CM; the bottom plate (2) is also provided with four corner platforms (12), the four corner platforms (12) are cubic, and the four corner platforms are respectively arranged at four corners of the upper side surface of the bottom plate (2); the FPGA fixing plate (13) is plate-shaped, and a plurality of strip-shaped or round hole-shaped through holes penetrating through the FPGA fixing plate (13) are further arranged on the FPGA fixing plate (13).
4. The FPGA functional test device of claim 3, wherein: the front plate (1) is arranged in front of the bottom plate (2), at least one radiating fan (8) is arranged on the front plate (1), and protective nets are arranged on the front side and the rear side of each radiating fan (8); the heat radiation fan (8) is electrically connected with the test controller.
5. The FPGA functional test device of claim 4, wherein: the two side plates (3) are respectively symmetrically arranged at the left side and the right side of the bottom plate (2), at least one wire inlet (10) is formed in each side plate (3), and the distance between each wire inlet (10) and the bottom plate (2) is 2 CM.
6. The FPGA functional test device of claim 5, wherein: the rear plate (4) is arranged behind the bottom plate (2), an air outlet (9) is formed in the rear plate (4), and a dust screen is further arranged on the air outlet (9).
7. The FPGA functional test device of claim 6, wherein: the upper plate (5) is arranged on the edge of the upper side of the rear plate (4), and a limiting card (6) and a temperature detection structure are further arranged on the upper plate (5); the limiting clamping piece (6) is a metal sheet with an L-shaped section, one side of the limiting clamping piece (6) is fixed on the edge of the upper side face of the upper plate (5), and the other side of the limiting clamping piece (6) extends downwards from the edge of the upper side face of the upper plate (5) until the limiting clamping piece extends out of the lower side face of the upper plate (5); the front edge, the left edge and the right edge of the upper plate (5) are respectively provided with at least one limiting card (6).
8. The FPGA functional test device of claim 7, wherein: the temperature detection structure is an infrared scanner (7), the infrared scanner (7) is perpendicular to the upper plate (5), and the front end of the infrared scanner (7) penetrates through the upper plate (5); the infrared scanner (7) is electrically connected with the test controller.
9. The FPGA functional test device of claim 7, wherein: the temperature detection structure is a heat conducting fin (14), the heat conducting fins (14) are arranged on the upper plate (5) in an array, and the heat conducting fins (14) penetrate through the upper plate (5); and the upper end of the heat conducting sheet (14) is provided with a temperature sensor electrically connected with the test controller.
10. The FPGA functional test device of any one of claims 8 or 9, wherein: the specific using method comprises the following steps:
firstly, presetting an automatic test program in a test controller;
fixing the tested FPGA on an FPGA fixing plate (13);
thirdly, connecting a connecting wire of the test controller with an interface of the FPGA after penetrating through a wire inlet (10) arranged on the side plate (3);
firstly, the front plate (1) and the two side plates (3) are turned upwards and kept vertical, and then the rear plate (4) is turned upwards and the side edges of the limiting clamping pieces (6) are clamped on the outer side surfaces of the front plate (1) and the two side plates (3);
fifthly, starting an automatic test program preset in the test controller;
sixthly, the test controller receives feedback information of the tested FPGA;
in the testing process, the testing controller collects the heating condition of the tested FPGA through the temperature detection structure, and starts the cooling fan (8) when the heating of the tested FPGA exceeds a preset value;
and seventhly, the test controller collects the feedback information, the heating condition and the running condition of the cooling fan and displays the feedback information, the heating condition and the running condition of the cooling fan in a table mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010470439.6A CN111562491A (en) | 2020-05-28 | 2020-05-28 | Programmable logic array FPGA function testing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010470439.6A CN111562491A (en) | 2020-05-28 | 2020-05-28 | Programmable logic array FPGA function testing device |
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| CN111562491A true CN111562491A (en) | 2020-08-21 |
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| CN202010470439.6A Pending CN111562491A (en) | 2020-05-28 | 2020-05-28 | Programmable logic array FPGA function testing device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040252090A1 (en) * | 2003-06-11 | 2004-12-16 | Toppoly Optoelectronics Corp. | Light-on aging test system for flat panel display |
| CN201359710Y (en) * | 2008-12-12 | 2009-12-09 | 钟立 | Novel computer case |
| CN107994178A (en) * | 2017-12-29 | 2018-05-04 | 苏州卡斯迈金属科技有限公司 | A kind of electric automobile battery box |
| CN108037445A (en) * | 2017-11-23 | 2018-05-15 | 中科亿海微电子科技（苏州）有限公司 | FPGA aging tests system and its circuit collocation method |
-
2020
- 2020-05-28 CN CN202010470439.6A patent/CN111562491A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040252090A1 (en) * | 2003-06-11 | 2004-12-16 | Toppoly Optoelectronics Corp. | Light-on aging test system for flat panel display |
| CN201359710Y (en) * | 2008-12-12 | 2009-12-09 | 钟立 | Novel computer case |
| CN108037445A (en) * | 2017-11-23 | 2018-05-15 | 中科亿海微电子科技（苏州）有限公司 | FPGA aging tests system and its circuit collocation method |
| CN107994178A (en) * | 2017-12-29 | 2018-05-04 | 苏州卡斯迈金属科技有限公司 | A kind of electric automobile battery box |
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Application publication date: 20200821 |