CN111554616A

CN111554616A - Chip packaging method

Info

Publication number: CN111554616A
Application number: CN202010365946.3A
Authority: CN
Inventors: 李红雷
Original assignee: Nantong Fujitsu Microelectronics Co Ltd
Current assignee: Nantong Fujitsu Microelectronics Co Ltd
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-08-18
Anticipated expiration: 2040-04-30
Also published as: CN111554616B

Abstract

The application discloses a chip packaging method, which comprises the following steps: providing a first package body and a second package body; the first packaging body comprises at least one first packaging unit, the first packaging unit comprises a first main chip, a second main chip and a first plastic packaging layer, wherein the first main chip and the second main chip are arranged adjacently; the second packaging body comprises at least one connecting chip, a plurality of first conductive columns and a second plastic packaging layer, wherein the periphery of each connecting chip is provided with a plurality of first conductive columns; electrically connecting the non-signal transmission areas of the first main chip and the second main chip with one side of the first conductive column close to the functional surface of the connecting chip, and electrically connecting the signal transmission areas of the first main chip and the second main chip with the functional surface of the connecting chip; and electrically connecting the surface of one side of the first conductive column, which is far away from the first packaging body, with the packaging substrate. The chip packaging method provided by the application can reduce the packaging cost and improve the performance of the packaged device.

Description

Chip packaging method

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.

Background

The existing polymer-based 2D packaging technology is the most basic and widely applied packaging form, is mature in technology and low in cost, but has no connection in the third direction and is large in line width. The recently developed packaging technology based on the silicon interposer is small in line width, and the formed packaged device is excellent in electrical performance and thermal conductivity, but high in cost, and the silicon material is high in brittleness, so that the stability of the packaged device is low. Therefore, there is a need to develop a new packaging technique that combines the advantages of the existing packaging techniques, can reduce the cost, and can form a packaged device with excellent performance.

Disclosure of Invention

The technical problem mainly solved by the application is to provide a chip packaging method, which can reduce the packaging cost and improve the performance of a packaged device.

In order to solve the technical problem, the application adopts a technical scheme that:

a chip packaging method is provided, which comprises the following steps: providing a first package body and a second package body; the first packaging body comprises at least one first packaging unit, the first packaging unit comprises a first main chip, a second main chip and a first plastic packaging layer, the first main chip and the second main chip are arranged adjacently, signal transmission areas of the first main chip and the second main chip are arranged adjacently, and the first plastic packaging layer covers the side surfaces of the first main chip and the second main chip; the second packaging body comprises at least one connecting chip, a plurality of first conductive columns and a second plastic packaging layer, wherein the periphery of each connecting chip is provided with the plurality of first conductive columns, and the second plastic packaging layer covers the connecting chip and the side faces of the first conductive columns; electrically connecting the non-signal transmission areas of the first main chip and the second main chip with one side of the first conductive column close to the functional surface of the connecting chip, and electrically connecting the signal transmission areas of the first main chip and the second main chip with the functional surface of the connecting chip; and electrically connecting the surface of one side, far away from the first packaging body, of the first conductive column with a packaging substrate.

Wherein the providing a first package comprises: providing a removable first carrier plate, wherein at least one area is defined on the first carrier plate; adhering the first main chip and the second main chip to each region, wherein the functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission regions of the first main chip and the second main chip are arranged adjacently; forming the first plastic package layer on one side of the first carrier plate, where the first main chip and the second main chip are arranged; and removing the first carrier plate.

Alternatively, the providing of the first package body includes: providing a removable first carrier plate, wherein at least one area is defined on the first carrier plate; adhering the first main chip and the second main chip to each region, wherein the non-functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission regions of the first main chip and the second main chip are arranged adjacently; forming a first plastic package layer on one side of the first carrier plate, where the first main chip and the second main chip are arranged, and exposing the functional surfaces of the first main chip and the second main chip from the first plastic package layer; and removing the first carrier plate.

Wherein the providing the second package comprises: providing a removable second carrier plate, wherein at least one area is defined on the second carrier plate; forming a plurality of first conductive pillars at each of the region edges; the connecting chip is adhered to the inner side of each area, the non-functional surface of the connecting chip faces the second carrier plate, and second conductive columns are arranged at the positions of bonding pads on the functional surface of the connecting chip respectively; and a second plastic package layer is formed on one side of the second carrier plate, which is provided with the connecting chip, and the surfaces of one sides, far away from the second carrier plate, of the first conductive columns and the second conductive columns are exposed out of the second plastic package layer.

Alternatively, the providing the second package body includes: providing a removable third carrier plate, wherein at least one area is defined on the third carrier plate; forming a plurality of first conductive pillars at each of the region edges; the connecting chip is adhered to the inner side of each area, the functional surface of the connecting chip faces the third carrier plate, and second conductive posts are arranged at the positions of bonding pads on the functional surface of the connecting chip respectively; forming a second plastic package layer on one side of the third carrier board, where the connection chip is disposed, exposing a surface of one side, away from the third carrier board, of the first conductive pillar from the second plastic package layer, where the height of the first conductive pillar is greater than or equal to a distance between a non-functional surface of the connection chip and a surface of one side, close to the first conductive pillar, of the third carrier board; removing the third carrier plate; and adhering the surface of one side, close to the non-functional surface of the connecting chip, of the first conductive column to a removable second carrier plate.

The non-signal transmission area of the first main chip and the non-signal transmission area of the second main chip are electrically connected with one side, close to the functional surface of the connecting chip, of the first conductive column, the signal transmission area of the first main chip and the signal transmission area of the second main chip are electrically connected with the functional surface of the connecting chip, and then the distance between the functional surface of the first main chip and the surface of one side, far away from the first packaging body, of the second plastic packaging layer is larger than or equal to the distance between the functional surface of the first main chip and the non-functional surface of the connecting chip.

Wherein, the non-signal transmission area of the first main chip and the second main chip is electrically connected with one side of the first conductive pillar, which is close to the functional surface of the connection chip, and the signal transmission area of the first main chip and the second main chip is electrically connected with the functional surface of the connection chip, and then, the method comprises the following steps: forming a first underfill between the functional surfaces of the first main chip and the second package body; and removing the second carrier plate.

Wherein, said one side surface of keeping away from the first packaging body with first conductive pillar is connected with the encapsulation base plate electricity, later, includes: and forming a second underfill between the second packaging body and the packaging substrate.

Wherein, after the providing the first package body, the method comprises: and forming the third conductive column on the bonding pad of the first main chip and the second main chip, which is located in the non-signal transmission area, and forming the fourth conductive column on the bonding pad of the first main chip and the second main chip, which is located in the signal transmission area.

The first packaging body comprises at least two first packaging units, and the first plastic packaging layers of the adjacent first packaging units are connected with each other; after the providing the first package, the method includes: and cutting off the area between the adjacent first packaging units to obtain a structure containing a single first packaging unit.

The beneficial effect of this application is: different from the prior art, the chip packaging method provided by the application adopts different connection modes for the signal transmission area and the non-signal transmission area of the main chip: for the signal transmission area, a connecting chip is adopted to connect the two main chips, so that the signal transmission rate between the main chips is improved, and the performance of a packaged device is improved; for the non-signal transmission area, the common conductive column is connected with the packaging substrate, so that the packaging cost can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:

FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;

FIG. 2a is a schematic structural diagram of an embodiment of a first package;

FIG. 2b is a schematic structural diagram of an embodiment of a second package;

FIG. 3 is a schematic flow chart diagram illustrating one embodiment of providing a first package;

FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 3;

FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 3;

FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 3;

FIG. 5 is a schematic flow chart diagram illustrating another embodiment of providing a first package;

FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 5;

FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S303 in FIG. 5;

FIG. 6c is a schematic structural diagram of another embodiment corresponding to step S303 in FIG. 5;

FIG. 6d is a schematic structural diagram of an embodiment corresponding to step S304 in FIG. 5;

FIG. 7 is a schematic structural diagram of an embodiment corresponding to the steps included after providing the first package;

FIG. 8 is a schematic structural diagram of another embodiment of the first package;

FIG. 9 is a schematic flow chart diagram illustrating one embodiment of providing a second package;

FIG. 10a is a schematic structural diagram of an embodiment corresponding to step S402 in FIG. 9;

FIG. 10b is a schematic structural diagram of an embodiment corresponding to step S403 in FIG. 9;

FIG. 10c is a schematic structural diagram of an embodiment corresponding to step S404 in FIG. 9;

FIG. 11 is a schematic flow chart diagram illustrating another embodiment of providing a second package;

FIG. 12a is a schematic structural diagram of an embodiment corresponding to step S503 in FIG. 11;

FIG. 12b is a schematic structural diagram of an embodiment corresponding to step S504 in FIG. 11;

FIG. 12c is a schematic structural diagram of an embodiment corresponding to step S505 in FIG. 11;

FIG. 12d is a schematic structural diagram of an embodiment corresponding to step S506 in FIG. 11;

FIG. 13 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;

FIG. 14 is a flowchart illustration of an embodiment of steps included after step S102 in FIG. 1;

FIG. 15a is a schematic structural diagram of an embodiment corresponding to step S601 in FIG. 14;

FIG. 15b is a schematic structural diagram of an embodiment corresponding to step S602 in FIG. 14;

FIG. 16 is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;

fig. 17 is a schematic structural diagram of an embodiment corresponding to the step included after step S103 in fig. 1.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the chip packaging method including the following steps:

s101, providing a first packaging body and a second packaging body; the first packaging body comprises at least one first packaging unit, the first packaging unit comprises a first main chip, a second main chip and a first plastic packaging layer, the first main chip and the second main chip are arranged adjacently, signal transmission areas of the first main chip and the second main chip are arranged adjacently, and the first plastic packaging layer covers the side surfaces of the first main chip and the second main chip; the second packaging body comprises at least one connecting chip, a plurality of first conductive columns and a second plastic packaging layer, wherein the periphery of each connecting chip is provided with the plurality of first conductive columns, and the second plastic packaging layer covers the side faces of the connecting chip and the first conductive columns.

Specifically, referring to fig. 2a and 2b, fig. 2a is a schematic structural diagram of an embodiment of a first package, and fig. 2b is a schematic structural diagram of an embodiment of a second package. Fig. 2a only schematically shows the case where the first package body comprises a first package unit, the first package unit comprising a first main chip 11 and a second main chip 12 adjacently arranged, and a first molding compound layer 13; the signal transmission regions 600 of the first main chip 11 and the second main chip 12 are disposed adjacent to each other, and the first molding compound layer 13 covers the side surfaces of the first main chip 11 and the second main chip 12. Fig. 2b only schematically illustrates the case where the second package comprises one connection chip 31, and in other embodiments, the second package may comprise a plurality of connection chips 31. In fig. 2b, the second package further includes a plurality of first conductive pillars 32 and a second molding compound layer 33, wherein the plurality of first conductive pillars 32 are disposed on the periphery of the connection chip 31, and the second molding compound layer 33 covers the side surface of the connection chip 31 and the side surface of the first conductive pillars 32. In order to facilitate the subsequent step S102, the first package and the second package are electrically connected, and the second package is kept attached to the carrier.

In one embodiment, referring to fig. 3, fig. 3 is a schematic flowchart of an embodiment of providing a first package, where the providing the first package in step S101 specifically includes the following steps:

s201, a removable first carrier is provided, and at least one area is defined on the first carrier.

Specifically, referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 3. The figure schematically illustrates that an area is defined on the first carrier 10, wherein the first carrier 10 is formed of a hard material such as metal, plastic, etc.

S202, adhering a first main chip and a second main chip to each area, wherein the functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission areas of the first main chip and the second main chip are arranged adjacently.

Specifically, please refer to fig. 4b, wherein fig. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 3. In this embodiment, the first main chip 11 and the second main chip 12 are attached to the first carrier 10 defining an area, the

functional surfaces

110 and 120 of the first main chip 11 and the second main chip 12 face the first carrier 10, and the signal transmission areas 600 of the first main chip 11 and the second main chip 12 are disposed adjacent to each other. Specifically, the first main chip 11 and the second main chip 12 may be attached to the first carrier 10 by a peelable adhesive such as a double-sided adhesive tape.

S203, forming a first plastic package layer on one side of the first carrier plate, where the first main chip and the second main chip are arranged.

Specifically, please refer to fig. 4c, wherein fig. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 3. A first molding layer 13 is formed on one side of the first carrier 10 where the first main chip 11 and the second main chip 12 are disposed. The first molding layer 13 covers the side surfaces of the first main chip 11 and the second main chip 12, and the

non-functional surfaces

111 and 121 of the first main chip 11 and the second main chip 12 may or may not be exposed from the first molding layer 13. The first molding compound layer 13 may be made of epoxy resin, and may protect the first main chip 11 and the second main chip 12.

In the step S203, a first molding compound layer 13 may be formed on one side of the first carrier 10, and the first molding compound layer 13 covers the

non-functional surfaces

111 and 121 of the first main chip 11 and the second main chip 12; then, grinding the surface of one side of the first plastic package layer 13 away from the first carrier plate 10 to flatten the surface of the first plastic package layer 13 and expose the

non-functional surfaces

111 and 121 of the first main chip 11 and the second main chip 12 from the first plastic package layer 13; or controlling the grinding process to flatten the surface of the first molding layer 13, while the

non-functional surfaces

111 and 121 of the first main chip 11 and the second main chip 12 are not exposed from the first molding layer 13. Fig. 4c schematically shows a case where the

non-functional surfaces

111 and 121 of the first and second

main chips

11 and 12 are not exposed from the first molding layer 13.

S204, removing the first carrier plate.

Specifically, referring to fig. 2a, after the carrier 10 is removed, the formed first package body includes a package unit 100, where the package unit 100 includes a first main chip 11 and a second main chip 12 that are adjacently disposed, and a first molding compound layer 13; the signal transmission regions 600 of the first main chip 11 and the second main chip 12 are disposed adjacent to each other, and the first molding compound layer 13 covers the side surfaces of the first main chip 11 and the second main chip 12.

In another embodiment, referring to fig. 5, fig. 5 is a schematic flow chart of another embodiment of providing a first package, and the providing the first package in step S101 may further include:

s301, a removable first carrier is provided, and at least one region is defined on the first carrier.

S302, a first main chip and a second main chip are pasted in each area, the non-functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission areas of the first main chip and the second main chip are arranged adjacently.

Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to step S302 in fig. 5. In this embodiment, the first main chip 21 and the second main chip 22 are attached to the first carrier 20, which defines an area, and the

non-functional surfaces

211 and 221 of the first main chip 21 and the second main chip 22 face the first carrier 20, and the signal transmission areas 600 of the first main chip 21 and the second main chip 22 are disposed adjacent to each other. Specifically, the first main chip 21 and the second main chip 22 may be attached to the first carrier 20 by a peelable adhesive such as a double-sided adhesive tape.

And S303, forming a first plastic package layer on one side of the first carrier plate, which is provided with the first main chip and the second main chip, wherein the functional surfaces of the first main chip and the second main chip are exposed out of the first plastic package layer.

Specifically, please refer to fig. 6b, wherein fig. 6b is a schematic structural diagram of an embodiment corresponding to step S303 in fig. 5. After the first main chip 21 and the second main chip 22 are attached to the first carrier 20 with an area defined, a first molding compound layer 23 is formed on one side of the first carrier 20 where the first main chip 21 and the second main chip 22 are disposed. The first molding layer 23 covers the side surfaces of the first and second

main chips

21 and 22, and the

functional surfaces

210 and 220 of the first and second

main chips

21 and 22 are exposed from the first molding layer 23. The first molding compound layer 23 may be made of epoxy resin, and may protect the first main chip 21 and the second main chip 22.

In another embodiment, please refer to fig. 6c, wherein fig. 6c is a schematic structural diagram of another embodiment corresponding to step S303 in fig. 5. The thickness of the first main chip 21 ' is smaller than that of the second main chip 22 ', and then the height of the first plastic package layer 23 ' is smaller than or equal to the minimum thickness of the first main chip 21 ' and the second main chip 22 ', that is, the height of the first plastic package layer 23 ' is smaller than or equal to the thickness of the first main chip 21 ', fig. 6c schematically illustrates a case that the height of the first plastic package layer 23 ' is equal to the thickness of the first main chip 21 ', and the second main chip 22 ' is in a semi-plastic package state, so as to ensure that the functional surfaces 210 ' and 220 ' of the first main chip 21 ' and the second main chip 22 ' are exposed from the first plastic package layer 23 '.

S304, removing the first carrier plate.

Specifically, please refer to fig. 6d, wherein fig. 6d is a schematic structural diagram of an embodiment corresponding to step S304 in fig. 5. After removing the first carrier 20, the formed first package body includes a first package unit, the first package unit includes a first main chip 21 and a second main chip 22 which are adjacently disposed, and a first molding compound layer 23; the signal transmission areas 600 of the first main chip 21 and the second main chip 22 are adjacently disposed, the first molding compound layer 23 covers the side surfaces of the first main chip 21 and the second main chip 22, and the

functional surfaces

210 and 220 of the first main chip 21 and the second main chip 22 are exposed from the first molding compound layer 23.

Further, referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment corresponding to steps included after providing the first package, and after forming the first package shown in fig. 2a or fig. 6d, taking the structure shown in fig. 2a as an example, the method further includes: the third conductive pillars 14 are formed on the pads of the first and second

main chips

11 and 12 located at the non-signal transmission area 700, and the fourth conductive pillars 15 are formed on the pads of the first and second

main chips

11 and 12 located at the signal transmission area 600. Before this, the structure shown in fig. 2a may be turned over as a whole. The heights of the third conductive pillars 14 and the fourth conductive pillars 15 are not particularly limited as long as they can be connected to the second package body later. The order of the time nodes for forming the third conductive pillars 14 and the fourth conductive pillars 15 is not limited, for example, the third conductive pillars 14 may be formed first, the fourth conductive pillars 15 may be formed first, or both the third conductive pillars 14 and the fourth conductive pillars 15 may be formed simultaneously. The third conductive pillar 14 and the fourth conductive pillar 15 are made of copper-containing alloy, and may be formed by electroplating or the like. For example, a patterned first mask layer may be formed on the surface of the first plastic package layer 13, a via hole is formed on the first mask layer, then a third conductive pillar 14 is formed in the via hole, and finally the first mask layer is removed; and then, a patterned second mask layer is formed on the surface of the first plastic package layer 13, a via hole is formed in the second mask layer, a fourth conductive pillar 15 is formed in the via hole, and finally, the second mask layer is removed.

Further, with reference to fig. 7, after the third conductive pillars 14 and the fourth conductive pillars 15 are formed, a first solder 16 may be formed on the surfaces of the third conductive pillars 14 and the fourth conductive pillars 15 away from the first main chip 11, where the first solder 16 is made of an electrically and thermally conductive material, so as to be electrically connected to the second package body in a subsequent step.

In another embodiment, please refer to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of a first package body, the first package body includes at least two first package units 100, and first molding compounds 13 of adjacent first package units 100 are connected to each other, that is, the first molding compounds 13 in the first package body are an integral body; after providing the first package, the method includes: the area between adjacent first packaging units 100 is cut away, for example along the dashed line 800 in the figure, to obtain a structure comprising a single first packaging unit 100 as shown in fig. 2 a.

In one embodiment, referring to fig. 9, fig. 9 is a schematic flowchart of an embodiment of providing a second package, where the providing the second package in step S101 specifically includes the following steps:

s401, providing a removable second carrier, wherein at least one region is defined on the second carrier.

S402, forming a plurality of first conductive pillars at the edge of each region.

Specifically, referring to fig. 10a, fig. 10a is a schematic structural diagram of an embodiment corresponding to step S402 in fig. 9. In the present embodiment, a plurality of first conductive pillars 32 are formed at the edge of the region of the second carrier 30 where one region is defined, and the material of the first conductive pillars 32 is an alloy containing copper, which can be formed by electroplating or the like. For example, a patterned mask layer may be formed on the surface of the second carrier 30, a via hole is formed on the mask layer, the first conductive pillar 32 is formed in the via hole, and finally the mask layer is removed.

And S403, adhering a connecting chip to the inner side of each region, wherein the non-functional surface of the connecting chip faces the second carrier plate, and second conductive posts are respectively arranged at the positions of the pads on the functional surface of the connecting chip.

Specifically, please refer to fig. 10b, wherein fig. 10b is a schematic structural diagram of an embodiment corresponding to step S403 in fig. 9. In the present embodiment, the connection chip 31 is attached to the inner side of the area of the second carrier 30 defining one area, the non-functional surface 311 of the connection chip 31 faces the second carrier 30, and the second conductive pillars 34 are respectively disposed at the pad positions on the functional surface 310 of the connection chip 31. Specifically, the non-functional surface 311 of the connecting chip 31 and the second carrier 30 can be adhered by a peelable adhesive such as a double-sided adhesive.

In addition, the present application is not limited to the point in time when the second conductive pillar 34 is formed. For example, the functional surface 310 of the connection chip 31 may be formed in advance before the above step S401 or step S402, or the non-functional surface 311 of the connection chip 31 and the second carrier 30 may be attached first and then the second conductive pillars 34 may be formed on the functional surface 310 of the connection chip 31 when the step S403 is performed. The second conductive pillars 34 may be made of a material similar to that of the first conductive pillars 32, such as copper, and may be formed in a similar manner.

S404, a second plastic package layer is formed on one side of the second carrier where the chip is connected, and the surfaces of the first conductive pillars and the second conductive pillars, which are far away from the second carrier, are exposed from the second plastic package layer.

Specifically, please refer to fig. 10c, wherein fig. 10c is a schematic structural diagram of an embodiment corresponding to step S404 in fig. 9. A second molding layer 33 is formed on the side of the second carrier plate 30 where the connecting chip 31 is disposed, and surfaces of the second conductive pillars 34 and the first conductive pillars 32 away from the second carrier plate 30 are exposed from the second molding layer 33. The second molding compound layer 33 may be made of epoxy resin, and can protect the connection chip 31, the first conductive pillar 32, and the second conductive pillar 34. The structure shown in fig. 10c is the structure shown in fig. 2b attached to the second carrier 30.

In addition, in the step S403, the height of the first conductive pillar 32 may be greater than the thickness of the connection chip 31, and the height of the first conductive pillar 32 may be greater than or equal to the sum of the thickness of the connection chip 31 and the height of the second conductive pillar 34, and more preferably, the height of the first conductive pillar 32 is equal to the sum of the thickness of the connection chip 31 and the height of the second conductive pillar 34. In the step S404, a second molding compound layer 33 may be formed on one side of the second carrier 30, and the second molding compound layer 33 covers the surfaces of the first conductive pillars 32 and the second conductive pillars 34 away from the second carrier 30; then, the surface of the second molding compound layer 33 away from the second carrier plate 30 is ground, so that the surfaces of the first conductive pillars 32 and the second conductive pillars 34 away from the second carrier plate 30 are flush and exposed from the second molding compound layer 33.

In another embodiment, referring to fig. 11, fig. 11 is a schematic flowchart of another embodiment of providing a second package, and the providing the second package in step S101 may further include:

s501, providing a removable third carrier, wherein at least one region is defined on the third carrier.

S502, forming a plurality of first conductive pillars at the edge of each region.

Step S501 and step S502 are the same as step S401 and step S402, respectively, and are not described again here.

S503, the connecting chip is pasted on the inner side of each area, the functional surface of the connecting chip faces the third carrier plate, and second conductive posts are respectively arranged at the positions of the pads on the functional surface of the connecting chip.

Specifically, referring to fig. 12a, fig. 12a is a schematic structural diagram of an embodiment corresponding to step S503 in fig. 11. The third carrier 45 is schematically illustrated as defining an area, a plurality of first conductive pillars 42 are formed at an edge of the area, the connection chip 41 is adhered to an inner side of the area, the functional surface 410 of the connection chip 41 faces the third carrier 45, second conductive pillars 44 are respectively disposed at pad positions on the functional surface 410 of the connection chip 41, and the non-functional surface 411 of the connection chip 41 is far away from the third carrier 45.

In addition, in the present embodiment, the time point when the second conductive pillar 44 is formed may be formed on the functional surface 410 of the connection chip 41 in advance before the step S503.

And S504, forming a second plastic package layer on the side of the third carrier board where the connection chip is disposed, exposing the surface of the first conductive pillar, which is far away from the third carrier board, from the second plastic package layer, and making the height of the first conductive pillar greater than or equal to the distance between the non-functional surface of the connection chip and the surface of the third carrier board, which is close to the first conductive pillar.

Specifically, referring to fig. 12b, fig. 12b is a schematic structural diagram of an embodiment corresponding to step S504 in fig. 11. In this embodiment, the second molding layer 43 is formed on the side of the third carrier plate 45 where the connection chip 41 is disposed, the thickness of the second molding layer 43 is preferably the same as the height of the first conductive pillar 42, the height of the first conductive pillar 42 is greater than or equal to the distance between the non-functional surface 411 of the connection chip 41 and the surface of the third carrier plate 45 close to the first conductive pillar 42, and at this time, the surface of the first conductive pillar 42 far from the third carrier plate 45 is exposed from the second molding layer 43. The non-functional surface 411 of the connection chip 41 may or may not be exposed from the second molding layer 43. The second molding compound layer 43 may be made of epoxy resin, and can protect the connection chip 41, the first conductive pillar 42, and the second conductive pillar 44.

And S505, removing the third carrier plate.

Specifically, referring to fig. 12c, fig. 12c is a schematic structural diagram of an embodiment corresponding to step S505 in fig. 11. After removing the third carrier plate 45, a second package similar to fig. 2b is obtained, including the connection chip 41 and the plurality of first conductive pillars 42 disposed at the periphery of the connection chip 41, and the second molding layer 43, where the second molding layer 43 covers the side surfaces of the connection chip 41 and the side surfaces of the first conductive pillars 42.

S506, the surface of one side of the first conductive pillar, which is close to the non-functional surface of the connection chip, is adhered to the removable second carrier.

Specifically, referring to fig. 12d, fig. 12d is a schematic structural diagram of an embodiment corresponding to step S506 in fig. 11. After the second package shown in fig. 12c is formed, in order to facilitate the subsequent step S102, i.e. to electrically connect the first package and the second package, the second package shown in fig. 12c needs to be kept in a state of being attached to the carrier, in this embodiment, the structure shown in fig. 12c is turned over, and then the surface of the first conductive pillar 42 close to the non-functional surface 411 of the connecting chip 41 is attached to the removable second carrier 40.

And S102, electrically connecting the non-signal transmission areas of the first main chip and the second main chip with the surface of one side, close to the functional surface of the connecting chip, of the first conductive column, and electrically connecting the signal transmission areas of the first main chip and the second main chip with the functional surface of the connecting chip.

Specifically, referring to fig. 13, fig. 13 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1. After forming the first package and the second package attached to the second carrier, taking the structure including the first package shown in fig. 7 and the structure including the second package shown in fig. 10c as examples, the non-signal transmission region 700 of the first main chip 11 and the second main chip 12 in the first package is electrically connected to the side of the first conductive pillar 32 in the second package close to the functional surface of the connection chip 31, and the signal transmission region 600 of the first main chip 11 and the second main chip 12 is electrically connected to the functional surface 310 of the connection chip 31. The non-signal transmission areas 700 of the first main chip 11 and the second main chip 12 may be electrically connected to the first conductive pillars 32 through the third conductive pillars 14 and the first solder 16, and the signal transmission areas 600 of the first main chip 11 and the second main chip 12 may be electrically connected to the functional surface 310 of the connection chip 31 through the fourth conductive pillars 15, the second conductive pillars 34 and the first solder 16.

Referring to fig. 13, after step S102 is executed, that is, after the first package and the second package are electrically connected, a distance h between the functional surface 110 of the first main chip 11 and a side surface of the second molding compound 33 away from the first package is provided₁Is greater than or equal to the distance h between the functional surface 110 of the first main chip 11 and the non-functional surface 311 of the connection chip 31₂. In FIG. 13 h is schematically drawn₁Is equal to h₂The case (1).

In addition, the first main chip 11 may be a CPU or the like, the second main chip 12 may be a GPU or the like, and one first main chip 11 may be electrically connected to at least one second main chip 12 through the connection chip 31. For example, the signal transmission region pads are disposed at four corners of the first main chip 11, the number of the second main chips 12 corresponding to one first main chip 11 may be four, and the chip types of the four second main chips 12 may be the same or different.

Further, referring to fig. 14, fig. 14 is a flowchart illustrating an embodiment of a step included after step S102 in fig. 1, and after step S102 is executed, that is, after the first package and the second package are electrically connected, the method includes the following steps:

s601, a first underfill is formed between the functional surfaces of the first main chip and the second package.

Specifically, referring to fig. 15a, fig. 15a is a schematic structural diagram of an embodiment corresponding to step S601 in fig. 14. On the basis of the structure shown in fig. 13, a first underfill 17 is formed between the

functional surfaces

110 and 120 of the first main chip 11 and the second main chip 12 and the second package. The first underfill 17 may protect the second conductive pillars 34, the third conductive pillars 14, and the fourth conductive pillars 15, so that the connection between the first package and the second package is more stable.

S602, removing the second carrier.

Specifically, please refer to fig. 15b, wherein fig. 15b is a schematic structural diagram of an embodiment corresponding to step S602 in fig. 14. After the first underfill 17 is formed, the second carrier 30 needs to be removed for subsequent electrical connection with the package substrate.

Further, referring to fig. 15b, after the second carrier board 30 is removed, a second solder 36 may be formed on a side surface of the first conductive pillar near the non-functional surface 311 of the connection chip 31, wherein the second solder 36 is made of a conductive material, so as to facilitate subsequent electrical connection with the package substrate.

And S103, electrically connecting the surface of one side, away from the first package body, of the first conductive pillar with the package substrate.

Specifically, referring to fig. 16, fig. 16 is a schematic structural view of an embodiment corresponding to step S103 in fig. 1, and the structure shown in fig. 15b is electrically connected to the package substrate 500, wherein a side surface of the first conductive pillar 32 away from the first package body is electrically connected to the package substrate 500, and the first conductive pillar 32 is electrically connected to the package substrate 500 through the second solder 36.

Further, referring to fig. 17, fig. 17 is a schematic structural diagram of an embodiment corresponding to the step included after step S103 in fig. 1, and after electrically connecting the side surface of the first conductive pillar 32 away from the first package body to the package substrate 500, a second underfill 37 may be formed between the second package body and the package substrate 500. The second underfill 37 can protect the first conductive pillars 32, so that the connection between the second package body and the package substrate 500 is more stable.

In the finally formed packaged device in the embodiment, the signal transmission areas of the two main chips are connected by adopting the connecting chip, so that the signal transmission rate between the main chips can be improved, and the performance of the packaged device is improved; the non-signal transmission area of the main chip is connected with the packaging substrate by adopting a common conductive column, so that the packaging cost can be reduced.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A chip packaging method is characterized by comprising the following steps:

providing a first package body and a second package body; the first packaging body comprises at least one first packaging unit, the first packaging unit comprises a first main chip, a second main chip and a first plastic packaging layer, the first main chip and the second main chip are arranged adjacently, signal transmission areas of the first main chip and the second main chip are arranged adjacently, and the first plastic packaging layer covers the side surfaces of the first main chip and the second main chip; the second packaging body comprises at least one connecting chip, a plurality of first conductive columns and a second plastic packaging layer, wherein the periphery of each connecting chip is provided with the plurality of first conductive columns, and the second plastic packaging layer covers the connecting chip and the side faces of the first conductive columns;

electrically connecting the non-signal transmission areas of the first main chip and the second main chip with the surface of one side, close to the functional surface of the connecting chip, of the first conductive column, and electrically connecting the signal transmission areas of the first main chip and the second main chip with the functional surface of the connecting chip;

and electrically connecting the surface of one side, far away from the first packaging body, of the first conductive column with a packaging substrate.

2. The chip packaging method according to claim 1, wherein the providing the first package body comprises:

providing a removable first carrier plate, wherein at least one area is defined on the first carrier plate;

adhering the first main chip and the second main chip to each region, wherein the functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission regions of the first main chip and the second main chip are arranged adjacently;

forming the first plastic package layer on one side of the first carrier plate, where the first main chip and the second main chip are arranged;

and removing the first carrier plate.

3. The chip packaging method according to claim 1, wherein the providing the first package body comprises:

adhering the first main chip and the second main chip to each region, wherein the non-functional surfaces of the first main chip and the second main chip face the first carrier plate, and the signal transmission regions of the first main chip and the second main chip are arranged adjacently;

forming a first plastic package layer on one side of the first carrier plate, where the first main chip and the second main chip are arranged, and exposing the functional surfaces of the first main chip and the second main chip from the first plastic package layer;

and removing the first carrier plate.

4. The chip packaging method according to claim 1, wherein the providing the second package body comprises:

providing a removable second carrier plate, wherein at least one area is defined on the second carrier plate;

forming a plurality of first conductive pillars at each of the region edges;

the connecting chip is adhered to the inner side of each area, the non-functional surface of the connecting chip faces the second carrier plate, and second conductive columns are arranged at the positions of bonding pads on the functional surface of the connecting chip respectively;

and a second plastic package layer is formed on one side of the second carrier plate, which is provided with the connecting chip, and the surfaces of one sides, far away from the second carrier plate, of the first conductive columns and the second conductive columns are exposed out of the second plastic package layer.

5. The chip packaging method according to claim 1, wherein the providing the second package body comprises:

providing a removable third carrier plate, wherein at least one area is defined on the third carrier plate;

forming a plurality of first conductive pillars at each of the region edges;

the connecting chip is adhered to the inner side of each area, the functional surface of the connecting chip faces the third carrier plate, and second conductive posts are arranged at the positions of bonding pads on the functional surface of the connecting chip respectively;

forming a second plastic package layer on one side of the third carrier board, where the connection chip is disposed, exposing a surface of one side, away from the third carrier board, of the first conductive pillar from the second plastic package layer, where the height of the first conductive pillar is greater than or equal to a distance between a non-functional surface of the connection chip and a surface of one side, close to the first conductive pillar, of the third carrier board;

removing the third carrier plate;

and adhering the surface of one side, close to the non-functional surface of the connecting chip, of the first conductive column to a removable second carrier plate.

6. The chip packaging method according to any one of claims 2 to 5,

the non-signal transmission area of the first main chip and the non-signal transmission area of the second main chip are electrically connected with one side, close to the functional surface of the connecting chip, of the first conductive column, the signal transmission area of the first main chip and the signal transmission area of the second main chip are electrically connected with the functional surface of the connecting chip, and then the distance between the functional surface of the first main chip and one side surface, far away from the first packaging body, of the second plastic packaging layer is larger than or equal to the distance between the functional surface of the first main chip and the non-functional surface of the connecting chip.

7. The chip packaging method according to claim 6, wherein the electrically connecting the non-signal transmission regions of the first main chip and the second main chip with the side of the first conductive pillar close to the functional surface of the connection chip and the electrically connecting the signal transmission regions of the first main chip and the second main chip with the functional surface of the connection chip, then includes:

forming a first underfill between the functional surfaces of the first main chip and the second package body;

and removing the second carrier plate.

8. The chip packaging method according to claim 7, wherein the electrically connecting the first conductive pillar to the package substrate at a side surface away from the first package body, and then includes:

and forming a second underfill between the second packaging body and the packaging substrate.

9. The chip packaging method according to claim 2 or 3, wherein after the providing the first package body, the method comprises:

and forming the third conductive column on the bonding pad of the first main chip and the second main chip, which is located in the non-signal transmission area, and forming the fourth conductive column on the bonding pad of the first main chip and the second main chip, which is located in the signal transmission area.

10. The chip packaging method according to claim 1,

the first packaging body comprises at least two first packaging units, and the first plastic packaging layers of the adjacent first packaging units are connected with each other;

after the providing the first package, the method includes: and cutting off the area between the adjacent first packaging units to obtain a structure containing a single first packaging unit.