CN1115515A - Separation purifying voltage stabilizing IC - Google Patents
Separation purifying voltage stabilizing IC Download PDFInfo
- Publication number
- CN1115515A CN1115515A CN 95102626 CN95102626A CN1115515A CN 1115515 A CN1115515 A CN 1115515A CN 95102626 CN95102626 CN 95102626 CN 95102626 A CN95102626 A CN 95102626A CN 1115515 A CN1115515 A CN 1115515A
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- capacitor
- gate controlled
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- controlled switch
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Abstract
The voltage-stabilizing integrated circuit is composed of 4 gate-controlled switches, 4 voltage detecting circuits, capacitor and CPU connected to said switches and detecting circuits, and features very strong anti-interference power. It has excellent decoupling action when used as DC power supply.
Description
The present invention relates to a kind of integrated regulator.
Existing integrated regulator is when work, and electric current generally is to pass through continuously wherein to lack the measure that the external interference signal is isolated fully, and therefore, its antijamming capability is strong inadequately.
The objective of the invention is: a kind of separation purifying voltage stabilizing IC is provided, has extremely strong antijamming capability.
Technical scheme of the present invention is: a kind of separation purifying voltage stabilizing IC, comprise K1, K2, K3 and four gate controlled switches of K4, F1, F2, F3 and four voltage detecting circuits of F4, also comprise first order capacitor C 1 and C2, second level capacitor C 3 and central processor CPU; The input of described gate controlled switch K1, K3 and testing circuit F1 is parallel to the input that the M point connects circuit of the present invention; The input of described gate controlled switch K2, testing circuit F2 and a utmost point of capacitor C 1 are parallel to the output that the O point meets described gate controlled switch K1, another utmost point ground connection of capacitor C 1; The input of described gate controlled switch K4, testing circuit F3 and a utmost point of capacitor C 2 are parallel to the output that the P point meets described gate controlled switch K3, another utmost point ground connection of capacitor C 2; The output of described gate controlled switch K2 and K4 is parallel to the input that the N point connects inductance L 2; One utmost point of the signal input part of the output of described inductance L 2, testing circuit F4 and described second level capacitor C 3 is parallel to the output that the H point connects circuit of the present invention, another utmost point ground connection of capacitor C 3; Described gate controlled switch K1, K2, K3, K4 and testing circuit F1, F2, F3, F4 all link with described central processor CPU and controlled by it.
Aforesaid integrated circuit of the present invention, input current flow into earlier first order capacitor C 1 and C2 and store and carry out separation purifying, and then enter second level capacitor C 3 and carry out filtering output, output be the direct current of no external interference.When circuit of the present invention is used as DC power supply circuit, can save transformer, also can be used as good decoupling circuit.
The present invention is described in more detail below in conjunction with accompanying drawing.
Fig. 1 is a circuit block diagram of the present invention.
As shown in Figure 1, the course of work of circuit of the present invention is as follows: extrinsic current is after full-wave rectification, and L1 flows through, arrive the M point, be divided into two-way then, first via electric current arrives the N point through K1, K2, flow through K3, K4 of the second road electric current arrives the N point, the two-way electric current successively through L2 to output.
The detailed operation process of first via electric current is as follows: K2 closes earlier, and K1 opens subsequently, and this moment, C1 began charging, and promptly C1 enters charge period, and when treating that voltage that F2 detects C1 arrives certain current potential, K1 closes, and the charge period of C1 finishes.This moment, K1, K2 were in closed condition, so C1 was isolated with extraneous completely cutting off fully, can there be any external interference signal in the electric charge that C1 stores, and promptly C1 is equivalent to a pure glitch-free power supply at this moment, and this stage is the purification phase of C1.Treat that K2 opens through an of short duration purification after date, this moment, C1 discharged to C3, and promptly C1 enters the discharge phase, and idle process is after certain discharge time, and K2 closes, and K1 opens subsequently, and this moment, C1 got back to charge period again.This is the charge and discharge process of C1, also is the course of work of first via electric current.
The detailed operation process of the second road electric current is as follows: K4 closes earlier, and K3 opens subsequently, and this moment, C2 began charging, and promptly C2 enters charge period, and when the voltage that idle F3 detects C2 arrived certain current potential, K3 closed, and the charge period of C2 finishes.This moment, K3, K4 were in closed condition, so C2 was isolated with extraneous completely cutting off fully, can there be any external interference signal in the electric charge that C2 stores, and promptly C2 is equivalent to a pure glitch-free power supply at this moment, and this stage is the purification phase of C2.Treat that K4 opens through an of short duration purification after date, this moment, C2 discharged to C3, and promptly C2 enters the discharge phase, treated that K4 closes through after certain discharge time, and K3 opens subsequently, and this moment, C2 got back to charge period again.This is the charge and discharge process of C2, also is the course of work of the second road electric current.
Two-way electric current alternating current carries out filtering output through C3.
The rated value of H end output voltage is kept by the discharge of C1, C2.The variation of H terminal potential was directly proportional with the open hour of K2, K4, if the open hour of K2, K4 are long partially, then Shu Chu voltage is higher, otherwise, then on the low side.When C1, C2 discharged in the discharge phase, can take form discharge discontinuous, that be interrupted, as the discharge phase of establishing C1, C2 be m second, so can be by being the s discharge process realization of second n discharge time.The voltage peak of C1, C2 should require the voltage height of output than H end, as the input of A, B end be alternating current 220V, the voltage request of output is 5V, then C1, the voltage peak that reaches when C2 is recharged can be chosen 10V.The effect of F4 is to be used for detecting whether the voltage of output is rated value, if the voltage of output has deviation, then deviation signal is fed back to CPU, and CPU revises the open hour of K2, K4 again.L1, L2 are in order to make when charging electric current more steady, and L2 plays the effect that intercepts the high-frequency harmonic that K2, K4 self produce simultaneously, and the also available resistance of L1, L2 replaces.F1 considers that the heating of K1 and K3 is provided with, if K1, K3 only open or close when the external power trough arrives, then can reduce the caloric value of K1, K3; F1 is the signal that is used for detecting trough, if do not consider the heating of K1, K3, then can save F1.
Claims (2)
1. a separation purifying voltage stabilizing IC comprises K1, K2, K3 and four gate controlled switches of K4, F1, F2, F3 and four voltage detecting circuits of F4, also comprises first order capacitor C 1 and C2, second level capacitor C 3 and central processor CPU; The input of described gate controlled switch K1, K3 and testing circuit F1 is parallel to the input that the M point connects circuit of the present invention; The input of described gate controlled switch K2, testing circuit F2 and a utmost point of capacitor C 1 are parallel to the output that the O point meets described gate controlled switch K1, another utmost point ground connection of capacitor C 1; The input of described gate controlled switch K4, testing circuit F3 and a utmost point of capacitor C 2 are parallel to the output that the P point meets described gate controlled switch K3, another utmost point ground connection of capacitor C 2; The output of described gate controlled switch K2 and K4 is parallel to the input that the N point connects inductance L 2; One utmost point of the signal input part of the output of described inductance L 2, testing circuit F4 and described second level capacitor C 3 is parallel to the output that the H point connects circuit of the present invention, another utmost point ground connection of capacitor C 3; Described gate controlled switch K1, K2, K3, K4 and testing circuit F1, F2, F3, F4 all link with described central processor CPU and controlled by it.
2. separation purifying voltage stabilizing IC as claimed in claim 1 is characterized in that: described inductance L 2 can replace with resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95102626A CN1041676C (en) | 1995-03-16 | 1995-03-16 | Separation purifying voltage stabilizing IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95102626A CN1041676C (en) | 1995-03-16 | 1995-03-16 | Separation purifying voltage stabilizing IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1115515A true CN1115515A (en) | 1996-01-24 |
| CN1041676C CN1041676C (en) | 1999-01-13 |
Family
ID=5074410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95102626A Expired - Fee Related CN1041676C (en) | 1995-03-16 | 1995-03-16 | Separation purifying voltage stabilizing IC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1041676C (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1011173B (en) * | 1988-06-28 | 1991-01-09 | 明昌连 | Gated separable power adapter |
-
1995
- 1995-03-16 CN CN95102626A patent/CN1041676C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1041676C (en) | 1999-01-13 |
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| MM4A | Cease of patent right caused by unpayment of annual fee |