CN111541390B - Multi-level inverter topology circuit - Google Patents

Multi-level inverter topology circuit Download PDF

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Publication number
CN111541390B
CN111541390B CN202010414148.5A CN202010414148A CN111541390B CN 111541390 B CN111541390 B CN 111541390B CN 202010414148 A CN202010414148 A CN 202010414148A CN 111541390 B CN111541390 B CN 111541390B
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switching unit
circuit
unit
type inverter
capacitor
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CN111541390A (en
Inventor
阿拉丁·穆斯塔法·穆罕默德·哈森
李小腾
王睿
陈文洁
杨旭
杨洋
周永兴
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State Grid Corp of China SGCC
Xian Jiaotong University
Electric Power Research Institute of State Grid Shaanxi Electric Power Co Ltd
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State Grid Corp of China SGCC
Xian Jiaotong University
Electric Power Research Institute of State Grid Shaanxi Electric Power Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a multi-level inverter topological circuit, which is formed by connecting an H-bridge topological circuit with a K-type inverter topological circuit to form a modular multi-level inverter topological circuit, wherein the H-bridge topological circuit is adopted as an auxiliary circuit, the K-type inverter topological circuit is mainly connected, the H-bridge topological circuit and the K-type inverter topological circuit are respectively connected as sub-modules, the connection structure of the circuit is simplified, meanwhile, multi-level output can be realized through the matching of the H-bridge topological circuit and a K-type inverter topological circuit switch, no additional booster circuit is needed, the output voltage can reach 3 multiplying power, cascade connection can be carried out to expand the output voltage and power, only 2 power sources and 3 switch capacitors are used in the K-type inverter topological circuit, non-interfering charge loops are respectively provided for the capacitors, and the number of active switches required for generating 15-level output voltage is reduced, the switching loss is reduced.

Description

Multi-level inverter topology circuit
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a multi-level inverter topology circuit.
Background
Recently, multilevel inverters (MLI) have attracted considerable attention in the DC-AC converter family, especially in applications in the industrial field in the high power range. MLI can significantly reduce Total Harmonic Distortion (THD) of the output voltage while also limiting electromagnetic interference (EMI), and in addition, the use of multiple output levels can also reduce voltage stress on the switches and switching losses, thus it is of great help to improve system efficiency. Multilevel power conversion is rapidly developing and widely used in the field of power engineering for applications such as medium voltage ac drives, flexible ac transmission system (FACTS) devices, and High Voltage Direct Current (HVDC) transmission systems. Based on the existing research, the more inverter output voltage levels means that the output is closer to a smooth sinusoidal waveform, the harmonic content is less, and the generation of multiple levels currently generally needs more direct-current voltage source coordination, which complicates the module topology and even introduces an unstable factor.
Disclosure of Invention
The invention aims to provide a multi-level inverter topology circuit to overcome the defects of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-level inverter topology circuit, a K-type inverter topology circuit and an H-bridge topology circuit;
the K-type inverter topology circuit comprises a fifth switch unit T5And a sixth switching unit T6Seventh switching unit T7The eighth switching unit T8And a ninth switching unit T9The tenth switching unit T10Eleventh switching unit T11And a twelfth switching unit T12And a thirteenth switching unit T13And a fourteenth switching unit T14A first capacitor C1A second capacitor C2A third capacitor C3And a first direct current power supply Vdc；
First DC power supply VdcPositive electrode, fourteenth switching unit T14One end, tenth switching unit T10One terminal and an eleventh switching unit T11One end is connected;
first direct currentPower supply VdcNegative electrode, thirteenth switching unit T13One end, seventh switch unit T7One end, eighth switch unit T8One terminal and a ninth switching unit T9One end is connected;
seventh switching unit T7Another end of (1), a sixth switching unit T6One terminal and a third capacitor C3Connecting the positive electrode;
third capacitor C3Negative electrode, twelfth switching element T12One terminal and a second capacitor C2Connecting the positive electrode; second capacitor C2Negative pole and fifth switch unit T5One end is connected;
tenth switching unit T10The other end of the ninth switch unit T9The other end and a first capacitor C1Connecting the negative electrodes;
eleventh switching unit T11The other end of the first capacitor C1Positive and eighth switch unit T8The other end, a sixth switching unit T6The other end and a fifth switching unit T5The other end is connected to form the output end of the K-type inverter topology circuit; twelfth switching unit T12The other end, a thirteenth switching unit T13The other end and a fourteenth switching unit T14The other end is connected;
the H-bridge topology circuit comprises a first switch unit T1A second switch unit T2A third switch unit T3A fourth switching unit T4And a second DC power supply Vdc；
Third switch unit T3One end, a first switch unit T1One end and an eleventh switch unit T11The other end is connected;
second DC power supply VdcPositive electrode of (1), first switch unit T1The other end and a second switch unit T2One end is connected; second DC power supply VdcNegative electrode, third switching unit T3The other end and a fourth switching unit T4One end is connected;
fourteenth switching unit T14The other end is connected with an output end A and a second switch unit T2The other end and the fourthSwitch unit T4The other end is connected with the output end B.
Furthermore, a plurality of H-bridge topology circuits are connected with a K-type inverter topology circuit after being cascaded.
Further, a plurality of H-bridge topology circuits are cascaded: third switching unit T of one of the H-bridge topology circuits3Fourth switching unit T with one end connected with another H-bridge topological circuit4The other end is connected; wherein the third switching unit T of one H-bridge topology circuit at one end of the H-bridge topology circuit cascade circuit3One end and an eleventh switch unit T11The other end is connected; the fourth switching unit T of the H-bridge topology circuit at the other end of the H-bridge topology circuit cascade circuit4The other end is connected with the output end B.
Furthermore, a plurality of K-type inverter topology circuits are connected with an H-bridge topology circuit after being cascaded.
Further, a plurality of K-type inverter topology circuits are cascaded: fourteenth switching unit T of one of the K-type inverter topology circuits14The other end of the eleventh switching unit T is connected with another K-type inverter topology circuit11The other end; the fourteenth switching unit T of one K-type inverter topology circuit at one end in the K-type inverter topology circuit cascade circuit14The other end of the eleventh switch unit T is connected with the output end A, and the eleventh switch unit T of the K-type inverter topology circuit at the other end in the K-type inverter topology circuit cascade circuit11The other end is connected with a third switch unit T3And the other end.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to a multi-level inverter topological circuit, which is formed by connecting an H-bridge topological circuit with a K-type inverter topological circuit to form a modular multi-level inverter topological circuit, wherein the H-bridge topological circuit is used as an auxiliary circuit, the K-type inverter topological circuit is used as a main circuit, the H-bridge topological circuit and the K-type inverter topological circuit are respectively connected as sub-modules, the connection structure of the circuit is simplified, meanwhile, multi-level output can be realized through the matching of the H-bridge topological circuit and a K-type inverter topological circuit switch, no additional booster circuit is needed, the output voltage can reach 3 multiplying powers, and the multi-level inverter topological circuit can be cascaded to expand the output voltage and power, only 2 power sources and 3 switch capacitors are used in the K-type inverter topological circuit, non-interfering charging loops are respectively provided for the capacitors, and the number of active switches required for generating 15-level output voltage is reduced, the switching loss is reduced.
Drawings
FIG. 1 is a schematic circuit topology according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of different switch states of an inverter topology, and FIG. 2(i) is a circuit diagram of a circuit forming 0.5VdcAn output path; FIG. 2(ii) shows the formation of-0.5VdcAn output path; FIG. 2(iii) shows the formation of 1VdcAn output path; FIG. 2(iv) is a diagram of formation of-VdcAn output path; FIG. 2(V) is a graph showing 1.5VdcAn output path; FIG. 2(vi) shows the formation of-1.5VdcAn output path; FIG. 2(vii) is a schematic view showing 2V formationdcAn output path; FIG. 2(viii) is a diagram showing the formation of-2VdcAn output path; FIG. 2(ix) shows 2.5V formationdcAn output path; FIG. 2(x) is a graph showing formation of-2.5VdcAn output path; FIG. 2(xi) is a diagram of forming 3VdcAn output path; FIG. 2(xii) is a diagram of formation of-3VdcAn output path; FIG. 2(xiii) is for forming 3.5VdcAn output path; FIG. 2(xiv) is a diagram forming-3.5VdcAnd (4) an output channel.
Fig. 3 is a circuit diagram of a cascade circuit in an embodiment of the present invention, fig. 3(a) is a circuit diagram of a cascade circuit in an H-bridge topology, and fig. 3(b) is a circuit diagram of a cascade circuit in a K-type inverter topology.
Fig. 4 shows the 15-level output voltage and load current in the simulation environment of the embodiment of the present invention.
Fig. 5 shows output voltages of H-bridge and K-type inverter sub-modules in a simulation environment according to an embodiment of the present invention.
FIG. 6 shows the voltage variation of the capacitor according to the embodiment of the present invention.
Fig. 7 is a graph of harmonic components of a single stage output voltage in an embodiment of the invention.
Fig. 8 shows the output voltage and the load current of the cascade system in an embodiment of the invention.
Fig. 9 shows the output voltages of different sub-modules in the cascade system according to an embodiment of the present invention.
FIG. 10 shows harmonic components of the output voltage of the cascade system in accordance with an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1, a multi-level inverter topology circuit includes 2 power supplies and 14 power switches and 3 symmetrical chargeable capacitors; the 2 power supplies comprise a first DC power supply VdcAnd a second DC power supply Vdc(ii) a The 14 power switches include a first switching unit T1A second switch unit T2A third switch unit T3A fourth switching unit T4A fifth switching unit T5And a sixth switching unit T6Seventh switching unit T7The eighth switching unit T8And a ninth switching unit T9The tenth switching unit T10Eleventh switching unit T11And a twelfth switching unit T12And a thirteenth switching unit T13And a fourteenth switching unit T14(ii) a The 3 symmetrical chargeable capacitors comprise a first capacitor C1A second capacitor C2And a third capacitance C3；
First DC power supply VdcPositive electrode, fourteenth switching unit T14One end, tenth switching unit T10One terminal and an eleventh switching unit T11One end is connected;
first DC power supply VdcNegative electrode, thirteenth switching unit T13One end, seventh switch unit T7One end, eighth switch unit T8One terminal and a ninth switching unit T9One end is connected;
seventh switching unit T7Another end of (1), a sixth switching unit T6One terminal and a third capacitor C3Connecting the positive electrode;
third capacitor C3Negative electrode, twelfth switching element T12One terminal and a second capacitor C2Connecting the positive electrode; second capacitor C2Negative pole and fifth switch unit T5One end is connected;
tenth switching unit T10The other end of the ninth switch unit T9The other end and a first capacitor C1Connecting the negative electrodes;
eleventh switching unit T11The other end of the first capacitor C1Positive and eighth switch unit T8The other end, a sixth switching unit T6The other end, a fifth switch unit T5The other end, a third switching unit T3One terminal and a first switching unit T1One end is connected;
second DC power supply VdcPositive electrode of (1), first switch unit T1The other end and a second switch unit T2One end is connected; second DC power supply VdcNegative electrode, third switching unit T3The other end and a fourth switching unit T4One end is connected;
twelfth switching unit T12The other end, a thirteenth switching unit T13The other end and a fourteenth switching unit T14The other end is connected with the output end A; second switch unit T2The other end and a fourth switching unit T4The other end is connected with the output end B.
Example (b): as shown in fig. 1, 11 circuit nodes are provided in total;
the first switch unit T1The first end is connected with circuit node (r), the second end is connected with circuit node (r);
the second switch unit T2First terminal connected to circuit node R, second terminal connected to circuit node
Figure BDA0002494412220000051
Connecting;
the third switching unit T3The first end is connected with a circuit node ninthly, and the second end is connected with a circuit node ((r));
the fourth switching unit T4First terminal and circuit node
Figure BDA0002494412220000052
The second end is connected with a circuit node;
the fifth switching unit T5First terminal and circuit nodeSeventhly, the second end of the circuit is connected with a circuit node;
the sixth switching unit T6The first end is connected with the circuit node r, and the second end is connected with the circuit node r;
the seventh switching unit T7The first end is connected with the circuit node III, and the second end is connected with the circuit node IV;
the eighth switching unit T8The first end is connected with a circuit node III, and the second end is connected with a circuit node III;
the ninth switching unit T9The first end is connected with the circuit node sixth, and the second end is connected with the circuit node third;
the tenth switching unit T10The first end is connected with a circuit node II, and the second end is connected with a circuit node II;
the eleventh switching unit T11The first end is connected with a circuit node II, and the second end is connected with a circuit node II;
the twelfth switching unit T12The first end is connected with the circuit node I, and the second end is connected with the circuit node II;
the thirteenth switching unit T13The first end is connected with the circuit node I, and the second end is connected with the circuit node III;
the fourteenth switching unit T14The first end is connected with the circuit node II, and the second end is connected with the circuit node I;
the first capacitor C1The first end is connected with a circuit node (c), and the second end is connected with a circuit node (b);
the second capacitor C2The first end is connected with a circuit node and the second end is connected with a circuit node;
the third capacitor C3The first end is connected with the circuit node (fifth), and the second end is connected with the circuit node (fourth);
wherein the circuit node is
Figure BDA0002494412220000061
Is a topological output node, and the nodes are respectively the positive and negative poles of the power supply of the K-type inverterNode (r) is the positive and negative poles of the power supply of the H bridge unit, and node (r) is the connection point of the H bridge topology circuit and the K-type module topology circuit.
By changing the switching state, the present multilevel inverter circuit is able to generate 14 different switching combinations, each combination being an output voltage level, as shown in fig. 2, the switching state analysis is as follows:
in fig. 2(i), output terminal a and output terminal B are via switching unit T13、T8、T1、T4And an H-bridge inverter power supply forms a path, and the output voltage of the inverter is V at the momentAB＝0.5Vdc。
In fig. 2(ii), the output terminal a and the output terminal B are via the switching unit T13、T8、T3、T2And an H-bridge inverter power supply forms a path, and the output voltage of the inverter is V at the momentAB＝-0.5Vdc。
In fig. 2(iii), output a and output B are via a switching unit T14、T8、T1、T2And a K-type inverter power supply forms a path, and the output voltage of the inverter is V at the momentAB＝Vdc。
In fig. 2(iv), output a and output B are via a switching unit T13、T11、T3、T4And a K-type inverter power supply forms a path, and the output voltage of the inverter is V at the momentAB＝-Vdc。
In fig. 2(v), output a and output B are via a switching unit T14、T8、T1、T4And all the direct current power supplies form a path, and the output voltage of the inverter is V at the momentAB＝1.5Vdc。
In fig. 2(vi), output terminal a and output terminal B are via switching unit T13、T11、T3、T2And all the direct current power supplies form a path, and the output voltage of the inverter is V at the momentAB＝-1.5Vdc。
In fig. 2(vii), output terminal a and output terminal B are via switching unit T13、T7、T5、T1、T2And a capacitor C2、C3A path is formed when the output voltage of the inverter is VAB＝2Vdc。
In fig. 2(viii), output terminal a and output terminal B are via switching unit T13、T10、T3、T4And a capacitor C1And a K-type inverter power supply forming a path when the output voltage of the inverter is VAB＝-2Vdc。
In fig. 2(ix), the output terminal a and the output terminal B are via the switching unit T13、T7、T5、T1、T4And a capacitor C2、C3And an H-bridge inverter power supply forming a path when the output voltage of the inverter is VAB＝2.5Vdc。
In fig. 2(x), output terminal a and output terminal B are via switching unit T13、T10、T3、T2And a capacitor C1And all the direct current power supplies form a path, and the output voltage of the inverter is V at the timeAB＝-2.5Vdc。
In fig. 2(xi), the output terminal a and the output terminal B are via the switching unit T14、T7、T5、T1、T2And a capacitor C3、C2And a K-type inverter power supply forming a path when the output voltage of the inverter is VAB＝3Vdc。
In FIG. 2(xii), output terminal A and output terminal B are via a switching unit T12、T7、T10、T3、T4And a capacitor C3、C1And a K-type inverter power supply forming a path when the output voltage of the inverter is VAB＝-3Vdc。
In fig. 2(xiii), the output terminal a and the output terminal B are via the switching unit T14、T7、T5、T1、T4And a capacitor C2、C3And all the direct current power supplies form a path, and the output voltage of the inverter is V at the timeAB＝3.5Vdc。
In FIG. 2(xi)v) output A and output B are connected via a switching unit T12、T7、T10、T3、T2And a capacitor C3、C1And all the direct current power supplies form a path, and the output voltage of the inverter is V at the timeAB＝-3.5Vdc。
By a fifth switching unit T5And a sixth switching unit T6Seventh switching unit T7The eighth switching unit T8And a ninth switching unit T9The tenth switching unit T10Eleventh switching unit T11And a twelfth switching unit T12And a thirteenth switching unit T13And a fourteenth switching unit T14A first capacitor C1A second capacitor C2A third capacitor C3And a first direct current power supply VdcThe K-type inverter topology circuit provides independent charging loops for the three capacitors, so that mutual charging cannot generate interference, and other auxiliary circuits are not needed. In addition, when the switch state is changed, only 12 power switches of 14 power switches in the multi-level inverter circuit actually participate in the generation of the multi-level output voltage, and the sixth switch unit T6And a ninth switching unit T9Only during the capacitor charging phase.
As an expansion application of the topology, the grade of output voltage can be improved after more units are cascaded, and the output power and the load carrying capacity are improved.
The embodiment of the invention relates to a master-slave hybrid 15-level-three-switch capacitor-3-time voltage rate cascaded multi-level inverter circuit topology which comprises two basic modules, namely an H-bridge topology circuit and a K-type inverter topology circuit. Fig. 3(a) shows the case of the cascade connection based on the H-bridge topology circuit, and fig. 3(b) shows the case of the cascade connection based on the K-type inverter.
As shown in fig. 4-10, a cascaded multilevel inverter circuit for a master-slave hybrid 15-level-three-switch capacitor-3 voltage-multiplying ratio is built in MATLAB-SIMULINK and used for supplying power to an R-L load. Simulation parameter set to RL＝100Ω,XL＝1.57Ω,V dc100v, and 50 Hz. By artificial observationThe output voltage of the submodule of the novel inverter, the integral multi-level output of the inverter and the system output under the cascade condition (two K-type inverter units and an H-bridge are cascaded) are observed. The voltage output of 15 levels can be reliably realized. The capacitor has the advantages of correct charging and discharging sequence, excellent response, small capacitor voltage ripple amount and close to constant. A very smooth sinusoidal output waveform can be obtained by cascading, further reducing the single stage output THD from 5.50% to 1.24%.

Claims (5)

1. A multi-level inverter topology circuit is characterized by comprising a K-type inverter topology circuit and an H-bridge topology circuit;
the K-type inverter topology circuit comprises a fifth switch unit T5And a sixth switching unit T6Seventh switching unit T7The eighth switching unit T8And a ninth switching unit T9The tenth switching unit T10Eleventh switching unit T11And a twelfth switching unit T12And a thirteenth switching unit T13And a fourteenth switching unit T14A first capacitor C1A second capacitor C2A third capacitor C3And a first direct current power supply Vdc；
First DC power supply VdcPositive electrode, fourteenth switching unit T14One end, tenth switching unit T10One terminal and an eleventh switching unit T11One end is connected;
first DC power supply VdcNegative electrode, thirteenth switching unit T13One end, seventh switch unit T7One end, eighth switch unit T8One terminal and a ninth switching unit T9One end is connected;
seventh switching unit T7Another end of (1), a sixth switching unit T6One terminal and a third capacitor C3Connecting the positive electrode;
third capacitor C3Negative electrode, twelfth switching element T12One terminal and a second capacitor C2Connecting the positive electrode; second capacitor C2Negative pole and fifth switch unit T5One end is connected;
tenth switching unit T10The other end of the ninth switch unit T9The other end and a first capacitor C1Connecting the negative electrodes;
eleventh switching unit T11The other end of the first capacitor C1Positive and eighth switch unit T8The other end, a sixth switching unit T6The other end and a fifth switching unit T5The other end is connected to form the output end of the K-type inverter topology circuit; twelfth switching unit T12The other end, a thirteenth switching unit T13The other end and a fourteenth switching unit T14The other end is connected;
the H-bridge topology circuit comprises a first switch unit T1A second switch unit T2A third switch unit T3A fourth switching unit T4And a second DC power supply Vdc；
Third switch unit T3One end, a first switch unit T1One end and an eleventh switch unit T11The other end is connected;
second DC power supply VdcPositive electrode of (1), first switch unit T1The other end and a second switch unit T2One end is connected; second DC power supply VdcNegative electrode, third switching unit T3The other end and a fourth switching unit T4One end is connected;
fourteenth switching unit T14The other end is connected with an output end A and a second switch unit T2The other end and a fourth switching unit T4The other end is connected with the output end B.
2. The multi-level inverter topology circuit according to claim 1, wherein a plurality of H-bridge topology circuits are cascaded and then connected to one of the K-type inverter topology circuits.
3. The multi-level inverter topology circuit according to claim 2, wherein a plurality of said H-bridge topology circuits are cascaded: third switching unit T of one of the H-bridge topology circuits3Fourth switch of one end and another H-bridge topological circuitUnit T4The other end is connected; wherein the third switching unit T of one end of the H-bridge topology circuit in the H-bridge topology circuit cascade circuit3One end and an eleventh switch unit T11The other end is connected; a fourth switching unit T of the H-bridge topology circuit at the other end of the H-bridge topology circuit cascade circuit4The other end is connected with the output end B.
4. The multilevel inverter topology circuit according to claim 1, wherein a plurality of the K-type inverter topology circuits are connected to one of the H-bridge topology circuits after being cascaded.
5. The multi-level inverter topology circuit according to claim 4, wherein a plurality of said K-type inverter topology circuits are cascaded: a fourteenth switching unit T of one of said K-type inverter topology circuits14The other end of the eleventh switching unit T is connected with another K-type inverter topology circuit11The other end; a fourteenth switching unit T of one end of the K-type inverter topology circuit in the K-type inverter topology circuit cascade circuit14The other end of the K-type inverter topology circuit cascade circuit is connected with an output end A, and an eleventh switch unit T of the K-type inverter topology circuit at the other end of the K-type inverter topology circuit cascade circuit11The other end is connected with a third switch unit T3One end of the tube.
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