CN111538473B

CN111538473B - Posit floating point number processor

Info

Publication number: CN111538473B
Application number: CN202010348464.7A
Authority: CN
Inventors: 梁峰; 赵科芃; 吴斌; 张国和; 孙齐伟
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2020-04-27
Filing date: 2020-04-27
Publication date: 2023-05-30
Anticipated expiration: 2040-04-27
Also published as: CN111538473A

Abstract

The application provides a Posit floating point number processor, and relates to the technical field of computers. The floating point number processor meeting the Posit standard is provided for the user. The Posit floating point number processor includes: a decoding circuit, an arithmetic circuit, and an encoding circuit; the decoding circuit is used for acquiring a plurality of target Posit floating points participating in operation according to a calculation instruction of the CPU, and converting the plurality of target Posit floating points into intermediate data in the form of complementary codes corresponding to the target Posit floating points; the intermediate data includes a plurality of fields: a sign field, a real exponent field, a first mantissa field, and a guard bit field; the operation circuit is used for carrying out operation on the received plurality of intermediate data output by the decoding circuit according to the calculation instruction to obtain an operation result represented by the intermediate data in the form of complement; the encoding circuit is used for converting the operation result into the Posit floating point number with the specified format according to the specified format in the calculation instruction.

Description

Posit floating point number processor

Technical Field

The application relates to the technical field of computers, in particular to a Posit floating point number processor.

Background

Floating point number is a data representation method commonly used in the scientific computing field and the high-performance computing field, and particularly, in the occasion with higher precision requirement on the computing result, a large amount of floating point number is used for data processing, such as the fields of automatic driving, aerospace and mechanical computing.

Compared with the floating point number of the IEEE 754 standard, the floating point number of the Posit standard has higher flexibility, the sampling distribution of the Posit floating point number on a real number is related to a sigmoid function, and the sigmoid function is an activation function commonly used in machine learning, so that the Posit floating point number is used in machine learning, and the efficiency of data processing of a computer is higher.

However, the floating point processors of the commercial computers are mostly floating point processors based on the IEEE 754 standard, and do not completely meet the Posit standard.

Disclosure of Invention

In order to solve the above problems, embodiments of the present application provide a Posit floating-point processor, which provides a floating-point processor satisfying Posit standards for users.

The Posit floating point number processor provided by the embodiment of the application comprises: a decoding circuit, an arithmetic circuit, and an encoding circuit;

the decoding circuit is used for acquiring a plurality of target Posit floating points participating in operation according to a calculation instruction of the CPU, and converting the plurality of target Posit floating points into intermediate data in the form of complementary codes corresponding to the target Posit floating points; the intermediate data includes a plurality of fields: a sign field, a real exponent field, a first mantissa field, and a guard bit field;

The operation circuit is used for carrying out operation on the received plurality of intermediate data output by the decoding circuit according to the calculation instruction to obtain an operation result represented by the intermediate data in the form of complement;

the encoding circuit is used for converting the operation result into the Posit floating point number with the specified format according to the specified format in the calculation instruction.

Optionally, the decoding circuit includes: the first exclusive-or device, the second exclusive-or device, the reverse leading zero detection circuit device, the first shift circuit device, the first splicing circuit device, the first extraction circuit device and the following modules:

the region real symbol determining module is used for carrying out exclusive OR operation on the highest bit of the target Posit floating point number and the next highest bit of the target Posit floating point number through the first exclusive OR device to obtain a real symbol of a region field of the target Posit floating point number;

the region field unification module is used for removing the highest bit and the next highest bit of the target Posit floating point number for the first time, removing the highest bit and the lowest bit of the target Posit floating point number for the second time, and performing exclusive OR operation on the result of the first time and the result of the second time through the second exclusive OR device to obtain a region unification field;

The region value calculation module is used for detecting the region unified field through the reverse leading zero detection circuit device and obtaining a value field of the region field according to the output of the reverse leading zero detection circuit device;

the extraction module is used for shifting out the highest three bits of the target Posit floating point number through the first shift circuit device, and shifting left the remaining fields of the target Posit floating point number after shifting out the highest three bits by a specified bit number; the specified bit number is obtained according to the output of the reverse leading zero detection circuit device;

the extraction module is further configured to extract, from the target Posit floating point number after the left shift, an exponent field and a second mantissa field of the target Posit floating point number according to a bit width of the exponent field of the target Posit floating point number;

the real index determining module is used for inverting the index field when the target Posit floating point number is negative, and then splicing the index field or the inverted index field with the value field of the region field through the first splicing circuit device to obtain and output a real index field in intermediate data corresponding to the target Posit floating point number;

The first mantissa field determining module is used for carrying out zero padding on the low order bits of the second mantissa field according to the maximum bit width of the first mantissa field to obtain the first mantissa field and outputting the first mantissa field; the maximum bit width of the first mantissa field is obtained by subtracting the bit width of the sign bit of the target Posit floating point number, the bit width of the exponent field and the minimum bit width of the region field from the total bit width of the target Posit floating point number;

the protection bit output module is used for taking a field with the value of 0 of each bit as the protection bit field and outputting the protection bit field; the guard bit field has a bit width of 3.

Optionally, the intermediate data further includes an infinity field and a zero value field; the decoding circuit further includes: an infinity number determining module and a zero value judging module;

the infinity determining module is configured to set an infinity field of intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is infinity;

and the zero value judging module is used for setting the zero value field of the intermediate data corresponding to the target Posit floating point number to be true when the target Posit floating point number is zero.

Optionally, the intermediate data further includes a symbol field; the decoding circuit further includes: a symbol judgment module;

the symbol judgment module is used for determining the symbol of the target Posit floating point number according to the highest bit of the target Posit floating point number, taking the symbol of the target Posit floating point number as the symbol of the intermediate data corresponding to the target Posit floating point number, and outputting the symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

Optionally, the encoding circuit includes: the second extraction circuit device, the second shift circuit device, the second splice circuit device, and the following modules:

the exponent field coding module is configured to extract, in the real exponent field of the operation result, a field having the same bit width as the exponent coding field according to the sequence from the lowest bit to the highest bit, and obtain the exponent coding field according to the field having the same bit width as the exponent coding field, and use the real exponent field after extracting the field having the same bit width as the exponent coding field as the value corresponding to the region coding field;

The region format determining module determines the filling format of the region coding field according to the sign field of the operation result and the sign of the region coding field;

the region field coding module is used for sequentially splicing the filling format, the exponent coding field, the first mantissa field of the operation result and the protection bit field of the operation result by using the second splicing circuit device to obtain a spliced field, and arithmetically shifting the spliced field to the right by using the second shifting circuit device according to the numerical value corresponding to the region coding field to obtain the region coding field;

and the floating point number result determining module is used for rounding the spliced field after rightward shift by utilizing the protection bit field, and adding a sign field of the operation result to the most significant bit of the spliced field after rounding operation to obtain the Posit floating point number in the specified format.

Optionally, the encoding circuit further includes an output module:

the output module is used for directly outputting the Posit floating point number in the appointed format as an infinite number coding field for expressing infinite number when the infinite number segment of the intermediate data is true;

The output module is further configured to directly output the Posit floating point number in the specified format as an infinite number encoding field representing a zero value when the zero value field of the intermediate data is true.

Optionally, the reverse leading zero detection circuit device comprises an or device, a first inverting device and a second inverting device;

the reverse leading zero detection circuit device is configured to perform an inverse operation on the 0 th bit of the input field with the bit width of 2 by using the first inverse device, and then perform an or operation on the 1 st bit of the input field with the bit width of 2 and the multiple inverse results by using the or device, so as to obtain the 0 th bit of the multiple output fields; the input field with the bit width of 2 is obtained by processing the region unified field through a dichotomy;

the reverse leading zero detection circuit device is further configured to perform an or operation on the 0 th bit of the input fields with the bit width of 2 and the 1 st bit of the input fields with the bit width of 2 by using the or device, so as to obtain the 1 st bit of the output fields;

and the reverse leading zero detection circuit device is also used for splicing the plurality of output fields to obtain the value code of the region unified field.

Optionally, the region value calculation module includes:

a region value calculation sub-module, configured to, when the real symbol of the region field is positive, invert the inversion code output by the reverse leading zero detection circuit device, and then add the real symbol of the region field to the highest bit of the inversion code output by the inverted leading zero detection circuit device, so as to obtain the value field of the region field;

and the region value calculation sub-module is further used for adding the real symbol of the region field to the highest bit of the code reversal output by the reverse leading zero detection circuit device when the real symbol of the region field is negative, so as to obtain the value field of the region field.

Optionally, the floating point number result determining module includes:

a protection bit sub-module, configured to, when each bit of the spliced field after rightward shifting is 0, add 1 to a least significant bit of the spliced field after rightward shifting, and when all values of the spliced field after rightward shifting are 1, keep the spliced field after rightward shifting unchanged;

the protection bit sub-module is further configured to add 1 to a least significant bit of the spliced field after rightward shifting or add 1 to a least significant bit of the spliced field after rightward shifting when the value of any two bits in the spliced field after rightward shifting is different, and add 1 to a least significant bit of the spliced field after rightward shifting when the value of the protection bit is equal to 4 and the least significant bit of the spliced field after rightward shifting is 1 when the value of the protection bit is greater than 4.

Optionally, the exponent field encoding module is further configured to invert the field with the same bit width as the exponent encoding field when the sign field of the intermediate data represents a negative number, to obtain the exponent encoding field;

and when the sign field of the intermediate data represents a positive number, taking the field with the same bit width as that of the exponent coding field as the exponent coding field.

According to the Posite floating point number processor provided by the embodiment of the application, the decoding circuit is utilized to convert the Posite floating point number obtained according to the calculation instruction into the intermediate data in the complement form, and the intermediate data comprises the infinity field and the zero value field which represent the special Posite floating point number, so that the arithmetic circuit and the coding circuit can directly output the infinity coding field or the zero value coding field which represent the special Posite floating point number when the calculation parameters or the calculation results are the special Posite floating point number, and the output efficiency of the Posite floating point number processor is improved.

The arithmetic circuit can directly use the real exponent field and the first mantissa field in the intermediate data to carry out operation, and after extracting and splicing the constituent fields of the Posit floating point number, the real exponent field and the first mantissa field can be obtained, the real exponent field and the first mantissa field are fixed point numbers in the form of complement, the operation result represented by the intermediate data obtained after a plurality of intermediate data are operated according to the calculation instruction is still fixed point numbers in the form of complement, and the encoding circuit only needs to convert the fixed point numbers in the form of complement into the encoding format of the Posit floating point number according to the format appointed by the CPU processor, so that the encoding of the Posit floating point number can be completed. The process does not need the process of interconversion from the original code to the complement code for multiple times, and simplifies the processing operation of Posit floating point numbers.

The symbol field in the intermediate data can be directly used in an operation circuit, the symbol for obtaining the operation result can also be used in an encoding circuit to obtain a region encoding field, and the region encoding field can be directly used as the highest bit of the Posit floating point number for finally representing the operation result, and when the complement is not needed to be considered, the difference of the encoding forms of the positive and negative Posit floating points is reduced, so that the processing operation of the Posit floating point number is simplified.

The protection bit field in the intermediate data is used in the operation circuit to round the operation result, and can also be used in the coding circuit to round the coding process, so that the operation of the Posit floating point number processor accords with the specification of the Posit floating point number.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a decoding circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a reverse leading zero detection circuit device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a Posit floating point number processor according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an encoding circuit according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Posit floating point number is a new type of floating point number standard (also called the Unum floating point standard, posit is the third edition of the Unum standard) proposed by the professor John L.Gustafson at the national university of Singapore, which defines data formats and arithmetic rules that differ from IEEE 754. Compared with IEEE 754, posit has the advantages of flexible data format, large dynamic range, few abnormal formats, high precision and the like. The advantages specifically are not limited to the following list:

the sampling distribution of Posit floating point numbers over real numbers is related to a sigmoid function, which is an activation function commonly used in currently popular machine learning. Through practice, the Posit floating point number is very convenient in fitting a sigmoid function, so that the Posit floating point number is applied to the field of machine learning, and related hardware design can be simplified.

Compared with the IEEE754 floating point number, the method has the advantages that when the total bit width of the floating point number is agreed, the bit width format specified in IEEE754-2008, namely, four bit widths of 16-bit half precision, 32-bit single precision, 64-bit double precision and 128-bit four precision, are required to be met. Under the condition that the Posit floating point number meets the application requirement, the bit width of any format can be selected, and not only can 32 bits be selected, but also 31 bits, 33 bits, 30 bits and the like can be selected, so that the flexibility of the Posit floating point number is reflected. Compared to IEEE754 floating-point numbers, which specify an unconventional number with a hidden bit of 0 in order to utilize more encoding space, the hidden bit of Posit floating-point numbers is always 1, reducing hardware complexity.

In the prior art, the processing of Posit floating point numbers is still in a theoretical research stage, and no Posit processor capable of being put into commercial application exists. In addition, the current research direction of the processing method of the Posit floating point number is that the decoding circuit is utilized to convert the Posit floating point number into an original code, the original code is input into the operation circuit, the operation circuit is convenient for operation, the original code is converted into a complementary code, the operation result of the complementary code is obtained, then the operation result of the original code is converted into the operation result of the original code, the operation result of the original code is input into the encoding circuit, and finally the operation result of the original code is converted into the Posit floating point number by the encoding circuit. The whole processing process needs to repeatedly perform original code to complement code and conversion from complement code to original code, and has complex logic, so that a large number of extra operations are caused, and the whole Posit floating point number processing circuit has large area.

In view of the above problems, an embodiment of the present application provides a Posit floating point processor, which is configured to decode a Posit floating point into intermediate data in a complement form, perform an operation with the intermediate data, and encode an operation result to obtain an operation result of the Posit floating point. The Posite floating point number processor provided by the embodiment of the application can decode the Posite floating point number into intermediate data capable of directly participating in operation, and solves the defect that the operation can only be performed by converting the Posite floating point number into binary code with the value, and the defect that a large amount of conversion calculation from original code to complement code and from complement code to original code is required in the whole processing process of the Posite floating point number in the prior art.

Floating point numbers are scientific counts used in computer technology to approximate any real number. In real number M x 2 ^e For example, M is mantissa, 2 is radix, and e is exponent. The data participating in the operation in the computer is represented by binary system, so that the data is IEEE 754 floating point number or Posit floating point numberThe cardinality is 2.

After the Posit floating point number is contracted for the total bit width, the bit width of the exponent is also contracted. In general, for a Posite floating point number whose total bit width is 32 bits, a bit width of 2-4 bits is usually agreed as the exponent bit width of the Posite floating point number, and for a Posite floating point number whose total bit width is 8 bits, a bit width of 1-2 bits is usually agreed as the bit width of the exponent field of the Posite floating point number. The Posit floating point number standard, including the exponent field, specifies that the Posit floating point number has the following fields:

And (3) a step of: a symbol field. The sign field is typically the most significant bit of a Posit floating point number.

2. The region field, located after the symbol field, is composed of a series of consecutive 1 s from the most significant bit to the next least significant bit and 0 s from the least significant bit, the 0 s from the least significant bit being the flip bit, or a series of consecutive 0 s from the most significant bit to the next less significant bit and 1 s from the most significant bit. When the region field is positive, the number of continuous 1 values of the region field is reduced by 1, and when the continuous region field is negative, the number of 0 values of the region field is negative. The width of the region field may be arbitrary. For example: when the region field is 1110, the value is 3-1=2; when the region field is 0001, it takes a value of-3.

3. And an exponent field, wherein if the region field does not use up the total bit width which is agreed in advance, the exponent field is immediately followed by the region field, and the bit exponent field is the bit width which is agreed in advance. The exponent field is an unsigned integer that must have a value greater than zero.

4. And if the exponent field and the region field do not use up the total bit width agreed in advance, the remaining total bit width is the bit width of the mantissa field. It is understood that, in decimal, since the mantissa is a fraction of 1.0 or more and less than 10, the integer part thereof takes any one integer of 1 to 9. In binary, the integer portion of the mantissa may only be 1, and to reduce unnecessary encoding, the Posit floating point standard uses the integer bits as hidden bits, and records only the decimal bits in the mantissa field of the Posit floating point. For example: if the mantissa field is 1001, then it is 11001 plus a hidden bit, and the corresponding decimal value is 1×2 ⁰ +1×2 ^-1 +0×2 ^-2 +0×2 ^-3 +1×2 ^-4 =1.5625. In the Posit floating point standard, the concept of used for numerically unifying the region field and the exponent field is also defined. The value of used is related to the bit width of the exponent field of the pre-agreed Posit floating point number, and is also fixed for any fixed format Posit floating point number. Assuming that the bit width of the exponent field is es, the value of used is

The method comprises the steps of carrying out a first treatment on the surface of the For example, when es=1, the element is->

The method comprises the steps of carrying out a first treatment on the surface of the es=2>

. Assuming that the sign of a Posit floating point number is s, the value of region is r, the value of exponent is e, and the mantissa value containing hidden bits is m, then the decimal real number corresponding to the Posit floating point number is:

(-1) ^s ×useed ^r ×2 ^e ×m

in the related research of Posite floating point numbers, posite floating point numbers are converted into original codes, namely Posite floating point numbers with negative signs are converted into absolute values, and the absolute values are positive numbers corresponding to the Posite floating point numbers with the negative signs, and sign bits representing the negative signs are added. Because the computer adopts the complement to operate, the arithmetic circuit needs to convert the mantissa part of the positive number corresponding to the Posit floating point number with the negative sign into the complement during operation; in the encoding process, it is again necessary to convert the complement code into the original code. It can be seen that the whole processor for Posit floating point number requires a plurality of circuits for performing the conversion from original code to complement code, which results in larger area and larger heat generation of the circuits for processing Posit floating point number.

The embodiment of the application creates a decoding circuit of a complementary code type, decodes the Posit floating point number into intermediate data which can directly participate in operation by the created decoding circuit, then uses the operation circuit to directly operate by the intermediate data to obtain an operation result represented by the intermediate data, and finally uses the created complementary code type encoding circuit to encode the operation result into the Posit floating point number. The whole processing process (decoding, operation and encoding) of Posit floating point numbers is carried out by complementary codes, a large amount of complementary code original code conversion is avoided, and power consumption is reduced.

The circuits and modules for processing the Posit floating point number are integrated into an open source RISC-V (open source instruction set architecture based on a reduced instruction set principle) processor RocketChip (an open source integrated chip generator developed based on an open source hardware construction language), so that the Posit floating point number processor provided by the application is formed, all floating point instructions can be executed, and corresponding functions can be completed correctly.

Referring to fig. 1, fig. 1 is a schematic diagram of a decoding circuit according to an embodiment of the present application. First, a decoding circuit of the Posit floating-point number processor will be described. The decoding circuit includes: an infinity determining module 101, a zero value judging module 102, a sign judging module 103, a region real sign determining module 104, a region field unifying module 105, a region value calculating module 106, an extracting module 107, a real exponent determining module 108, a first mantissa field determining module 109, and a guard bit outputting module 110.

compared with the prior art that before the Posit floating point number is calculated, whether the Posit floating point number is subjected to complementary conversion is judged by judging the sign of the Posit floating point number, the sign field in the embodiment of the application can directly participate in operation, and logic judgment of the Posit floating point number before operation and after operation is completed is reduced.

The target Posit floating point number is the Posit floating point number to be decoded, which is obtained by the decoding circuit according to the calculation instruction. Because the target Posit floating point number participates in the operation, the number of the target Posit floating point number is two or more than two, and the decoding circuit can decode a plurality of target Posit floating point numbers simultaneously or sequentially.

The intermediate data set in the embodiment of the present application is in a format of fixed point number, and specifically includes: an infinity field, a zero value field, a sign field, a true exponent field, a first mantissa field, and a protection bit field.

To distinguish between the mantissa fields of the intermediate data and the target Posit floating point number, the mantissa field in the intermediate data is represented by a first mantissa field and the mantissa field of the target Posit floating point number is represented by a second mantissa field.

There are only two special encodings in Posit floating point numbers: the real number 0 is represented by a code in which all bits are 0, the highest bit is 1, and the remaining bits are 0, representing an infinite number. Therefore, the decoding circuit is provided with the infinity determining module and the zero value judging module so as to mark the target Posit floating point number of the special codes, so that the operation circuit can directly output the operation result after the operation of the plurality of target Posit floating points of the special codes when the target Posit floating point number of the special codes is identified according to the mark, and further, the encoding circuit can directly output the codes representing the infinity and the codes representing zero when the operation result is intermediate data representing the special codes. According to the analysis, the Posit floating point number processor provided by the application processes the specially encoded target Posit floating point number more quickly.

Assuming that the specified format is Posit <8,1>, then the code for infinity is 10000000 and the code for zero is 00000000.

The decoding circuit further includes: an infinity determination module 101 and a zero value judgment module 102;

the intermediate data also includes an infinity field and a zero value field; the decoding circuit further includes: an infinity number determining module and a zero value judging module;

the infinity determining module 101 is configured to set an infinity field of intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is infinity;

the zero value judging module 102 is configured to set a zero value field of intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is zero.

And when the infinity number determining module judges that the target Posit floating point number is not infinity number, setting a zero value field and an infinity number field as false. The infinity determining module 101, the zero value judging module 102 and the sign judging module 103 are connected in parallel, and the decoding circuit decodes the target Posit floating point number to obtain a sign field, a true exponent field, a first mantissa field and a protection bit field no matter whether the infinity field and the zero value field are true or not. The infinity field and the zero value field are used for ensuring that when the operation result caused by the fact that the target Posit floating point number is zero or infinity, the Posit floating point number processor can rapidly and accurately output the Posit floating point number representing zero or infinity no matter whether the code obtained by calculation according to the sign field, the true exponent field, the first mantissa field and the protection bit field is the code of zero or infinity or no matter whether the code obtained by calculation according to the sign field, the true exponent field, the first mantissa field and the protection bit field is the calculation efficiency of special code obtained by calculation according to the sign field, the true exponent field, the first mantissa field and the protection bit field.

The intermediate data further includes a symbol field; the decoding circuit further includes: a symbol judgment module;

the symbol judgment module 103 is configured to determine a symbol of the target Posit floating point number according to a most significant bit of the target Posit floating point number, and then take the symbol of the target Posit floating point number as a symbol of intermediate data corresponding to the target Posit floating point number, and output a symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

According to the Posit floating point number standard, the most significant bit of the target Posit floating point number is the sign bit. When the target Posit floating point number is not infinite number or zero, if the highest bit is 1, the target Posit floating point number is negative number, 1 is used as a sign field, and if the highest bit is 0, the target Posit floating point number is positive number, and 0 is used as the sign field. The symbol field of the intermediate data is that after the decoding circuit analyzes the Posit floating point number code, the highest bit of the Posit floating point number, namely the symbol field of the Posit floating point number is directly used as the symbol field.

The decoding circuit further includes: the first exclusive-or device, the second exclusive-or device, the reverse leading zero detection circuit device, the first shift circuit device, the first splicing circuit device and the first extraction circuit device.

A region real symbol determining module 104, configured to perform an exclusive-or operation on a highest bit of a target Posit floating point number and a next highest bit of the target Posit floating point number through the first exclusive-or device, to obtain a real symbol of a region field of the target Posit floating point number;

because the Posit floating point number is in the complement form as a whole, the sign of the region field of the negative Posit floating point number cannot be directly determined by the form of the region field of the Posit floating point number. The method is characterized in that when the Posit floating point number represents negative numbers, the sign of the corresponding positive number is not changed into 1, and the Posit floating point number is inverted by one as the complement. For example, assume that the format of the target Posit floating point number is Posit <8,1>, and that the target Posit floating point number is 01011000, 01011000 representing 3, but-3 is not 11011000, but 10100111+1=10101000.

According to the embodiment of the application, the real symbol of the region field in the target Posit floating point number can be distinguished by using the region real symbol determining module and calculating the two-bit number (the highest bit and the next highest bit of the target Posit floating point number) by using the exclusive OR circuit device, so that the area of a circuit is reduced, and the heating of the Posit floating point number processor in operation is reduced.

Continuing with the above description of the example for the region field, assume that the form of obtaining the region field from the Posit floating point number is 1110, where the Posit floating point number is positive, the region field of the Posit floating point number is 1110; where the Posit floating point number is negative, the entire Posit floating point number is derived from another encoding complement, and necessarily the region field therein is also derived from another encoding 0001 complement.

In view of this, the decoding circuit of the Posit floating point number according to the embodiment of the present application obtains the real symbol of the region field in the Posit floating point number with the region real symbol determining module.

The working principle of the region real symbol determining module is as follows: the binary arbitrary number of bits is kept unchanged by 0 exclusive or, and the bit number of the bit is taken as an inverse code by 1 exclusive or. When the Posit floating point number is positive, the highest bit is 0,0 is exclusive OR with the first bit of the region field, and the first bit of the region field is kept unchanged; when the Posit floating point number is negative, the most significant bit is 1,1 exclusive OR with the first bit of the region field, which is inverted. For example, posit floating point number is 01110, region field 1110 is a positive number, posit floating point number is 11110, region field 1110 should be 0001, and negative number. According to the embodiment of the application, the characteristics of the exclusive algorithm and the properties of the region field are combined, the exclusive OR device is used for exclusive OR of the two digits of the highest order and the next highest order, the real symbol of the region field can be obtained, the circuit is simple, and other operation circuits are not required to be added.

A region field unifying module 105, configured to remove the most significant bit and the least significant bit of the target Posit floating point number for the first time, remove the most significant bit and the least significant bit of the target Posit floating point number for the second time, and perform an exclusive-or operation on the result of the first removal and the result of the second removal through the second exclusive-or device to obtain a region unifying field;

the first removal is to remove the most significant and the next most significant of the target Posit floating point number; the second removal is to remove the same target Posit floating point number from the most significant and least significant bits. The first removal and the second removal refer to removing the most significant bit and the next most significant bit, respectively, for the same target Posit floating point number. Wherein the first and second do not represent a limitation on the order in which the steps are performed.

The working principle of the region field unification module is as follows: the Posit floating point number after the most significant bit and the least significant bit are removed, one bit is different from the Posit floating point number after the most significant bit and the least significant bit are removed, and the least significant bit of the region field is turned over, so that the last significant bit of the region field is always xored with the least significant bit of the region field, belongs to xored of different numbers, the bit xored before the least significant bit of the region field is the same number of xored, the different numbers of xored are 1, the same number of xored is 0, and the obtained region unified field is in the form of a series of 0 and 1. The region unified field is a field obtained by unifying the region field of the preamble 0 and the region field of the preamble 1.

For example, assuming that the target Posit floating point number is "0.sub.110.sub.0.sub.000", the result of the first removal is "110.sub.0.sub.00", the result of the second removal is "10.sub.0.sub.000", and the "0.sub.110.sub.0.sub.000" and "10.sub.0.sub.000" are exclusive-ored, the region unified field "01.sub.0000" is obtained.

According to the embodiment of the application, two coding forms of the region field are unified into one coding form through the region field unifying module, so that the effect that the values of all the region fields (such as 11110 and 00001) can be obtained through one leading zero detection circuit is achieved, the defect that leading zero detection circuits and leading one detection circuits are needed to be used for the region fields of the two coding forms is avoided, and the overlarge circuit area caused by the fact that the leading zero detection circuits and the leading one detection circuits are used simultaneously is avoided.

A region value calculation module 106, configured to detect the region unified field through the reverse leading zero detection circuit device, and obtain a value field of the region field according to an output of the reverse leading zero detection circuit device;

the value field of the region field is a value of the region field expressed in binary.

Another embodiment of the present application proposes a method for detecting a region unified field by using a reverse leading zero detection circuit to obtain a value of the region field. Referring to fig. 2, fig. 2 is a schematic structural diagram of a reverse leading zero detection circuit device according to an embodiment of the present application.

The reverse leading zero detection circuit device comprises an OR device, a first negation device and a second negation device;

The reverse leading zero detection circuit device firstly folds the region unified field for a plurality of times to obtain a plurality of input fields with the bit width of 2. For example, assuming that the region unified field is 000001, a plurality of input fields with a bit width of 2 obtained by the binary circuit are (00), (01). And detecting the input field with each bit width of 2 by using a sub-circuit to obtain the inverse code of the number of 0 in the input field with each bit width of 2.

For example, describing (01) in the input field with a plurality of bit widths of 2, a "1" is the 0 th bit of the input field (01), a "0" is the 1 st bit of the input field (01), a "0" is obtained by inverting the "1", and a "0" is obtained by performing an or operation with the "0" to obtain 0 as the 0 th bit of the corresponding output field of (01). Similarly, the 1 st bit of the output field is 1, the output field corresponding to (01) is '10', and similarly, the sub-circuit is used for calculating (00) to obtain the inverse code [ (01) (01) (10) ] of the value of the unified field of the region, wherein the output field corresponding to (00) is 01.

After the inverse [ (01) (01) (10) ] of the value of the region unified field is obtained, the "10" is inverted to obtain "01", wherein 01 is the number of 0 in (01), which means that 10 exists in (01). The inversion of 01, gives 10, i.e., the number of 0 s in (00), indicating 2 0 s in (00). Further, the detection result of the input field [ (00) (00) (01) ] having a plurality of bit widths of 2 is [ (2) + (2) + (1) ], that is, a total of 5 0 s in 000001.

Detecting the unified field 000001 of the region, obtaining that 5 zeros exist in the unified field, namely the value of the region field is 5, and obtaining that the value of the region field is 101. According to the real symbols of the regions and the values of the unified fields of the regions, the values of the regions in the target Posit floating point number can be obtained clearly.

The reverse leading zero detection circuit provided by the embodiment of the application detects the region unified field to directly obtain the inverse code of the value of the region field, and then performs unified logic inversion on the output field obtained by each sub-circuit, so that the increase of the circuit area caused by frequent inversion on the 1 st bit and the 0 th bit of the input field in each sub-circuit is avoided.

An extraction module 107, configured to shift out, by using the first shift circuit device, the highest three bits of the target Posit floating point number, and shift left the remaining fields of the target Posit floating point number after shifting out the highest three bits by a specified number of bits; the specified bit number is obtained according to the output of the reverse leading zero detection circuit device;

The highest three bits shifted out are the sign bit of the target Posit floating point, the inversion bit of the region field of the target Posit floating point, and 1 bit of the difference between the region unified field and the region field, respectively.

The specified bit number is the number of 0 s to the region unified field after the reverse leading zero detection circuit device detects the region unified field. For example, assuming that the region unified field is 0001, the specified number of bits is 3.

According to the decoding circuit provided by the embodiment of the application, the reverse leading zero detection circuit device is used for detecting and obtaining the number of 0 s of the region unified field, then the number and sign bit of 0 s of the region unified field, the turning bit and 1 bit of the difference between the region unified field and the region field are shifted out, the remaining index field and the second mantissa field with the determined bit widths are obtained, the problem that the index resolution is difficult due to the fact that the bit widths of the region fields in the position floating point number are uncertain is solved, and the index field is further obtained by directly extracting the target position floating point number after the highest three bits and the designated bit number are shifted out.

The real exponent determining module 108 is configured to invert the exponent field when the target Posit floating point number is a negative number, and then splice the exponent field or the inverted exponent field with the value field of the region field through the first splicing circuit device, so as to obtain and output a real exponent field in intermediate data corresponding to the target Posit floating point number;

a first mantissa field determining module 109, configured to zero-fill a low order of the second mantissa field according to a maximum bit width of the first mantissa field to obtain the first mantissa field, and output the first mantissa field; the maximum bit width of the first mantissa field is obtained by subtracting the bit width of the sign bit of the target Posit floating point number, the bit width of the exponent field and the minimum bit width of the region field from the total bit width of the target Posit floating point number;

the second mantissa field extracted from the Posit floating point number is directly used as the first mantissa field of the intermediate data. And splicing the extracted exponent field from the Posit floating point number with the value field of the region field to obtain the real exponent field of the intermediate data. When the region index and the index field are spliced, the region index is in a high order.

Since the bit width of the exponent field to the left is exactly 2 ^es According to the embodiment of the application, the exponent field is directly spliced at the low order of the value field of the region field, so that the carry of the value field of the region field is realized. The exponent field is placed at low level, the value field of the region field is placed at high level, and the exponentiation of the region field is completed by splicing, so that the redundant logic circuit required by utilizing used to exponentiation of the region field is avoided, and the circuit area of the Posit floating point number processor is further reduced.

After the Posit floating point number is converted into the real value of the corresponding binary representation, the exponent field and the region field of the Posit floating point number are unified through used. The unified exponent field and region field are: useed-region+e, where useed=2 ^es Where e refers to the exponent field, region refers to the region field, and es refers to the exponent bit width of the Posit floating point number.

The bit width of the real exponent field is determined by the bit width of the exponent and the bit width of the value field of the region field, and is a fixed value. Still further determining a bit wide range of the first mantissa field: the bit width-sign bit-minimum region field (2 bits) =maximum of the bit width of the first mantissa field of the target Posit floating-point number total bit width-exponent field.

According to the real index field of the intermediate data obtained by the embodiment of the application, the real index field which can participate in operation can be obtained by only splicing the value field of the region field and the index field, the extracted second mantissa field can be directly used as the first mantissa field of the intermediate data, the decoding process is simple, and the calculation steps of a decoding circuit are simplified.

A protection bit output module 110, configured to take a field with a value of 0 for each bit as the protection bit field, and output the protection bit field; the guard bit field has a bit width of 3.

The decoding circuit does not have right shift rounding in the process of converting the target Posit floating point number into intermediate data, so the values of the three guard bits of the guard bit field are directly set to 0.

When the operation circuit operates with intermediate data, the protection bit field is used for rounding the operated result, the rounding principle in the Posit floating point standard is followed, on the other hand, the real exponent field and the first mantissa field are the fields of the target Posit floating point directly extracted or are spliced by each field in the target Posit floating point and still are in the complementary form, so that the intermediate data obtained by the Posit floating point processor provided by the embodiment of the application strictly follow the Posit floating point standard, the obtained intermediate data does not need to be converted into an original code, and the decoding process is simple.

Referring to FIG. 3, FIG. 3 is a schematic diagram of a Posit floating point number processor according to an embodiment of the present application. The Posit floating point number processor includes: a decoding circuit 301, an arithmetic circuit 302, and an encoding circuit 303;

the operation circuit 302 is configured to perform an operation on the received plurality of intermediate data output by the decoding circuit according to the calculation instruction, to obtain an operation result represented by the intermediate data in a complementary form;

the decoding circuit obtains intermediate data: after the infinity field, the zero value field, the sign field, the true exponent field, the first mantissa field and the protection bit field, the operation circuit directly uses intermediate data to operate. When the infinity field or the zero value field in the intermediate data is true, the operation circuit can directly obtain the corresponding special value (the infinity or zero intermediate data), and the protection bit field is used in the operation process or for rounding the operation result. The input of the whole operation circuit is the complement type intermediate data, the output is still the complement type intermediate data, the conversion of the original code and the complement is not needed to be carried out on the intermediate data, and the operation process is simplified.

The encoding circuit 303 is configured to convert the operation result into a Posit floating point number in a specified format according to the specified format in the calculation instruction.

The specified format refers to the convention of the total bit width and exponent bit width of a Posit floating point number. Posit < Total bit Width, exponent bit Width > is generally used as the specified format.

The coding circuit converts the intermediate data output by the operation circuit into Posit floating point number codes according to a format appointed by a Computer Processor (CPU) to the operation result. The whole coding process does not involve conversion from original codes to complementary codes, only all fields of intermediate data are required to be restored to all fields of Posit floating point number coding, and the coding circuit logic is simple.

The encoding circuit further includes an output module:

the output module 401 is configured to directly output the Posit floating point number in the specified format as an infinite number encoding field representing an infinite number when the infinite number segment of the intermediate data is true;

the output module 401 is further configured to directly output the Posit floating point number in the specified format as an infinite number encoding field representing a zero value when the zero value field of the intermediate data is true.

And when the infinite number field of the intermediate data is not true and the zero value field is not true, the output module outputs the Posit floating point number obtained by encoding the sign field, the true exponent field, the first mantissa field and the protection bit field of the intermediate data. It can be understood that according to the sign field, the true exponent field, the first mantissa field and the protection bit field of the intermediate data, the calculation of obtaining the Posite floating point number by encoding is complex, and the Posite floating point number processor processes a plurality of target Posite floating point numbers, so that the time for obtaining the output Posite floating point number is long, therefore, when the infinity field is true or the zero value field is true, the output module directly outputs the special encoding representing 0 or infinity forcibly and preferentially, the time consumed by waiting for the Posite floating point number processor to convert the target Posite floating point number into the intermediate data and then calculating the intermediate data can be avoided, the special encoding is directly output, and the output efficiency of the Posite floating point number processor to the special encoding of 0 or infinity is improved.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an encoding circuit according to an embodiment of the present application.

The encoding circuit 303 includes: the second extraction circuit device, the second shift circuit device, the second splice circuit device, and the following modules:

an exponent field encoding module 402, configured to extract, from the real exponent field of the operation result, a field having the same bit width as the exponent encoding field according to the order from the lowest bit to the highest bit, and obtain the exponent encoding field according to the field having the same bit width as the exponent encoding field, and use the real exponent field after extracting the field having the same bit width as the exponent encoding field as the value corresponding to the region encoding field;

the exponent field coding module is further configured to invert a field with the same bit width as the exponent coding field when the sign field of the intermediate data represents a negative number, to obtain the exponent coding field;

The encoding circuit is the inverse of the decoding circuit, i.e. outputs a Posit (total bit width, exponent bit width) code according to a specific intermediate data type, requiring a shift rounding operation.

The exponent encoding field refers to an exponent field of a Posit floating point number representing the result of an operation.

In the real index field, the region index is in the high order, the index field is in the low order, and the bit width of the index coding field is determined by the format of the Posit floating point number of the operation result, so that the index coding field can be rapidly extracted from the real index field. For example, assuming that the real exponent field is 11101011, the exponent bit width of the Posit floating point number representing the operation result is 2, 11 is directly extracted as the exponent encoding field, and the remaining 111010 is used as the region exponent to be converted into the region encoding field.

A region format determining module 403, configured to determine a filling format of the region coding field according to the sign field of the operation result and the sign of the region coding field;

the region encoding field refers to a region field of a Posit floating point number representing the result of an operation.

The reverse code output by the reverse leading zero detection circuit device is inverted by the region value calculation submodule, the real symbol of the region field is added to obtain the value field of the region field, or the reverse code output by the reverse leading zero detection circuit device is added by the region value calculation submodule, the real symbol of the region field is added to obtain the value field of the region field, and therefore the value field of the region field in the real index field in the intermediate data corresponding to the operation result carries the symbol of the region coding field, and the coding circuit can directly obtain the symbol of the region coding field according to the value field of the region field in the real index field of the extraction index coding field.

Further determining the expression form of the region coding field in the Posite floating point number of the operation result, and combining the sign of the Posite floating point number of the operation result, namely the sign of the intermediate data, and the sign field of the intermediate data.

The filling format refers to: the region code field is in the form of a leading one or leading zero, determined from the sign of the region code field and the sign of the Posit floating point number (sign field). If the Posit floating point number is positive, the region encoding field is also positive, then 10 is filled; if Posit floating point number is positive, region is the negative of the encoding field, then fill 01; if the Posit floating point number is a negative number and the region encoding field is a positive number, then fill 01; if the Posit floating point number is negative, the region encoding field is also negative, then 10 is filled.

A region field coding module 404, configured to splice the filling format, the exponent coding field, the first mantissa field of the operation result and the protection bit field of the operation result in sequence by using the second splicing circuit device to obtain a spliced field, and shift the spliced field to the right arithmetically by using the second shift circuit device according to a value corresponding to the region coding field to obtain the region coding field;

The lowest three bits of the spliced field are the protection bit fields to ensure input protection of the entire spliced field when filled in accordance with the fill format.

For example, assuming that the Posit floating point number is positive, the region encoding field is positive, the padding format is 10, the exponent encoding field is 11, the first mantissa field of the operation result is 110111, the resulting concatenation field is 10.sub.11.sub.110111.sub.000, the corresponding value of the region encoding field is 3, the concatenation field 11110111 000 needs to be arithmetically shifted 3 bits to result in 11110.sub.11.sub.110.sub.111. The mantissa field 111 passes through the protection bits, which ultimately form 111. Thus directly obtaining the region encoding field 11110. The protection bit is used to protect the precision of the Posit floating point number. The Posit floating point standard specifies three Guard bits GRS called Guard, round, sticky, respectively.

If the total bit width of the calculation result Posit floating point number Posit <12,2> specified by the calculation instruction is 12 bits, the rounding is needed to be performed on 1111110 11110111, the rounded spliced field is 1111110 11110, and during the rounding process, 111 passes through the protection bits 000, 000 respectively correspond to GRS bits, that is, S bits, and the S bits are fixed to be 1.

And the floating point number result determining module 405 is configured to perform rounding operation on the spliced field after the rightward shift by using the protection bit field, and add a sign field of the operation result to a most significant bit of the spliced field after the rounding operation, so as to obtain the Posit floating point number in the specified format.

Rounding operations may be understood as binary "rounding" operations.

And according to the fact that the Posit floating point number is positive, the sign field of the intermediate data is 1, and sign bits are spliced on the highest bit of the rounded spliced field 1111110 11110, so that an operation result Posit floating point number 11111110 11110 in a specified format is obtained.

According to the standard specification of Posit, the encoding circuit takes saturation operation for the encoding process of intermediate data.

The floating point number result determining module comprises:

The values of any two digits in the spliced field after right shifting are different, namely, all spliced fields in other forms except that the spliced field after right shifting is in the forms of 00000 … … 0 and 11111 … … 1.

The standard specification of Posit is that when special codes (infinite number codes and zero value codes) are not considered in the process of coding, the code of the minimum value of the positive Posit floating point number is 00000 … … 01, the code of the maximum value of the positive Posit floating point number is 01111 … … 1, the code of the negative Posit floating point number is 1111111 … … 1 when the absolute value of the negative Posit floating point number is maximum, the code of the negative Posit floating point number is 10000 … … 01 when the absolute value of the negative Posit floating point number is minimum, and the saturation operation is that when the number after coding is smaller than the code of the minimum value of the Posit floating point number, the code of the minimum value of the Posit floating point number is 00000 … … 01; when the number after encoding is smaller than the encoding of the maximum value of the Posit floating point number, the encoding of the maximum value of the Posit floating point number is adopted, namely 1111111 … ….

The arithmetic circuit can directly use the real index field and the first mantissa field in the intermediate data to carry out operation, and after the constituent fields of the Posit floating point number are extracted and spliced according to the encoding rule of the Posit floating point number, the real index field and the first mantissa field can be obtained, the real index field and the first mantissa field are fixed points in the complement form, the operation result represented by the intermediate data is still fixed points in the complement form after a plurality of intermediate data are operated according to the calculation instruction, and the encoding circuit can complete the encoding of the Posit floating point number by converting the fixed points in the complement form into the encoding format of the Posit floating point number only according to the format appointed by the CPU. The process does not need to convert the Posit floating point number into the original code and then convert the original code into the Posit floating point number, so that the processing operation of the Posit floating point number is simplified. The method avoids the redundancy and waste of calculation caused by the fact that the Posit floating point number is converted into the original code and the complementary code is needed during calculation.

The sign field in the intermediate data participates in the operation of the mantissa field in the operation circuit, and the sign field of the operation result is directly output. The method can be directly used in an operation circuit, can be used for obtaining a sign of an operation result, can also be used in an encoding circuit, can be used for obtaining a region encoding field, and can be directly used as the highest bit of the Posit floating point number for finally representing the operation result, when the complement is not needed to be considered, the difference of encoding forms of the positive and negative Posit floating points is avoided, and the processing operation of the Posit floating point number is simplified.

In this specification, each embodiment is described in a progressive or illustrative manner, and each embodiment is mainly described by the differences from other embodiments, and identical and similar parts between the embodiments are mutually referred.

While preferred embodiments of the present embodiments have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the present application.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, or terminal device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, or circuit. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus or circuit comprising such elements.

The above description of the present application provides a Posit floating point processor, and the description of the above embodiments is only used to help understand the working principle of the Posit floating point processor of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A Posit floating point processor, the Posit floating point processor comprising: a decoding circuit, an arithmetic circuit, and an encoding circuit;

The encoding circuit is used for converting the operation result into Posit floating point numbers with the specified format according to the specified format in the calculation instruction;

wherein the decoding circuit includes: the first exclusive-or device, the second exclusive-or device, the reverse leading zero detection circuit device, the first shift circuit device, the first splicing circuit device, the first extraction circuit device and the following modules:

The protection bit output module is used for taking a field with the value of 0 of each bit as the protection bit field and outputting the protection bit field; the bit width of the protection bit field is 3;

wherein the encoding circuit includes: the second extraction circuit device, the second shift circuit device, the second splice circuit device, and the following modules:

2. The Posit floating point number processor of claim 1, wherein the intermediate data further comprises an infinity field and a zero value field; the decoding circuit further includes: an infinity number determining module and a zero value judging module;

3. The Posit floating point number processor of claim 2, wherein the intermediate data further comprises a sign field; the decoding circuit further includes: a symbol judgment module;

4. The Posit floating point number processor of claim 1, wherein the encoding circuit further comprises an output module:

5. The Posit floating point number processor of claim 1, wherein said reverse leading zero detection circuit device comprises an or device, a first inverting device, a second inverting device;

the reverse leading zero detection circuit device is configured to perform an inverse operation on the 0 th bit of the input field with the bit width of 2 by using the first inverse device, and then perform an or operation on the 1 st bit of the input field with the bit width of 2 and the multiple inverse results by using the or device, so as to obtain the 0 th bit of the multiple output fields; the input field with the bit width of 2 is obtained by processing the region unified field through a binary circuit;

6. The Posit floating point number processor of claim 5, wherein the region value calculation module comprises:

7. The Posit floating point number processor of claim 1, wherein the floating point number result determination module comprises:

8. The Posit floating point number processor of claim 1, wherein the exponent field encoding module is further configured to invert a field having a bit width identical to a bit width of the exponent encoded field to obtain the exponent encoded field when a sign field of the intermediate data represents a negative number;