CN111526355A

CN111526355A - Pixel control signal verification in stacked image sensors

Info

Publication number: CN111526355A
Application number: CN201911372081.7A
Authority: CN
Inventors: M·J·斯特德曼; S·C·丹尼; S·沙玛
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-02-01
Filing date: 2019-12-27
Publication date: 2020-08-11
Anticipated expiration: 2039-12-27
Also published as: CN111526355B

Abstract

The invention provides a pixel control signal verification in a stacked image sensor. An image sensor may be formed of a first substrate and a second substrate stacked. The imaging pixel array and the verification circuitry may be formed in a first substrate. The row control circuits may be formed in a second substrate. The row control circuitry may provide row control signals to the imaging pixel array. The verification circuitry may also receive row control signals from the row control circuitry. The first substrate may include a plurality of n-channel metal oxide semiconductor transistors and may not include any p-channel metal oxide semiconductor transistors. The verification circuit may include an SR latch circuit having an S node coupled to the pull-up line and an R node coupled to the pull-down transistor to ensure that the SR latch circuit is enabled in the set state. The verification circuit may include a level shifter that shifts the control signal voltage when the control signal is at a low level.

Description

Pixel control signal verification in stacked image sensors

This application claims the benefit of provisional patent application No.62/799,802 filed on 2019, 2/1, which is hereby incorporated by reference in its entirety.

Technical Field

The present invention relates generally to image sensors and, more particularly, to methods and circuits for testing the integrity of components in image sensors.

Background

Image sensors are often used in electronic devices such as mobile phones, cameras and computers to capture images. Conventional image sensors are fabricated on a semiconductor substrate using Complementary Metal Oxide Semiconductor (CMOS) technology or Charge Coupled Device (CCD) technology. The image sensor may include an array of image sensor pixels, each pixel including a photodiode and other operational circuitry, such as transistors formed in a substrate.

Image sensors may be prone to failure throughout the lifetime of the electronic device. Conventional image sensors are sometimes provided with methods and circuits for testing the functionality of the image sensor. However, including circuitry for testing the functionality of the image sensor can complicate the manufacturing process of the image sensor. In addition, in the conventional image sensor, a single semiconductor substrate is used for the image sensor. This may reduce the amount of space available for the pixel photodiode.

It is therefore desirable to be able to provide an improved image sensor including circuitry for testing the functionality of the image sensor.

Drawings

FIG. 1 is a schematic diagram of an exemplary electronic device having an image sensor, according to one embodiment.

Fig. 2 is a perspective view of an exemplary image sensor formed using stacked substrates according to one embodiment.

FIG. 3 is a schematic diagram of an exemplary image sensor having a pixel array and verification circuitry formed in a first substrate and readout circuitry formed in a second substrate, according to one embodiment.

Fig. 4 is a circuit diagram of an exemplary pixel that may be included in an image sensor (such as the image sensor of fig. 3) according to one embodiment.

Fig. 5 is a circuit diagram of an exemplary verification circuit that may be included in an image sensor (such as the image sensor of fig. 3), according to one embodiment.

FIG. 6 is a circuit diagram of an exemplary latch circuit that may be included in an authentication circuit of an image sensor, according to one embodiment.

Fig. 7 is a circuit diagram of an exemplary level shifter that may be used to shift a control signal to a low logic level closer to ground potential, according to one embodiment.

Detailed Description

Embodiments of the invention relate to an image sensor. It will be understood by those skilled in the art that the exemplary embodiments of the invention may be practiced without some or all of these specific details. In other instances, well known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include an image sensor that collects incident light to capture an image. The image sensor may include an array of pixels. Pixels in an image sensor may include a photosensitive element, such as a photodiode that converts incident light into an image signal. The image sensor may have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., mega pixels). The image sensor may include a control circuit (such as a circuit for operating the pixels) and a readout circuit for reading out an image signal corresponding to the charge generated by the photosensitive element.

FIG. 1 is a schematic diagram of an exemplary imaging and response system including an imaging system that captures images using an image sensor. The system 100 of fig. 1 may be an electronic device, such as a camera, mobile phone, video camera, or other electronic device that captures digital image data, may be a vehicle security system (e.g., an active braking system or other vehicle security system), or may be a surveillance system.

As shown in fig. 1, system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). The imaging system 10 may include a camera module 12. The camera module 12 may include one or more image sensors 14 and one or more lenses.

Each image sensor in camera module 12 may be the same or there may be different types of image sensors in a given image sensor array integrated circuit. During image capture operations, each lens may focus light onto an associated image sensor 14. Image sensor 14 may include light sensitive elements (i.e., pixels) that convert light into digital data. An image sensor may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., several mega pixels). For example, the image sensor 14 may include a bias circuit (e.g., a source follower load circuit), a sample and hold circuit, a Correlated Double Sampling (CDS) circuit, an amplifier circuit, an analog-to-digital converter circuit, a data output circuit, a memory (e.g., a buffer circuit), an addressing circuit, and the like.

Still image data and video image data from the camera sensor 14 may be provided to the image processing and data formatting circuit 16 via path 28. The image processing and data formatting circuit 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, video image stabilization, face detection, and the like. The image processing and data formatting circuitry 16 may also be used to compress raw camera image files as needed (e.g., into a joint photographic experts group format or JPEG format for short). In a typical arrangement, sometimes referred to as a system-on-a-chip (SOC) arrangement, the camera sensor 14 and the image processing and data formatting circuit 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). The camera sensor 14 and the image processing circuit 16 may be formed on separate semiconductor substrates, if desired. For example, the camera sensor 14 and the image processing circuit 16 may be formed on separate substrates that have been stacked.

Imaging system 10 (e.g., image processing and data formatting circuitry 16) may communicate the acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include processing software for detecting objects in images, detecting movement of objects between image frames, determining distances of objects in images, filtering, or otherwise processing images provided by imaging system 10.

The system 100 may provide a number of advanced functions for the user, if desired. For example, in a computer or advanced mobile phone, the user may be provided with the ability to run user applications. To achieve these functions, the host subsystem 20 of the system 100 may have input-output devices 22 (such as a keypad, input-output ports, joystick, and display) and storage and processing circuitry 24. The storage and processing circuitry 24 may include volatile memory and non-volatile memory (e.g., random access memory, flash memory, hard disk drives, solid state drives, etc.). The storage and processing circuitry 24 may also include a microprocessor, microcontroller, digital signal processor, application specific integrated circuit, or the like.

The system 100 may be a vehicle security system. In a vehicle security system, images captured by an image sensor may be used by the vehicle security system to determine environmental conditions around the vehicle. For example, vehicle safety systems may include systems such as parking assist systems, automatic or semi-automatic cruise control systems, automatic braking systems, collision avoidance systems, lane keeping systems (sometimes referred to as lane drift avoidance systems), pedestrian detection systems, and the like. In at least some cases, the image sensor may form part of a semi-autonomous or autonomous unmanned vehicle. Vehicle safety standards may require that any components of the vehicle safety system, including the image sensor, be verified to be operating properly before, during, and/or after operation of the vehicle. The verification operation of the image sensor may be performed by the imaging system before, during, and/or after operation of the vehicle (e.g., upon activation and/or deactivation of the imaging system).

The image sensor 14 may be implemented using a single semiconductor substrate, if desired. Alternatively, the image sensor 14 may be implemented in a stacked die arrangement. In a stacked die arrangement, the pixels may be formed in a substrate and the readout circuitry may be formed in a separate substrate. The pixels may optionally be divided between two substrates. The substrate layer may be a layer of semiconductor material, such as a silicon layer. The substrate layers may be connected using metal interconnects. An example is shown in fig. 2, where

substrates

42,44, and 46 are used to form image sensor 14.

Substrates

42,44, and 46 may sometimes be referred to as chips. The upper chip 42 may include photodiodes in the pixel array 32. A charge transfer transistor gate (e.g., transfer transistor 58 in fig. 4) may also be included in upper chip 42. However, to ensure that there is sufficient space in the upper chip 42 for the photodiodes, most of the circuitry of the image sensor may be formed in the middle chip 44 and the lower chip 46.

The middle chip 44 may be bonded to the upper chip 42 at each pixel with an interconnect layer. For example, the pixel circuits 34 in the middle chip 44 may be bonded to a Floating Diffusion (FD) connected to a charge transfer transistor formed in the upper chip 42. Bonding each pixel in the upper chip 42 to a corresponding pixel circuit (e.g., floating diffusion to floating diffusion) in the middle chip 44 may be referred to as hybrid bonding. The middle chip 44 and the lower chip 46 may be coupled without hybrid bonding. Only the peripheral electrical contact pads 36 of each chip may be joined together (e.g., chip-to-chip connections 38). Each chip in the image sensor 14 may include associated circuitry. The upper chip may include a photodiode and a charge transfer transistor gate. The middle chip may include pixel circuitry (e.g., floating diffusion node, source follower transistor, reset transistor, etc.). The bottom chip 46 (sometimes referred to as an ASIC chip) may include one or more of clock generation circuitry, pixel addressing circuitry, signal processing circuitry, such as Correlated Double Sampling (CDS) circuitry, analog-to-digital converter circuitry, digital image processing circuitry, system interface circuitry, clamp input generator circuitry, clamp transistors, and clamp circuitry.

The example shown in fig. 2 is merely exemplary. As previously mentioned, in another embodiment, the image sensor may include two substrates. In this embodiment, the first substrate may include a photodiode, a charge transfer transistor gate, and pixel circuitry (e.g., a floating diffusion node, a source follower transistor, a reset transistor, etc.). The second substrate (e.g., ASIC chip) may include one or more of clock generation circuitry, pixel addressing circuitry, signal processing circuitry (such as CDS circuitry), analog-to-digital converter circuitry, digital image processing circuitry, system interface circuitry, clamp input generator circuitry, clamp transistors, and clamp circuitry.

Fig. 3 shows an exemplary image sensor 14 comprising a plurality of substrates and verification circuitry. Image sensor 14 includes an array of pixels, such as array 32 of pixels 52 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels 52). The image sensor 14 may sense light by: the impinging photons are converted into electrons or holes that accumulate (collect) into sensor pixels in the pixel array 32. After the accumulation period is completed, the collected charge may be converted to a voltage, which may be provided to an output terminal of the image sensor 14. After the charge-to-voltage conversion is complete and the resulting signal is transferred out of the pixel, the pixel of image sensor 14 may be reset in preparation for accumulating new charge. In some implementations, the pixel can use a floating diffusion region (FD) as the charge detection node. When a floating diffusion node is used, reset may be accomplished by turning on a reset transistor that conductively connects the FD node to a voltage reference, which may be the pixel SF drain node.

As shown in fig. 3, the image sensor 14 may also include row control circuitry 22 (sometimes referred to as row decoders/drivers). Row control circuitry 22 may send control signals to pixel array 32 (e.g., via control lines 86) to control the operation of the pixels in pixel array 32. For example, row control circuitry 22 may send a transfer control signal (TX), a reset control signal (RST), a row select control signal (RS), and/or a dual conversion gain control signal (DCG) to pixel array 32 and/or to verify circuitry 45 using control lines 86. A transfer control signal may be provided to the transfer transistor in each pixel in a given row. A reset control signal may be provided to the reset transistor in each pixel in a given row. A row select control signal may be provided to the row select transistor in each pixel in a given row. A dual conversion gain control signal may be provided to the dual conversion gain control transistor in each pixel in a given row.

Each pixel in pixel array 32 may be coupled to a corresponding column line 24. Each column line may be coupled to each pixel in a respective column of the pixel array. During operation of the pixel array 32, the pixels may output a voltage that is based on the amount of light collected onto the column lines 24 (sometimes referred to as column output lines 24) during an accumulation period. Each column line 24 is coupled to a respective analog-to-digital converter (ADC) 26. The analog-to-digital converter is used to convert the voltage received from the column output line into a digital signal. Analog-to-digital converter 26 may be an analog ground-referenced analog-to-digital converter.

In some cases, as shown in fig. 3, the image sensor includes a clamp transistor. Clamp transistor 28 may be coupled between column output line 24 and bias voltage source terminal 30. The bias voltage source terminal 30 may supply a bias voltage, such as V_AAPIXOr another desired bias voltage. In the example of fig. 3, the clamp transistor 28 is an n-channel metal oxide semiconductor (nMOS) transistor having a drain terminal coupled to the bias voltage source terminal 30 and a source terminal coupled to the column output line 24. The gate of each clamp transistor may receive a signal from a clamp input generator 20. The clamp input generator 20 may output either a ground referenced clamp input or a power referenced clamp input. During normal imaging operation (when pixel array 32 is used to collect light during an accumulation period), clamp input generator 20 may output a reference supply voltage (e.g., V)_AAPIX) The generated power reference clamp input. During a test operation (sometimes referred to as a verify operation), clamp input generator 20 may output a ground-referenced clamp input that is generated with reference to an analog ground potential. In some cases, using an analog ground referenced clamp input may ensure a high precision test input during test operations.

The image sensor of fig. 3 may also include a VLN signal generator 72 that generates a corresponding VLN signal. The VLN signal is provided to the gate of VLN transistor 74. In the example of fig. 3, VLN transistor 74 is an n-channel metal oxide semiconductor (nMOS) transistor having a drain terminal coupled to column output line 24 and a source terminal coupled to ground potential 76. VLN transistor 74 and VLN signal generator 72 may form an nMOS current source used during readout and testing of pixels in the image sensor.

VLN signal generator 72 and clamp input generator 20 may be part of control and processing circuitry 82. Analog-to-digital converter 26, clamp transistor 28, and VLN transistor 74 may be considered part of column control and readout circuitry 84. The control and processing circuitry 82 may correspond to the image processing and data formatting circuitry 16 of fig. 1. The control and processing circuitry 82 may be coupled to the row control circuitry 22 and may be coupled to the column control and readout circuitry 84. Row control circuitry 22 may receive row addresses from control and processing circuitry 82 and may supply corresponding row control signals (e.g., TX, RST, RS, DCG) to image pixels in image array 32 (e.g., a dual conversion gain control signal, a pixel reset control signal, a charge transfer control signal, a halo control signal, a row select control signal, or any other desired pixel control signal) via control path 86. Column control and readout circuitry 84 may be coupled to columns of pixel array 32 via column lines 24. Column lines 24 may be used to read out image signals from image pixels and supply bias signals (e.g., bias currents or bias voltages) to the image pixels. During an image pixel readout operation, a row of pixels in image pixel array 32 may be selected using row control circuitry 22, and image data associated with the image pixels of the row of pixels may be read out on column lines 24 by column control and readout circuitry 84.

In addition to the analog-to-digital converters, clamp input transistors, and VLN transistors shown in fig. 3, column control and readout circuitry 84 may also include column circuitry such as column amplifiers for amplifying signals read out of array 32, sample and hold circuitry for sampling and storing signals read out of array 32, column memory for storing the read signals and any other desired data, and/or any other desired components. Column control and readout circuitry 84 may output digital pixel values to control and processing circuitry 82.

Array 32 may have any number of rows and columns. In general, the size of the array 32 and the number of rows and columns in the array 32 will depend on the particular implementation of the image sensor 14. Although rows and columns are generally described herein as horizontal and vertical, respectively, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically and features described herein as columns may be arranged horizontally).

Image sensors may be susceptible to failure throughout their lifetime. Accordingly, the image sensor 14 in FIG. 3 may include a verification circuit 45 for testing the functionality of the image sensor. In some implementations, the verification circuitry 45 can include dummy pixels 47. The virtual pixels 47 may include some or all of the components from the imaging pixels of the array 32 (even if the virtual pixels are not configured to measure incident light). The verification circuit 45 may also include logic circuits, comparison circuits, and latch circuits, if desired. Verification circuitry 45 may include circuitry arranged in respective verification circuit blocks. Each verification circuit block may include one or more virtual pixels.

The row control circuitry 22 and the pixel array 32 may be integrated together in a single integrated circuit (as one example), if desired. Alternatively, the row control circuitry 22 and the pixel array 32 may be implemented in separate semiconductor substrates. In one example, as shown in fig. 3, pixel array 32 and verification circuitry 45 may be formed in first chip 92, while additional circuitry (e.g., row control circuitry 22, clamp input generator 20, ADC 26, etc.) is formed in second chip 94. The first chip may sometimes be referred to as a pixel sensor chip. The second chip may be referred to as an Application Specific Integrated Circuit (ASIC) chip. The two chips may be connected by a conductive interconnect layer (e.g., hybrid bond and/or bond at peripheral contact pads).

In the above-described implementation using stacked chips to implement the image sensor 14, it may be desirable for the verification circuitry (e.g., the verification circuitry 45 in the pixel sensor chip) to have only nMOS (n-channel metal oxide semiconductor) transistors. Including nMOS transistors (and no pMOS transistors) only in the pixel sensor chip can reduce the amount of implantation steps required to form the chip during fabrication. In addition, forming a pixel sensor chip with only nMOS transistors (and no pMOS transistors) may reduce contamination. Therefore, it may be desirable to use only nMOS transistors in the pixel sensor chip.

Row control circuitry 22 may provide row control signals to the image pixels (e.g., via control paths 86) for capturing image data. The verification circuitry may also receive row control signals from row control circuitry 22. The verification circuitry may identify a predetermined range of acceptable row control signal amplitudes based on the type of row control signal and the operating mode of the image sensor. When the output test signal is not within the determined range, an error flag may be output from the image sensor.

The ASIC chip 94 may also include one or more p-channel metal oxide semiconductor (pMOS) current sources 96 (e.g., current sources formed from one or more pMOS transistors). The pMOS current source 96 may be used as an active load for the verification circuit 45 in the pixel sensor chip. However, in order to ensure that the nMOS structure is formed only in the pixel sensor chip 92, the pMOS current source 96 is formed in the ASIC chip 94. The row select signal from row control circuit 22 may be used as a power-up signal for verification circuit 45 (e.g., the row select signal may be asserted in the row to be tested). For example, the row select control signal (RS) is asserted to enable testing using a given row of the verification circuitry. Current sources from the ASIC chip (e.g., from current source 96) may be provided only to rows enabled by assertion of the row select control signal. Activating only the verification circuitry of the selected row may reduce power consumption during testing. The verification circuit may have an nMOS source follower transistor and an nMOS row select transistor. Since the verification circuit is within the chip 92, a pMOS structure is not formed in the verification circuit.

Fig. 4 is a circuit diagram showing the structure of the pixel 52 in fig. 3. As shown in fig. 4, the pixel 52 includes a photodiode 54, a floating diffusion region (FD)56, and a transfer transistor 58. The photodiode 54 may sense light by converting impinging photons into electrons or holes. The transfer transistor 58 may be asserted to transfer charge from the photodiode 54 to the floating diffusion region 56. A row select transistor 64 is interposed between the drain of the source follower transistor 60 and the column output line 24. Is composed ofThe charge is read out of the floating diffusion region 56, the row select transistor 64 is asserted and the voltage corresponding to the charge at the floating diffusion region is read out on the column output line 24. The floating diffusion region 56 is coupled to a source follower transistor 60 and a reset transistor 62. The source follower transistor is further coupled to a bias voltage supply line 63 which provides a bias voltage V_AAPIX。

After the charge-to-voltage conversion is completed and the resulting signal is transferred out of the pixel (by asserting the row select transistor 64), the pixel can be reset by asserting the reset transistor 62 and coupling the floating diffusion region to the bias voltage supply line 63. Since the pixels 52 are formed in the pixel sensor chip 92, all of the transistors in the pixels 52 can be nMOS transistors. In other words, the transfer transistor 58, the reset transistor 62, the source follower transistor 60, and the row select transistor 64 are all nMOS transistors. The pixel structure shown in fig. 4 is merely exemplary. If desired, the pixel 52 may include any other desired pixel components (e.g., one or more storage diodes, one or more storage capacitors, an anti-blooming transistor, one or more dual conversion gain transistors, one or more dual conversion gain capacitors, etc.) in any desired configuration.

Fig. 5 is a circuit diagram showing the structure of the verification circuit 45 (including the dummy pixels 47) in fig. 3. As shown in FIG. 5, each dummy pixel 47 may include a source follower transistor 60 coupled at V_AAPIXAnd row select transistor 64. A row select transistor 64 is coupled between source follower transistor 60 and column line 24. Each dummy pixel may also include a corresponding verify circuit 47V (sometimes referred to as verify circuit 47V, verify circuit portion 47V, or verify circuit block 47V). The verification circuit 47V may receive control signals such as a transfer control signal TX, a reset control signal RST, and a row selection control signal RS from the row control circuit 22. Verify circuit 47V may also be coupled to pMOS current source 96. pMOS current source 96 may provide a current source for verify circuit 47V. However, in order to ensure that the nMOS structure is formed only in the pixel chip 92, the pMOS current source is formed in the ASIC chip 94, and each dummy pixel 47 is formed in the pixel chip 92The verification circuit 47V and the rest. As mentioned previously, the row selection signal RS serves as an enable signal for the verification circuit 47V. Therefore, only the pixel 47 in which the row select control signal RS is asserted will receive the supply current from the pMOS current source 96.

To ensure that the nMOS structure is formed only in the pixel chip 92, the source follower transistor 60 and the row select transistor 64 of each dummy pixel 47 are formed of nMOS transistors. In addition, the verification circuit of each virtual pixel is formed only by the nMOS structure.

The verify circuitry 47V for each dummy pixel may also include logic circuitry, comparison circuitry, level shifting circuitry, and/or latching circuitry (e.g., NAND gates, NOR gates, SR latches, etc.), if desired. The virtual pixels may be used to perform many tests of control signals and functions within the image sensor 14. For example, dummy pixels may be used to perform a reset signal check. In the reset signal check, the reset signal is made low during the analog-to-digital conversion. If the reset signal is low, the FDIN node will be low during the analog-to-digital conversion. If the reset signal is not low, a fault has occurred and the FDIN node will be high during the analog-to-digital conversion. The reset signal check may use a nand gate in the verification circuit. The virtual pixels may also be used to perform a row address check. The row address check may use a NAND gate, a NOR gate, and an SR latch in the verify circuitry. The dummy pixels may also be used to perform transfer control signals, reset control signals, row select control signal propagation checks (sometimes referred to as TX, RST, RS propagation checks) in FD merge mode. The dummy pixels may also be used to perform a Dual Conversion Gain (DCG) mode check.

The outputs of the dummy pixels in the respective columns are provided to column lines 24. Column line 24 may be connected to a clamp transistor, a VLN transistor, and an analog-to-digital converter, as shown in fig. 3. The ADC output may be output in the form of image data or a register output. The ADC output may be examined (e.g., by the control and processing circuitry 82) to determine whether it is within a predetermined range (e.g., a predetermined range expected for a given test). When the output is not within the determined range, an error flag may be output from the image sensor (e.g., noting that a fault has occurred). Generally, the validation circuit can identify a predetermined range of acceptable control signal amplitudes based on the type of control signal (e.g., TX, RST, RS, or DCG) and the operating mode of the image sensor. A row image pattern may be output for each column or for some columns. To check the row address selected by the row decoder, a unique row image pattern for each row or some rows may be output from the ADC connected to the virtual pixel column.

In the example of fig. 5, a column of virtual pixels is shown. This example is merely exemplary. Additional columns of dummy pixels may be included in the verification circuitry 45 if desired. Each column of dummy pixels may be coupled to a respective pMOS current source 96 in the ASIC chip 94. In an alternative implementation, two or more pMOS current sources may be coupled to a virtual pixel in a given column.

The image sensor shown in fig. 3 may be divided between the substrates in any desired manner. In one illustrative example (shown in fig. 3), pixel array 32 and verification circuitry 45 may be formed in a first substrate (e.g., pixel sensor chip 92), while row control circuitry 22, clamp input generator 20, ADCs 26, etc. may be formed in a second substrate (e.g., ASIC chip 94). The first substrate and the second substrate may be connected by hybrid bonding and/or peripheral bonding, as shown in fig. 2. In this example, either of the first substrate and the second substrate may include a verification circuit. However, the verification circuitry (with the pixels and the dummy pixel components) in the first substrate may comprise nMOS transistors only, as described in connection with fig. 3 and 5.

In another illustrative example, pixel array 32 may be formed using two substrates, with at least the photodiode in a first substrate and at least the row select transistor in a second substrate. The row control circuit 22, the clamp input generator 20, the ADC 26, etc. may be formed in a third substrate. The first substrate, the second substrate, and the third substrate may be connected by hybrid bonding and/or peripheral bonding. In this example, any one of the first substrate, the second substrate, and the third substrate may include a verification circuit. However, the verification circuitry (with the pixels and the dummy pixel components) in the first substrate and/or the second substrate may comprise nMOS transistors only, as described in connection with fig. 3 and 5. In general, the array 32, row control circuitry 22, column control and readout circuitry 84, and control and processing circuitry 82 may be divided between two or more stacked substrates in any desired manner.

An example of an exemplary verification circuit is shown in FIG. 6. FIG. 6 shows an exemplary verify circuit block 47V including latch circuit 102. Latch circuit 102 (sometimes referred to as SR latch circuit 102) is an SR latch designed to ensure that assertion of transfer control signal TX follows assertion of reset control signal RST. The latch circuit may start in a set state when the row of pixels associated with the latch circuit is being tested. When the reset control signal RST is asserted, the latch circuit is reset. Subsequent assertion of the transfer control signal TX then restores the latch circuit to the set state.

Properly testing the sequential assertion of the reset control signal RST and the transfer control signal TX may require the latch circuit to begin testing in a set state. However, since the latch circuit is powered down when the row associated with the latch circuit is not being read, the latch circuit cannot respond to the signal and the previous state of the latch is not retained. Thus, the latch circuit may be powered on in either the set or reset state, if not carelessly. If the latch circuit is powered on in the reset state, the verify operation may be inaccurate.

The latch circuit 102 in fig. 6 is designed to ensure power-on (enable) in the set state. The S node 104 is coupled to a pull-up line 106, holding S high. The pull-up line 106 may be coupled to the pMOS current source 96 in the chip 94 as shown in fig. 3. When the latch circuit is powered on, S will be high and the latch circuit will be in the set state. Then, when the reset control signal RST is asserted, the transistor 114 will be asserted, thereby flipping the latch circuit to a reset state (e.g., asserting the reset signal RST at a logic high level such that the R node is at a logic high level and the S node is at a logic low level). Next, when the transfer control signal TX is asserted, the transistor 112 will be asserted, flipping the latch circuit back to the set state (e.g., asserting the transfer control signal TX at a logic high level such that the S node is at a logic high level and the R node is at a logic low level).

A pull-down transistor 108 is included to hold the R node low when the latch is deselected. Transistor 108 is coupled between R-node 110 and a ground bias power supply terminal. The gate terminal of transistor 108 may receive an inverted row select signal RSB. When the row select control signal RS is low, RSB will be high, ensuring that transistor 108 is asserted and the R node is held low. When the row select control signal RS is high, RSB will be low, thereby de-asserting the transistor 108.

In the example of fig. 6, the pull-down transistor 108 is coupled to the R node 110. This example is merely exemplary. The pull-down transistor may alternatively or additionally be coupled to the S-node 104 depending on the design of the verification circuit. The pull-down transistor may have a gate that receives either an inverted row control signal or a normal row control signal, depending on the application.

An inverter 116 may be included to receive the row selection control signal RS and output an inverted row selection signal RSB. The inverter 116 may be an nMOS inverter (e.g., with a diode-connected load or a pull-up bias voltage). The inverter 116 may be shared between two or more latch circuits (e.g., multiple latch circuits associated with a given row may receive the inverted signal RSB from the inverter).

The latch circuit 102 may also include a transistor 118 coupled between the R node 110 and the pull-up line 120. The pull-up line 120 may be coupled to the pMOS current source 96 in the chip 94 as shown in fig. 3. The latch circuit of fig. 6 may have an output node 162. The output from the latch circuit may be provided from the output node 162 to additional logic circuitry and/or to a floating diffusion node of the dummy pixel (e.g., as shown in fig. 5) to ensure that the RST and TX signals are asserted in proper order. The latch circuit 102 may also include a transistor 122 interposed between the S-node 104 and the transistor 114.

Transistors

118 and 122 may each receive a row control signal RS at their gate terminals.

Transistors

118 and 122 thus function as enable transistors. The latch circuit may operate only when RS is asserted. A resistor 124 may be included between the pull-up line 106 and the S node 104. Resistor 124 may optionally be omitted.

The location of enable

transistors

118 and 122 in fig. 6 is merely exemplary. In some cases, enable transistors 118 and/or 122 may be at different locations within the depicted circuit. For example, in one exemplary alternative embodiment, the enable transistor 122 may be located at the place of the resistor 124 (e.g., between the S-node 104 and the pull-up line 106).

The pull-up line 106 coupled to the S-node 104 may help ensure that the latch circuit 102 is powered on in the set state (by keeping the S-node high). The pull-down transistor 108 coupled to the R node 110 may also help ensure that the latch circuit 102 is powered on in the set state (by keeping the R node low). In other words, when the latch circuit 102 is enabled (e.g., when

transistors

118 and 122 are asserted to enable operation of the latch circuit), the S node will be high and the R node will be low, thereby ensuring that the SR latch circuit is in a set state.

The pull-up lines 106 and 120 (sometimes referred to as bias voltage supply lines, pull-up bias voltage lines, etc.) may be coupled to a pMOS current source, such as pMOS current source 96 in fig. 3 and 5. Since only nMOS transistors may be formed in the first chip 92, the pMOS current source may be formed in the second chip, while the remaining latch circuits shown in fig. 6 are formed in the first chip.

In fig. 6, the S node is coupled to the gates of two S transistors in series. Similarly, the R node is coupled to the gates of two R transistors in series. This example is merely exemplary. The S-node and R-node may be coupled to the gates of only one transistor instead of two transistors in series, may be coupled to the gates of two transistors coupled in parallel, etc., if desired. In general, the S and R transistors of the SR latch circuit may have any desired arrangement.

Some pixel row control signals may have a logic low level that is slightly above ground potential. This may cause undesirable leakage currents and/or logic failures. To account for these logic low level signals above ground, the verification circuitry in image sensor 14 may also include a level shifter for bringing the non-zero logic low level closer to ground. FIG. 7 illustrates an exemplary level shifter that may be included in a verify circuit. The level shifter may shift the low level closer to ground potential. However, it is desirable that the high level is not affected by the level shifter. Thus, the level shifter may be designed not to shift the signal when received at a high level (or to shift the signal by a lesser amount when the signal is at a high level).

The reset control signal RST may need to be shifted closer to ground potential to optimize the performance of the image sensor. Fig. 7 shows an exemplary level shifter 142 that receives a reset control signal RST at a gate terminal of a transistor 144. Transistor 144 is an nMOS source follower that functions as a level down shifter. The nMOS source follower transistor 144 operates using a bias current to ground. A current mirror 146, to which a reference current is fed via a pull-up line 158, may be used to provide a bias current for the nMOS source follower transistor 144. The pull-up line 158 may be coupled to a pMOS current source 96 in the chip 94 as shown in fig. 3. Current mirror 146 may include

transistors

166 and 168. The output node 148 of the level shifter (e.g., coupled to the source of the transistor 144) may output a shifted reset control signal RST'. For example, the reset control signal may be shifted from an input voltage (RST) of 0.8V to an output voltage (RST') of 0.2V.

To prevent the reset signal from shifting to a high logic level (sometimes referred to as high, logic level high, logic high, etc.), the bias current may be reduced while the reset signal is high. When the reset signal is high, transistor 150 (which receives the shifted reset signal RST' at its gate terminal) may be asserted. Asserting transistor 150 increases transistor 164 (both its gate and drain coupled to pull-up line 158 through transistors 154 and 150) to the current from pull-up line 158. Increasing transistor 164 decreases the reference current provided to the current mirror and correspondingly decreases the bias current applied to source follower transistor 144.

The amount by which the control signal RST is shifted may be proportional to the reference current provided to the current mirror. Therefore, reducing the reference current when RST is high causes RST to shift less at a logic high level than at a logic low level (sometimes referred to as a low level, a low logic level, a logic level low, etc.). In one example, the voltage of the control signal may shift by more than 0.2V, more than 0.3V, more than 0.4V, more than 0.5V, more than 0.6V, between 0.4V and 0.8V, or between 0.5 and 0.7V when at a logic low level. When at a logic high level, the voltage of the control signal may shift less than 0.1V, less than 0.2V, less than 0.3V, less than 0.6V, between 0.001V and 0.2V, or between 0.05 and 0.1V.

Transistor 152 may be interposed at a bias voltage supply terminal 156 (which provides a bias voltage V)_AAPIX) And transistor 144. The transistor 154 may be interposed between the upper pull line 158 and the current mirror 146.

Transistors

152 and 154 may receive a row select control signal RS at their gate terminals. Accordingly, the

transistors

152 and 154 may function as enable transistors that prevent the level shifter from operating unless a row control signal associated with the level shifter is asserted.

Level shifter 142 may also include a transistor 170 for powering down the level shifter. Thus, transistor 170 may sometimes be referred to as a power down transistor 170.

The example of shifting the reset control signal RST in fig. 7 is merely exemplary. Any desired control signal (e.g., TX) may be provided to the gate terminal of transistor 144, thus shifting any desired control signal using a level shifter. The shifted control signal (e.g., RST') may be provided to additional verify circuit blocks (e.g., the latch circuits of FIG. 6) within the verify circuit.

In general, an image sensor may include a verification circuit. The verification circuit may be formed of nMOS transistors, and may be formed in the first chip 92. The verification circuit may include a level shifter configured to shift a control signal (e.g., a reset control signal) to a low level closer to the ground potential. At high levels, the level shifter may not shift the control signal as much as at low levels. The shifted control signals may be provided to additional verify circuitry to ensure proper operation of the imaging pixels. The verification circuitry may also include latch circuitry that tests whether the reset control signal (RST) and the transfer control signal (TX) are asserted in proper order. In one example, the latch circuit may receive the shifted reset control signal RST' from the level shifter. To ensure that the latch circuit is powered on in the set state, a pull-up line may be coupled to the S node of the latch and a pull-down transistor may be coupled to the R node of the latch. The pull-down transistor may receive an inverted row control signal from the inverter to ensure that the pull-down transistor is asserted when the row control signal is de-asserted. By including a circuit that always powers on the latch circuit in the set state, proper verify operation can be ensured.

In various embodiments, an image sensor may include a first substrate and a second substrate; an array of imaging pixels in the first substrate, each imaging pixel having a photodiode; row control circuitry in the second substrate, the row control circuitry configured to provide row control signals to the array of imaging pixels; and a verification circuit in the first substrate, the verification circuit receiving the row control signal from the row control circuit. The first substrate may include a plurality of n-channel metal oxide semiconductor transistors and may not include any p-channel metal oxide semiconductor transistors.

The image sensor may also include a current source coupled to the verification circuit. The current source may be a p-channel metal oxide semiconductor current source. The p-channel metal oxide semiconductor current source may be formed in the second substrate. The verification circuitry may include a plurality of dummy pixels, each dummy pixel may have a respective verification circuitry portion, and each dummy pixel may receive a row select control signal from the row control circuitry that selectively enables the respective verification circuitry portion of the dummy pixel. Only the verify circuit portion of the dummy pixel enabled by the row select control signal may receive current from the current source.

Each imaging pixel may include a floating diffusion region, a transfer transistor coupled between a photodiode and the floating diffusion region, a source follower transistor coupled to the floating diffusion region, a reset transistor coupled to the floating diffusion region, and a row select transistor coupled to the source follower transistor. The plurality of dummy pixels may include at least one column of dummy pixels, and each column of the at least one column of dummy pixels may be coupled to a corresponding column output line. Each column output line may be coupled to a respective analog-to-digital converter.

In various embodiments, an image sensor may include a first substrate and a second substrate, an array of imaging pixels arranged in a plurality of rows and columns in the first substrate, a plurality of dummy pixels arranged in a plurality of rows and at least one column in the first substrate, and row control circuitry in the second substrate. The row control circuitry may be configured to provide respective control signals to each row of imaging pixels and each row of dummy pixels, the control signals may selectively enable the verification circuitry in each dummy pixel, and the first substrate may not include any p-channel metal-oxide-semiconductor transistors.

The image sensor may also include a current source coupled to the verify circuit in each of the first column of virtual pixels. The current source may include at least one p-channel metal oxide semiconductor transistor. The current source may be formed in the second substrate. Only the verify circuits that have been enabled by the control signal may receive current from the current source. Each imaging pixel may include a floating diffusion region, a transfer transistor coupled between a photodiode and the floating diffusion region, a source follower transistor coupled to the floating diffusion region, a reset transistor coupled to the floating diffusion region, and a row select transistor coupled to the source follower transistor. The gate of the row select transistor of each imaging pixel may receive a control signal from a row control circuit.

In various embodiments, an image sensor may include a first substrate including an imaging pixel array including a plurality of n-channel metal oxide semiconductor transistors and not including any p-channel metal oxide semiconductor transistors, and a second substrate; and a verification circuit including a plurality of n-channel metal oxide semiconductor transistors and not including any p-channel metal oxide semiconductor transistors, and the second substrate overlapping the first substrate and including a current source and a row control circuit in the second substrate, the current source coupled to the verification circuit and including at least one p-channel metal oxide semiconductor transistor. The row control circuit may be configured to provide a first row control signal to a first row of imaging pixels in the imaging pixel array and a first portion of the verification circuit, and the first row control signal may control whether the first portion of the verification circuit receives current from the current source.

A first row control signal may be provided to the gate of the row select transistor in each of the first row of imaging pixels. The row control circuit may be configured to provide a second row control signal to the first row of imaging pixels and the first portion of the verification circuit, and may provide the second row control signal to the gate of the transfer transistor in each of the first row of imaging pixels. The row control circuit may be configured to provide a third row control signal to the first row of imaging pixels and the first portion of the verification circuit, and may provide the third row control signal to the gate of the reset transistor in each of the first row of imaging pixels.

In various embodiments, an image sensor may include an imaging pixel array and a verification circuit configured to test operation of the imaging pixel array. The verification circuit may have an SR latch circuit associated with a given row of imaging pixels, and the SR latch circuit may include a first node coupled to a pull-up bias line configured to ensure that the SR latch circuit begins in a set state.

The first node may be an S node of the SR latch circuit, and the SR latch circuit may include an R node. The SR latch circuit can also include a first transistor coupled to the R node, the first transistor having a gate that receives a transfer control signal associated with a given row of imaging pixels; and a second transistor coupled to the S node, the second transistor having a gate that receives a reset control signal associated with a given row of imaging pixels. The SR latch circuit may be configured to verify whether the reset control signal and the transfer control signal are asserted in the correct order. The SR latch circuit may be formed in a first substrate, the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors, and the pull-up bias line may be coupled to a pMOS current source formed in a second substrate. The SR latch circuit can further include a pull-down transistor coupled to the R node and configured to ensure that the SR latch circuit begins in a set state; and an inverter that receives the row select control signal associated with a given row of imaging pixels and outputs an inverted version of the row select control signal. The pull-down transistor may have a gate that receives an inverted version of the row select control signal.

In various embodiments, an image sensor may include an array of imaging pixels and a verification circuit configured to test operation of a given row of imaging pixels. The verification circuit may include an inverter that receives a row select control signal associated with a given row of imaging pixels and outputs an inverted version of the row select control signal; and an SR latch circuit associated with a given row of imaging pixels. The SR latch circuit may include a first node coupled to a pull-down transistor, and the pull-down transistor may have a gate that receives an inverted version of a row select control signal.

The SR latch circuit can also include a first transistor coupled to the R node, the first transistor having a gate that receives a transfer control signal associated with a given row of imaging pixels; and a second transistor coupled to the S node, the second transistor having a gate that receives a reset control signal associated with a given row of imaging pixels. The SR latch circuit may be configured to verify whether the reset control signal and the transfer control signal are asserted in the correct order. The S node may be coupled to a pull-up bias line, the pull-down transistor may be configured to hold the R node low when the SR latch circuit is not in use, and the pull-up bias line may be configured to hold the S node high when the SR latch circuit is not in use. The SR latch circuit may be formed in a first substrate, and the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors.

In various embodiments, an image sensor may include an imaging pixel array including a given row of imaging pixels; row control circuitry configured to provide control signals to a given row of imaging pixels; and a verification circuit configured to test operation of the imaging pixel array. The verification circuit may include a level shifter configured to receive the control signal, shift a voltage of the control signal by a first amount when the control signal is at a low level, and shift the voltage of the control signal by a second amount less than the first amount when the control signal is at a high level.

The control signal received by the level shifter may be a reset control signal associated with a given row of imaging pixels. The level shifter may include a source follower transistor, which may have a gate receiving the control signal, and a drain outputting a shifted version of the control signal based on the bias current. The level shifter may also include a current mirror that provides a bias current for the source follower transistor. The current mirror may be fed by a reference current provided by a pull-up bias line. The level shifter may further include a first transistor coupled to the pull-up bias line in parallel with the current mirror; and a second transistor coupled between the pull-up bias line and the first transistor and having a gate that receives a shifted version of the control signal. The level shifter may be formed in a first substrate, and the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors.

According to one embodiment, an image sensor may include an imaging pixel array and a verification circuit configured to test operation of the imaging pixel array. The verification circuit may have an SR latch circuit associated with a given row of imaging pixels, and the SR latch circuit may include a first node coupled to a pull-up bias line configured to ensure that the SR latch circuit begins in a set state.

According to another embodiment, the first node may be an S node of the SR latch circuit, and the SR latch circuit may include an R node.

According to another embodiment, the SR latch circuit can further include a first transistor coupled to the R node, wherein the first transistor has a gate that receives a transfer control signal associated with a given row of imaging pixels; and a second transistor coupled to the S node, wherein the second transistor has a gate that receives a reset control signal associated with a given row of imaging pixels.

According to another embodiment, the SR latch circuit may be configured to verify whether the reset control signal and the transfer control signal are asserted in the correct order.

According to another embodiment, the SR latch circuit may be formed in a first substrate, the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors, and the pull-up bias line may be coupled to a pMOS current source formed in a second substrate.

According to another embodiment, the SR latch circuit may include a pull-down transistor coupled to the R node and configured to ensure that the SR latch circuit begins in a set state.

According to another embodiment, the image sensor may further include an inverter that receives the row select control signal associated with a given row of imaging pixels and outputs an inverted version of the row select control signal. The pull-down transistor may have a gate that receives an inverted version of the row select control signal.

According to one embodiment, an image sensor may include an array of imaging pixels and a verification circuit configured to test operation of a given row of imaging pixels. The verification circuit may include an inverter that receives a row select control signal associated with a given row of imaging pixels and outputs an inverted version of the row select control signal; and an SR latch circuit associated with a given row of imaging pixels. The SR latch circuit may include a first node coupled to a pull-down transistor, and the pull-down transistor may have a gate that receives an inverted version of a row select control signal.

According to another embodiment, the first node may be an R node of the SR latch circuit, and the SR latch circuit may further include an S node.

According to another embodiment, the SR latch circuit further comprises a first transistor coupled to the R node, wherein the first transistor has a gate that receives a transfer control signal associated with a given row of imaging pixels; and a second transistor coupled to the S node, wherein the second transistor has a gate that receives a reset control signal associated with a given row of imaging pixels.

According to another embodiment, the S node may be coupled to a pull-up bias line, the pull-down transistor may be configured to hold the R node low when the SR latch circuit is not in use, and the pull-up bias line may be configured to hold the S node high when the SR latch circuit is not in use.

According to another embodiment, the SR latch circuit may be formed in a first substrate, and the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors.

According to one embodiment, an image sensor may include an imaging pixel array including a given row of imaging pixels; row control circuitry configured to provide control signals to a given row of imaging pixels; and a verification circuit configured to test operation of the imaging pixel array. The verification circuit may include a level shifter configured to receive the control signal, shift a voltage of the control signal by a first amount when the control signal is at a low level, and shift the voltage of the control signal by a second amount less than the first amount when the control signal is at a high level.

According to another embodiment, the control signal received by the level shifter may be a reset control signal associated with a given row of imaging pixels.

According to another embodiment, the level shifter may include a source follower transistor, the source follower transistor may have a gate receiving the control signal, and the source follower transistor may have a drain outputting a shifted version of the control signal based on the bias current.

According to another embodiment, the level shifter may further include a current mirror to provide a bias current for the source follower transistor.

According to another embodiment, the current mirror may be fed by a reference current provided by a pull-up bias line.

According to another embodiment, a level shifter may include a first transistor coupled to a pull-up bias line in parallel with a current mirror; and a second transistor coupled between the pull-up bias line and the first transistor. The second transistor may have a gate that receives a shifted version of the control signal.

According to another embodiment, the level shifter may be formed in a first substrate, and the first substrate may include a plurality of n-channel metal oxide semiconductor (nMOS) transistors and may not include any p-channel metal oxide semiconductor (pMOS) transistors.

The foregoing is considered as illustrative only of the principles of the invention, and numerous modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The above-described embodiments may be implemented individually or in any combination.

Claims

1. An image sensor, comprising:

an imaging pixel array; and

a verify circuit configured to test operation of the array of imaging pixels, wherein the verify circuit has an SR latch circuit associated with a given row of imaging pixels, and wherein the SR latch circuit includes a first node coupled to a pull-up bias line configured to ensure that the SR latch circuit begins in a set state.

2. The image sensor of claim 1, wherein the first node is an S node of the SR latch circuit, wherein the SR latch circuit comprises an R node, and wherein the SR latch circuit further comprises:

a first transistor coupled to the R node, wherein the first transistor has a gate that receives a transfer control signal associated with the given row of imaging pixels; and

a second transistor coupled to the S-node, wherein the second transistor has a gate that receives a reset control signal associated with the given row of imaging pixels, wherein the SR latch circuit is configured to verify whether the reset control signal and the transfer control signal are asserted in the correct order, wherein the SR latch circuit is formed in a first substrate, wherein the first substrate includes a plurality of n-channel metal oxide semiconductor (NMOS) transistors and does not include any p-channel metal oxide semiconductor (pMOS) transistors, and wherein the pull-up bias line is coupled to a pMOS current source formed in a second substrate.

3. The image sensor of claim 2, wherein the first node is an S node of the SR latch circuit, wherein the SR latch circuit comprises an R node, wherein the SR latch circuit further comprises a pull-down transistor coupled to the R node and configured to ensure that the SR latch circuit starts in the set state, and wherein the image sensor further comprises:

an inverter receiving a row select control signal associated with the given row of imaging pixels and outputting an inverted version of the row select control signal, wherein the pull-down transistor has a gate receiving the inverted version of the row select control signal.

4. An image sensor, comprising:

an imaging pixel array; and

a verification circuit configured to test operation of a given row of imaging pixels, wherein the verification circuit comprises:

an inverter that receives a row select control signal associated with the given row of imaging pixels and outputs an inverted version of the row select control signal; and

an SR latch circuit associated with the given row of imaging pixels, wherein the SR latch circuit comprises a first node coupled to a pull-down transistor, and wherein the pull-down transistor has a gate that receives the inverted version of the row select control signal.

5. The image sensor of claim 4, wherein the first node is an R node of the SR latch circuit, wherein the SR latch circuit further comprises an S node, and wherein the SR latch circuit further comprises:

a second transistor coupled to the S-node, wherein the second transistor has a gate that receives a reset control signal associated with the given row of imaging pixels, wherein the SR latch circuit is configured to verify whether the reset control signal and the transfer control signal are asserted in a correct order.

6. The image sensor of claim 4, wherein the first node is an R node of the SR latch circuit, wherein the SR latch circuit further comprises an S node, wherein the S node is coupled to a pull-up bias line, wherein the pull-down transistor is configured to hold the R node low when the SR latch circuit is not in use, and wherein the pull-up bias line is configured to hold the S node high when the SR latch circuit is not in use.

7. The image sensor of claim 4, wherein the SR latch circuit is formed in a first substrate, and wherein the first substrate comprises a plurality of n-channel metal oxide semiconductor (nMOS) transistors and does not comprise any p-channel metal oxide semiconductor (pMOS) transistors.

8. An image sensor, comprising:

an imaging pixel array comprising a given row of imaging pixels

Row control circuitry configured to provide control signals to the given row of imaging pixels; and

a verification circuit configured to test operation of the array of imaging pixels, wherein the verification circuit includes a level shifter configured to:

receiving the control signal;

shifting a voltage of the control signal by a first amount when the control signal is at a low level; and

shifting the voltage of the control signal by a second amount less than the first amount when the control signal is at a high level.

9. The image sensor of claim 8, wherein the level shifter comprises a source follower transistor, wherein the source follower transistor has a gate that receives the control signal, wherein the source follower transistor has a drain that outputs a shifted version of the control signal based on a bias current, wherein the level shifter further comprises a current mirror that provides the bias current for the source follower transistor, wherein the current mirror is fed by a reference current provided by a pull-up bias line, and wherein the level shifter further comprises:

a first transistor coupled to the pull-up bias line in parallel with the current mirror; and

a second transistor coupled between the pull-up bias line and the first transistor, wherein the second transistor has a gate that receives the shifted version of the control signal.

10. The image sensor of claim 8, wherein the level shifter is formed in a first substrate, and wherein the first substrate comprises a plurality of n-channel metal oxide semiconductor (nMOS) transistors and does not comprise any p-channel metal oxide semiconductor (pMOS) transistors.