CN111510261B - Signal processing method, device, equipment and computer readable storage medium - Google Patents

Signal processing method, device, equipment and computer readable storage medium Download PDF

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CN111510261B
CN111510261B CN201910090486.5A CN201910090486A CN111510261B CN 111510261 B CN111510261 B CN 111510261B CN 201910090486 A CN201910090486 A CN 201910090486A CN 111510261 B CN111510261 B CN 111510261B
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sequence
target
preamble
interleaver
leader
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CN111510261A (en
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马文平
甄少华
罗炼飞
任斌
赵铮
邢艳萍
林祥利
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Datang Mobile Communications Equipment Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
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Abstract

The invention discloses a signal processing method, a signal processing device, signal processing equipment and a computer readable storage medium, relates to the technical field of communication, and aims to solve the problem that the prior art cannot ensure the detection performance of a leader sequence and enhance the leader capacity at the same time. The method comprises the following steps: generating a ZC sequence according to a root sequence number, wherein the root sequence number is related to the window length of a single user; generating a first leader sequence according to the ZC sequence; determining a target leader sequence and a target interleaver according to the first leader sequence; interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence; sending the interleaved target leader sequence to network side equipment; different terminals respectively use the same target interleaver to interleave different target preamble sequences. The embodiment of the invention can ensure the detection performance of the leader sequence and enhance the leader capacity at the same time.

Description

Signal processing method, device, equipment and computer readable storage medium
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a signal processing method, an apparatus, a device, and a computer-readable storage medium.
Background
In a high-speed scenario of an LTE (Long Term Evolution) system, a preamble sequence used in a random access process is a ZC (Zadoff-Chu) sequence.
Under the condition of high-speed movement of a UE (User Equipment), autocorrelation of a ZC sequence is seriously damaged by large Doppler frequency offset. And because the bandwidth occupied by each subcarrier in LTE is 1.25kHz and is far less than the subcarrier bandwidth occupied by data by 15kHz, the leader sequence is particularly sensitive to frequency offset and phase noise. Therefore, when there is a large frequency offset, the detection performance of the random access preamble sequence may be seriously degraded.
Aiming at the problem of large Doppler frequency offset generated by a 5G mobile communication system in a high-speed mobile environment, a method for generating a new limit set by circularly shifting a leader sequence is provided to overcome the influence of frequency offset. However, this scheme cannot achieve a large preamble capacity.
Therefore, it is necessary to provide a scheme for ensuring the detection performance of the preamble sequence and improving the preamble capacity.
Disclosure of Invention
Embodiments of the present invention provide a signal processing method, an apparatus, a device, and a computer-readable storage medium, so as to solve the problem that the prior art cannot guarantee the detection performance of a preamble sequence and enhance the preamble capacity at the same time.
In order to solve the technical problem, the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a signal processing method, applied to a terminal, including:
generating a ZC sequence according to a root sequence number, wherein the root sequence number is related to the window length of a single user;
generating a first leader sequence according to the ZC sequence;
determining a target leader sequence and a target interleaver according to the first leader sequence;
interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence;
sending the interleaved target leader sequence to network side equipment;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein, the generating of the ZC sequence according to the root sequence number comprises:
acquiring a cyclic shift parameter;
determining a root sequence number corresponding to the cyclic shift parameter;
and generating a ZC sequence according to the serial number of the root sequence.
Wherein the acquisition cyclic shift parameter is determined by the following formula:
Figure BDA0001963120030000021
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000022
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
Wherein the generating a first preamble sequence according to the ZC sequence comprises:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu，v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(n) denotes a first preamble sequence,0≤n≤NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
Wherein the determining a target preamble sequence and a target interleaver according to the first preamble sequence comprises:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
Wherein the selecting a target preamble sequence from the second preamble sequence and a target interleaver from the interleavers comprises:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
Wherein, the sending the interleaved target preamble sequence to the network side device includes:
mapping the interleaved target leader sequence to a frequency domain through resources;
modulating the signal mapped to the frequency domain through Orthogonal Frequency Division Multiplexing (OFDM) to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
In a second aspect, an embodiment of the present invention provides a signal processing method, applied to a network side device, including:
generating an interleaver and a deinterleaver;
receiving a first leader sequence sent by a terminal;
sending the interleaver and a second preamble sequence to the terminal, wherein the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
receiving an interleaved target leader sequence sent by the terminal;
deinterleaving the target preamble sequence using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein the sending the interleaver and the second preamble sequence to the terminal includes:
grouping the first leader sequence to obtain a second leader sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
In a third aspect, an embodiment of the present invention provides a communication device, including: a transceiver, a memory, a processor, and a computer program stored on the memory and executable on the processor;
the processor is used for reading the program in the memory and executing the following processes:
generating a ZC sequence according to a root sequence number, wherein the root sequence number is related to the window length of a single user;
generating a first leader sequence according to the ZC sequence, and sending the first leader sequence to network side equipment;
determining a target leader sequence and a target interleaver according to the first leader sequence;
interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence;
the transceiver is configured to send the interleaved target preamble sequence to a network side device;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
acquiring a cyclic shift parameter;
determining a root sequence number corresponding to the cyclic shift parameter;
and generating a ZC sequence according to the serial number of the root sequence.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
determining the acquisition cyclic shift parameter by the following formula:
Figure BDA0001963120030000041
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000051
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu,v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
mapping the interleaved target leader sequence to a frequency domain through resources;
carrying out OFDM modulation on the signal mapped to the frequency domain to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
In a fourth aspect, an embodiment of the present invention provides a communication device, including: a transceiver, a memory, a processor, and a computer program stored on the memory and executable on the processor;
the processor is used for reading the program in the memory and executing the following processes:
generating an interleaver and a deinterleaver;
receiving a first leader sequence sent by a terminal;
sending the interleaver and a second preamble sequence to the terminal, wherein the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
receiving an interleaved target leader sequence sent by the terminal;
deinterleaving the target preamble sequence using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein the processor is further configured to read the program in the memory and execute the following processes:
grouping the first leader sequence to obtain a second leader sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
In a fifth aspect, an embodiment of the present invention provides a signal processing apparatus, which is disposed in a terminal, and includes:
a first generating module, configured to generate a ZC sequence according to a root sequence number, where the root sequence number is related to a window length of a single user;
a second generating module, configured to generate a first preamble sequence according to the ZC sequence, and send the first preamble sequence to a network side device;
a determining module, configured to determine a target preamble sequence and a target interleaver according to the first preamble sequence;
an obtaining module, configured to interleave the target preamble sequence by using the target interleaver, and obtain an interleaved target preamble sequence;
a sending module, configured to send the interleaved target preamble sequence to a network side device;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein the first generating module comprises:
the acquisition submodule is used for acquiring cyclic shift parameters;
the determining submodule is used for determining a root sequence number corresponding to the cyclic shift parameter;
and the generating submodule is used for generating the ZC sequence according to the serial number of the root sequence.
In a sixth aspect, an embodiment of the present invention provides a signal processing apparatus, which is disposed in a network side device, and includes:
a generating module for generating an interleaver and a deinterleaver;
a first receiving module, configured to receive a first preamble sequence sent by a terminal;
a sending module, configured to send the interleaver and a second preamble sequence to the terminal, where the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
a second receiving module, configured to receive the interleaved target preamble sequence sent by the terminal;
a processing module, configured to perform deinterleaving on the target preamble sequence by using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein the sending module comprises:
a grouping submodule, configured to group the first preamble sequence to obtain the second preamble sequence;
a sending submodule, configured to send the interleaver and the second preamble sequence to the terminal.
In a seventh aspect, an embodiment of the present invention provides a computer-readable storage medium for storing a computer program, where the computer program, when executed by a processor, implements the steps in the method according to the first aspect; alternatively, the computer program realizes the steps in the method according to the second aspect when executed by a processor.
In the embodiment of the invention, the selection of the root sequence number of the ZC sequence is limited, so that the offset positions of the related peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. Meanwhile, different terminals can interleave different target preamble sequences by using the same target interleaver, so that the preamble capacity is enhanced.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a flowchart of a signal processing method according to an embodiment of the present invention;
fig. 2 is a second flowchart of a signal processing method according to an embodiment of the present invention;
fig. 3 is a flowchart of a preamble capacity enhancement method based on interleaving according to an embodiment of the present invention;
fig. 4 is a process diagram of a preamble capacity enhancement method based on interleaving according to an embodiment of the present invention;
fig. 5 is one of the structural diagrams of a signal processing apparatus provided by the embodiment of the present invention;
fig. 6 is a second structural diagram of a signal processing apparatus according to an embodiment of the present invention;
fig. 7 is one of the schematic diagrams of a communication device provided by the embodiment of the present invention;
fig. 8 is a second schematic diagram of a communication device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a signal processing method provided by an embodiment of the present invention, and is applied to a terminal. As shown in fig. 1, the method comprises the following steps:
step 101, generating a ZC sequence from a root sequence number, wherein the root sequence number is related to a window length of a single user.
In this step, a cyclic shift parameter is obtained, a root sequence number corresponding to the cyclic shift parameter is determined, and then a ZC sequence is generated according to the root sequence number.
Specifically, the cyclic shift parameter is determined by the following formula:
Figure BDA0001963120030000081
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence.
Generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000082
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
And 102, generating a first leader sequence according to the ZC sequence.
Specifically, in this step, a preamble sequence is generated by cyclic shift according to the root sequence number using the following formula;
xu，v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
And 103, determining a target leader sequence and a target interleaver according to the first leader sequence.
In this step, the first preamble sequence may be transmitted to the network side device. Then, a second leader sequence allocated by the network side equipment according to the first leader sequence is obtained, an interleaver allocated by the network side equipment is obtained, a target leader sequence is selected from the second leader sequence, and a target interleaver is selected from the interleaver.
When the target leader sequence is selected, a leader sequence subset is generated according to the second leader sequence, the target leader sequence is selected from the leader sequence subset, and a random access request is sent to the network side equipment. In selecting a target interleaver, a target interleaver is selected from the interleavers. The selection target preamble sequence may be randomly selected, and the selection target interleaver may also be randomly selected.
And 104, interleaving the target preamble sequence by using the target interleaver to obtain an interleaved target preamble sequence.
Different terminals respectively use the same target interleaver to interleave different target preamble sequences. In this step, the interleaved target preamble sequence is mapped to a Frequency domain by a resource, and then, a signal mapped to the Frequency domain is modulated by OFDM (Orthogonal Frequency Division Multiplexing) to generate a time domain symbol. And then constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
And 105, sending the interleaved target preamble sequence to network side equipment.
In the embodiment of the invention, the selection of the root sequence number of the ZC sequence is limited, so that the offset positions of the related peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. Meanwhile, different terminals can interleave different target preamble sequences by using the same target interleaver, so that the preamble capacity is enhanced.
As shown in fig. 2, a signal processing method according to an embodiment of the present invention is applied to a network device, and includes:
step 201, generating an interleaver and a deinterleaver.
The network side device can generate a plurality of pairs of different interleavers and deinterleavers by using the existing method.
Step 202, receiving a first preamble sequence sent by the terminal.
Step 203, sending the interleaver and a second preamble sequence to the terminal, where the second preamble sequence is obtained according to the first preamble sequence sent by the terminal.
Specifically, in this step, the first preamble sequence is grouped to obtain the second preamble sequence, and the interleaver and the second preamble sequence are sent to the terminal.
Wherein the second preamble sequence is an arbitrary set of grouped preamble sequences.
And step 204, receiving the interleaved target preamble sequence sent by the terminal.
Step 205, deinterleaving the target preamble sequence by using the deinterleaver.
Different terminals respectively use the same target interleaver to interleave different target preamble sequences.
In the embodiment of the invention, the selection of the root sequence number of the ZC sequence is limited, so that the offset positions of the related peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. Meanwhile, different terminals can interleave different target preamble sequences by using the same target interleaver, so that the preamble capacity is enhanced.
Following the LTE standard, the UE initiates a content-based random access procedure. By selecting the preamble signature, no content access is started by one dedicated signature assigned from the eNodeB. Each cell has 64 PRACH (Physical Random Access Channel) signatures. Based on the ZC sequences, a preamble sequence set is established by cyclic shift. The cyclically shifted sequences will then form a Single-carrier Frequency-Division Multiple Access (SC-FDMA) signal with a specified Cyclic Prefix CP (CP) and Guard Time GT (Guard Time, GT), the length of CP and GT depending on the preamble format.
Figure BDA0001963120030000101
xu(N) denotes a ZC sequence, u denotes a parameter, is reciprocal to the sequence length, N is a constant, N isZCIs the length of the ZC sequence.
When a user initiates random access, the higher layers instruct the UE to select a root sequence for generating a preamble, which is broadcast as part of the system information of the network. Generating a signal having a length N by cyclic shift based on the u-th ZC sequenceZC-1 random access preamble of zero correlation zone.
xu,v(n)＝xu((n+Cv)mod NZC) (2)
Wherein x isu,v(n) denotes a ZC sequence after cyclic shift, Cv denotes a cyclic shift, and (n + C)v)mod NZCIs a modular operation, representing the use of n and CvSum to NZCA modulo operation is performed and the parameters may take different values depending on the specified preamble format.
Figure BDA0001963120030000111
s (t) represents a transmitted time-continuous random access signal, k and n are constants, fRA(t-TCP) Represents T-TCPSubcarrier spacing at time, where T denotes the transmission time signal, TCPTime slots, T, of sequence prefixesSEQIndicating the time gap, N, of the signal in the preamble sequenceZCIs the length of the PRACH sequence, betaPRACHIs an amplitude scaling factor, a variable
Figure BDA0001963120030000112
Is a fixed offset, constant, determining the frequency domain position of the random access preamble within the physical resource blockk0Depending on the preamble format and system parameters, Δ fRAIs the subcarrier spacing, factor, of the random access preamble
Figure BDA0001963120030000113
Is the subcarrier spacing of uplink data Δ fDATAAnd Δ fRAThe ratio of (a) to (b).
In LTE system,. DELTA.fDATA15kHz for uplink data, Δ fRA1.25kHz for LTE preamble format 0-3, Frequency Division Duplex (FDD) system, afRASignal for uplink data LTE preamble format 4 at 7.5kHz, Time Division Duplex (TDD) system.
When the frequency deviation deltaf satisfies deltaf>ΔfRAI.e. Δ f ═ K · Δ fRA+ δ f, where K is an integer greater than 1, δ f denotes a fractional frequency offset, 0<δf<ΔfRAThe ZC sequence generated at the receiver can be expressed as:
Figure BDA0001963120030000114
in the formula, Δ f is the frequency offset, δ f represents the fractional frequency offset, TSEQRepresenting time gaps in the preamble sequence.
Wherein the frequency offset is assumed to be Δ f<ΔfRA,xu(n, Δ f); it can be further simplified as:
Figure BDA0001963120030000115
Figure BDA0001963120030000121
in the formula (5), phiuIndicating the exponential coefficient with e as the base. From this formula it can be observed that false peaks of correlation correspond to false alarms. Assuming that the number of users of a cell is N, the length of a ZC sequenceIs NZCThen the maximum search window range for a single user can be expressed as
Figure BDA0001963120030000122
If the frequency offset is Δ f, position CVWill be at the correlation peak in
Figure BDA0001963120030000123
A false peak is generated. Thus, the maximum shift of the correlation peak can be expressed as
Figure BDA0001963120030000124
And the range of the correlation peak shift is in the window Cv-dmax,Cv+dmax]And (4) the following steps.
Considering the effect of propagation delay, the search range of the correction is [ C ]v-dmax,Cv+dmax+NCS]. Therefore, the preamble peak offset range has a length Wpeak＝2dmax+NCS. W should be satisfied if the cell has a predefined upper bound on the number of users N accessedpeakThe requirement of less than or equal to W is met. Therefore, the temperature of the molten metal is controlled,
Figure BDA0001963120030000125
NCSbased on a window length parameter in a ZC root sequence leader sequence; w represents the maximum search window range for a single user.
Here, it is assumed that each base station may have a predetermined maximum number of users per cell and a maximum supported frequency offset Δ f. For high frequency channel scenarios, the base station has planned coverage and deployment of each cell in the channel. Therefore, it is feasible to assume that each base station has a predefined N and Δ f according to the cell radius to ensure a low false alarm probability. Thus, duRepresents a cyclic shift parameter whose value satisfies equation (6) and can be calculated and stored in the base station before the user transmits a random access.
Thus, according to the formula
Figure BDA0001963120030000126
Can calculate the correspondence duIs determined. By using a specific root sequence number u, a ZC sequence can be generated according to equation (1).
To accomplish this, in an embodiment of the present invention, a search window of width W is usedpeak＝2dmax+NCS. The success of the detection requires that there is no overlap between all windows. Based on this requirement, the cyclic shift of N users can be calculated:
Cv＝2(n-1)dmax+(n-1)NCS (7)
in the formula (d)maxMaximum shift of correlation peak, CvFor cyclic shift, n is a constant.
With the specific root sequence number, a preamble sequence may be generated by cyclic shift according to equation (2). Ensuring preamble peak offset is centered at 2dmax+NCSWithin the range of (1).
For performing multi-user detection, the width appended together is 2dmax+NCSWill generate disparate correlation metrics within the search window.
The above method is computationally simple, and supports a single window to detect all false peaks. The traditional method can only detect the low frequency deviation delta f less than or equal to delta fRAThe false peak value of (2) will increase the false alarm probability, and the higher doppler shift will cause the leakage of the correlation peak value outside the detection window, increasing the error rate. In this embodiment, by limiting the choice of root sequence numbers for ZC sequences, the offset locations of the correlation peaks are concentrated within a single search box, counteracting most doppler shifts.
On the basis, in the design of the preamble signal, a preamble capacity enhancement method based on interleaving is combined.
A preamble sequence generating and transmitting method based on interleaving, that is, a function of multiplexing one preamble sequence for multiple users is realized by interleaving the generated preamble sequence with an interleaver, and the process is shown in fig. 3. The basic process is as follows: before transmission starts, the gNB generates M (M is a positive integer) pairs of interleavers and deinterleavers different from each other, and then the gNB allocates available preamble sequences and interleavers to the respective UEs. And the UE generates a leader sequence and interleaves the leader sequence through an interleaver to obtain the interleaved leader sequence. And the UE sends the interleaved preamble sequence to the gNB through the PRACH. The gNB deinterleaves the received preamble sequence and then detects the preamble sequence. In the above procedure, the UE enhances the preamble capacity by multiplexing the same preamble sequence using different interleavers.
Fig. 4 is a simple diagram of the method, which shows the process of multiplexing a preamble sequence M times by using the method.
As can be seen from FIG. 4, the UE has M interleavers I1，I2,…,IMFor 1 leader sequence SpreInterleaving is performed to generate M multiplexing leading sequences. In the figure, the UE has M interleavers I1，I2,…,IMFor 1 leader sequence SpreInterweaving to generate M multiplex leading sequences SI,1,SI,2,…,SI,MAnd sending the data to gNB to respectively correspond to M user U1,U2,…,UMIn which S isI,m≠SI,nM ≠ n. And then the gNB deinterleaves the received leader sequence to complete the leader sequence detection process.
Assuming that the length of the ZC sequence is 839 and the root index is 68, the interleaver selects a secondary congruence mapping interleaver, and a corresponding matched deinterleaver is obtained according to the generated interleaver. The secondary congruence mapping interleaver is realized by the following formula, and for an original sequence ZC sequence s ═ a1,a2,…,aNInterweaving to get s' ═ a1,a2,…,aN}。
Figure BDA0001963120030000141
When the ZC sequence is taken as a leader sequence, assuming that the number of sampling points of a sliding window varies from 1 to 1677, when the number of sampling points of the ZC sequence and the time domain convolution operation result of the ZC sequence is 839 at the time of the sliding window transition, a peak with the amplitude of 839 is generated, and the amplitudes of other positions are not higher than 100 and are far smaller than the peak value.
It can be seen from the above that, the capacity enhancement method herein effectively enhances the preamble capacity on the basis of the preamble sequence design method of the embodiment of the present invention. Theoretically, when the preamble sequence length is N, if the interleaver satisfies: (1) the interleaving depth N of the interleaver; (2) the interleavers have good mutual inertia. Then, with this embodiment, it is achieved that 1 preamble sequence is divided by N! Multiplexing of the users.
The specific scheme of preamble sequence design and joint preamble capacity enhancement comprises the following steps:
step 401, according to the formula
Figure BDA0001963120030000142
Can calculate the correspondence duIs determined.
Step 402, by using a specific root sequence number u, may be based on
Figure BDA0001963120030000143
0≤n≤NZC-1 generating a ZC sequence.
Step 403, using the specific root sequence number, can be according to formula xu,v(n)＝xu((n+Cv)mod NZC) The preamble sequence is generated by cyclic shift.
Step 404, adding CP to the preamble sequence and adding GT at the end of the sequence to obtain a complete PRACH sequence.
Step 405, the gNB generates M pairs of interleaver and deinterleaver { (I) which are different from each other1,D1),(I2,D2),…,(IM,DM)}. Design a set of interleavers Γ ═ I1,I2,…,IMThe following two conditions need to be satisfied:
I1,I2,…,IMthe method has good cross correlation so as to ensure the detection performance of the leader sequence;
I1,I2,…,IMas many as possible to further enhance the preamble capacity.
And step 406, the gNB configures the preamble sequence and the PRACH resource for sending the preamble sequence, notifies the UE residing in the cell of the configuration result through a system message, and allocates an available preamble sequence and an interleaver to each UE.
With the ith user UEiFor example, the contention random access procedure includes:
and the gNB receives the preamble sequences generated by the UE and groups all the preamble sequences.
When triggering random access, the UEiDetermining a preamble sequence set according to the size of an L1/L2 message to be transmitted and the size of the path loss, and randomly selecting one interleaver I from M interleavers generated by the gNBmAnd finishing the allocation of the preamble sequence and the interleaver.
Step 407, the UE interleaves the generated preamble sequence with the interleaver to obtain an interleaved preamble sequence. With the ith user UEiFor example, the contention random access procedure includes:
UEigenerating a leader sequence subset P ═ s meeting the network configuration requirements according to the leader sequence allocation result of the gNB1,s2,…,sL}；
UEiRandomly selecting a leader sequence S from Ppre＝{a1,a2,…,aNSending a random access request to the gNB;
UEiusing an interleaver ImTo Spre＝{a1,a2,…,aNInterweaving to obtain the interweaved leading sequence SI,m＝{ai1,ai2,…,aiN}；
And step 408, the UE sends the interleaved preamble sequence to the gNB through the PRACH.
UEiFor the interleaved leader sequence sI,mFirstly mapping to a frequency domain through resources, then generating a time domain symbol through OFDM modulation, and finally constructing a preamble signal S according to a preamble formatI,mAnd then sent to the gNB.
The frequency offset detection range of the PRACH in the current LTE specification in the high-speed cell is [ -1.25kHz, +1.25kHz ], when the frequency offset greatly exceeds the range, the PRACH signal cannot be detected or the PRACH detection performance is reduced, and the use of the restriction set reduces the number of available preamble sequences, which cannot meet the requirements of future users for high speed and high capacity. And the 5G mobile communication system generates larger Doppler frequency offset in a high-speed environment, and a new PRACH cyclic shift scheme is provided in the prior art aiming at the problem so as to support a high-speed scene with the frequency offset as high as +/-2.5 kHz. Because large frequency offset can cause energy of a receiving end correlation function to leak to a plurality of secondary window positions, at least five windows including a main window and a plurality of secondary windows need to be jointly detected, so that the influence caused by Doppler frequency shift can be avoided.
The embodiment of the invention expands the frequency deviation range to 2 times of subcarrier intervals. For the LTE system in the high-speed scenario, research in the prior art still focuses on analyzing the influence of the frequency offset on the LTE system and improving the algorithm of the frequency offset estimation accuracy. However, these methods still perform peak detection based on three detection windows of the LTE standard algorithm, which will limit the maximum doppler shift range and cannot meet the development requirements of increasing high-speed rail and increasing the number of terminals and data rate.
The embodiment of the invention discloses a new leader sequence generation method, which is combined with a capacity enhancement scheme for capacity expansion. By limiting the selection of the root sequence number of the ZC sequence, the offset positions of the correlation peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. This method is computationally simple, and supports a single window to detect all false peaks. The traditional method can only detect the low frequency deviation delta f less than or equal to delta fRAThe false peak value of (2) will increase the false alarm probability, and the higher doppler shift will cause the leakage of the correlation peak value outside the detection window, increasing the error rate.
The new leader sequence is combined with a leader capacity enhancement method based on interleaving, so that the detection performance of the leader sequence can be ensured, and the multiplexing of a plurality of users to the same leader sequence can be supported. The method is simple to realize, compared with four preamble capacity enhancing methods provided in the prior art, the embodiment of the invention is not limited by the design scheme of the preamble signal, can effectively enhance the preamble capacity, and can theoretically realize that 1 preamble sequence is not limited by N!at most! Multiplexing of the users. In addition, the interleaving-based capacity enhancement method can be conveniently combined with other preamble capacity enhancement methods to further enhance the preamble capacity.
Referring to fig. 5, fig. 5 is a structural diagram of a signal processing apparatus according to an embodiment of the present invention, and as shown in fig. 5, the signal processing apparatus includes:
a first generating module 501, configured to generate a ZC sequence according to a root sequence number, where the root sequence number is related to a window length of a single user;
a second generating module 502, configured to generate a first preamble sequence according to the ZC sequence, and send the first preamble sequence to a network side device;
a determining module 503, configured to determine a target preamble sequence and a target interleaver according to the first preamble sequence;
an obtaining module 504, configured to interleave the target preamble sequence by using the target interleaver, and obtain an interleaved target preamble sequence;
a sending module 505, configured to send the interleaved target preamble sequence to a network side device;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Optionally, the first generating module includes: the acquisition submodule is used for acquiring cyclic shift parameters; the determining submodule is used for determining a root sequence number corresponding to the cyclic shift parameter; and the generating submodule is used for generating the ZC sequence according to the serial number of the root sequence.
Optionally, the acquiring cyclic shift parameter is determined by the following formula:
Figure BDA0001963120030000171
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user,NZCindicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000172
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
Optionally, the second generating module 502 includes: the first generation submodule is used for generating a leader sequence by cyclic shift according to the root sequence number by using the following formula; x is the number ofu,v(n)＝xu((n+Cv)mod NZC) (ii) a An adding submodule, configured to add a cyclic prefix CP and a guard time GT to the preamble sequence, and generate the first preamble sequence; wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
Optionally, the determining module 503 includes: a sending submodule, configured to send the first preamble sequence to the network side device; the obtaining submodule is used for obtaining a second leader sequence distributed by the network side equipment according to the first leader sequence and obtaining an interleaver distributed by the network side equipment; a selection sub-module for selecting a target preamble sequence from the second preamble sequence and a target interleaver from the interleaver.
Optionally, the selecting sub-module includes: a generating unit, configured to generate a preamble sequence subset according to the second preamble sequence; a first selecting unit, configured to select a target preamble sequence from the preamble sequence subset, and send a random access request to the network side device; a second selection unit for selecting a target interleaver from the interleavers.
Optionally, the sending module 505 includes: a mapping sub-module, configured to map the interleaved target preamble sequence to a frequency domain through a resource; the modulation submodule is used for modulating the signal mapped to the frequency domain through OFDM to generate a time domain symbol; and the sending submodule is used for constructing a preamble signal according to the time domain symbol and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
The device can implement each process implemented by the terminal in the above method embodiments, and is not described here again to avoid repetition.
In the embodiment of the invention, the selection of the root sequence number of the ZC sequence is limited, so that the offset positions of the related peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. Meanwhile, different terminals can interleave different target preamble sequences by using the same target interleaver, so that the preamble capacity is enhanced.
Referring to fig. 6, fig. 6 is a structural diagram of a signal processing apparatus according to an embodiment of the present invention, and as shown in fig. 6, the signal processing apparatus includes:
a generating module 601, configured to generate an interleaver and a deinterleaver; a first receiving module 602, configured to receive a first preamble sequence sent by a terminal; a sending module 603, configured to send the interleaver and a second preamble sequence to the terminal, where the second preamble sequence is obtained according to a first preamble sequence sent by the terminal; a second receiving module 604, configured to receive an interleaved target preamble sequence sent by the terminal; a processing module 605, configured to perform deinterleaving on the target preamble sequence by using the deinterleaver; different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Optionally, the sending module 603 includes: a grouping submodule, configured to group the first preamble sequence to obtain the second preamble sequence; a sending submodule, configured to send the interleaver and the second preamble sequence to the terminal.
In the embodiment of the invention, the selection of the root sequence number of the ZC sequence is limited, so that the offset positions of the related peaks are concentrated in a single search box, and most Doppler frequency shifts are resisted. Meanwhile, different terminals can interleave different target preamble sequences by using the same target interleaver, so that the preamble capacity is enhanced.
As shown in fig. 7, the communication device of the embodiment of the present invention includes: the processor 700, which is used to read the program in the memory 720, executes the following processes:
generating an interleaver and a deinterleaver; receiving a first leader sequence sent by a terminal; transmitting the interleaver and a second preamble sequence to the terminal through the transceiver 710, wherein the second preamble sequence is obtained according to a first preamble sequence transmitted by the terminal; receiving, by the transceiver 710, the interleaved target preamble sequence sent by the terminal; deinterleaving the target preamble sequence using the deinterleaver; different terminals respectively use the same target interleaver to interleave different target preamble sequences.
A transceiver 710 for receiving and transmitting data under the control of the processor 700.
Where in fig. 7, the bus architecture may include any number of interconnected buses and bridges, with various circuits being linked together, particularly one or more processors represented by processor 700 and memory represented by memory 720. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 710 may be a number of elements including a transmitter and a transceiver providing a means for communicating with various other apparatus over a transmission medium. The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 in performing operations.
The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 in performing operations.
The processor 700 is further configured to read the computer program and perform the steps of grouping the first preamble sequence to obtain the second preamble sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
As shown in fig. 8, the communication device of the embodiment of the present invention includes: the processor 800, which is used to read the program in the memory 820, executes the following processes:
generating a ZC sequence according to a root sequence number, wherein the root sequence number is related to the window length of a single user; generating a first leader sequence according to the ZC sequence; determining a target leader sequence and a target interleaver according to the first leader sequence; interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence; sending the interleaved target preamble sequence to a network side device through a transceiver 810; different terminals respectively use the same target interleaver to interleave different target preamble sequences.
A transceiver 810 for receiving and transmitting data under the control of the processor 800.
Where in fig. 8, the bus architecture may include any number of interconnected buses and bridges, with various circuits being linked together, particularly one or more processors represented by processor 800 and memory represented by memory 820. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 810 may be a number of elements including a transmitter and a receiver that provide a means for communicating with various other apparatus over a transmission medium. The user interface 830 may also be an interface capable of interfacing with a desired device for different user devices, including but not limited to a keypad, a display, a speaker, a microphone, a joystick, etc.
The processor 800 is responsible for managing the bus architecture and general processing, and the memory 820 may store data used by the processor 800 in performing operations.
The processor 800 is further configured to read the computer program and perform the following steps:
acquiring a cyclic shift parameter;
determining a root sequence number corresponding to the cyclic shift parameter;
and generating a ZC sequence according to the serial number of the root sequence.
The processor 800 is further configured to read the computer program and perform the following steps:
determining the acquisition cyclic shift parameter by the following formula:
Figure BDA0001963120030000201
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000202
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
The processor 800 is further configured to read the computer program and perform the following steps:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu，v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
The processor 800 is further configured to read the computer program and perform the following steps:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
The processor 800 is further configured to read the computer program and perform the following steps:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
The processor 800 is further configured to read the computer program and perform the following steps:
mapping the interleaved target leader sequence to a frequency domain through resources;
modulating the signal mapped to the frequency domain through Orthogonal Frequency Division Multiplexing (OFDM) to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
Furthermore, a computer-readable storage medium of an embodiment of the present invention stores a computer program executable by a processor to implement:
generating a ZC sequence according to a root sequence number, wherein the root sequence number is related to the window length of a single user;
generating a first leader sequence according to the ZC sequence;
determining a target leader sequence and a target interleaver according to the first leader sequence;
interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence;
sending the interleaved target leader sequence to network side equipment;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Wherein, the generating of the ZC sequence according to the root sequence number comprises:
acquiring a cyclic shift parameter;
determining a root sequence number corresponding to the cyclic shift parameter;
and generating a ZC sequence according to the serial number of the root sequence.
Wherein the acquisition cyclic shift parameter is determined by the following formula:
Figure BDA0001963120030000221
wherein d isuDenotes the cyclic shift parameter, p denotes the window length of a single user (the red background portion is instead: satisfies the division by NZCSmallest non-negative integer of the remainder 1), NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure BDA0001963120030000222
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
Wherein the generating a first preamble sequence according to the ZC sequence comprises:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu，v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
Wherein the determining a target preamble sequence and a target interleaver according to the first preamble sequence comprises:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
Wherein the selecting a target preamble sequence from the second preamble sequence and a target interleaver from the interleavers comprises:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
Wherein, the sending the interleaved target preamble sequence to the network side device includes:
mapping the interleaved target leader sequence to a frequency domain through resources;
modulating the signal mapped to the frequency domain through Orthogonal Frequency Division Multiplexing (OFDM) to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
Furthermore, a computer-readable storage medium of an embodiment of the present invention stores a computer program executable by a processor to implement:
generating an interleaver and a deinterleaver;
receiving a first leader sequence sent by a terminal;
sending the interleaver and a second preamble sequence to the terminal, wherein the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
receiving an interleaved target leader sequence sent by the terminal;
deinterleaving the target preamble sequence using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
Grouping the first leader sequence to obtain a second leader sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the transceiving method according to various embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A signal processing method applied to a terminal is characterized by comprising the following steps:
acquiring a cyclic shift parameter, wherein the cyclic shift parameter is equal to the window length of a single user, or the cyclic shift parameter is equal to the window length of the single user subtracted from the length of the ZC sequence;
determining a root sequence number corresponding to the cyclic shift parameter;
generating a ZC sequence according to the root sequence number;
generating a first leader sequence according to the ZC sequence;
determining a target leader sequence and a target interleaver according to the first leader sequence;
interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence;
sending the interleaved target leader sequence to network side equipment;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
2. The method of claim 1, wherein the obtaining cyclic shift parameter is determined by the following equation:
Figure FDA0003343066720000011
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure FDA0003343066720000012
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
3. The method of claim 1, wherein the generating a first preamble sequence from the ZC sequence comprises:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu,v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
4. The method of claim 1, wherein determining a target preamble sequence and a target interleaver from the first preamble sequence comprises:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
5. The method of claim 4, wherein selecting a target preamble sequence from the second preamble sequence and selecting a target interleaver from the interleavers comprises:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
6. The method of claim 1, wherein the sending the interleaved target preamble sequence to a network side device comprises:
mapping the interleaved target leader sequence to a frequency domain through resources;
modulating the signal mapped to the frequency domain through Orthogonal Frequency Division Multiplexing (OFDM) to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
7. A signal processing method is applied to network side equipment, and is characterized by comprising the following steps:
generating an interleaver and a deinterleaver;
receiving a first leader sequence sent by a terminal;
sending the interleaver and a second preamble sequence to the terminal, wherein the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
receiving an interleaved target leader sequence sent by the terminal;
deinterleaving the target preamble sequence using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target leader sequences;
wherein the target preamble sequence is determined by the terminal according to the first preamble sequence; the first preamble sequence is generated as follows:
acquiring a cyclic shift parameter, wherein the cyclic shift parameter is equal to the window length of a single user, or the cyclic shift parameter is equal to the window length of the single user subtracted from the length of the ZC sequence;
determining a root sequence number corresponding to the cyclic shift parameter;
generating a ZC sequence according to the root sequence number;
and generating the first leader sequence according to the ZC sequence.
8. The method of claim 7, wherein the sending the interleaver and the second preamble sequence to the terminal comprises:
grouping the first leader sequence to obtain a second leader sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
9. A communication device, comprising: a transceiver, a memory, a processor, and a computer program stored on the memory and executable on the processor; it is characterized in that the preparation method is characterized in that,
the processor is used for reading the program in the memory and executing the following processes:
acquiring a cyclic shift parameter, wherein the cyclic shift parameter is equal to the window length of a single user, or the cyclic shift parameter is equal to the window length of the single user subtracted from the length of the ZC sequence;
determining a root sequence number corresponding to the cyclic shift parameter;
generating a ZC sequence according to the root sequence number;
generating a first leader sequence according to the ZC sequence, and sending the first leader sequence to network side equipment;
determining a target leader sequence and a target interleaver according to the first leader sequence;
interweaving the target leader sequence by using the target interweaver to obtain an interwoven target leader sequence;
the transceiver is configured to send the interleaved target preamble sequence to a network side device;
different terminals respectively use the same target interleaver to interleave different target preamble sequences.
10. The apparatus of claim 9, wherein the processor is further configured to read a program in the memory and perform the following:
determining the acquisition cyclic shift parameter by the following formula:
Figure FDA0003343066720000041
wherein d isuDenotes a cyclic shift parameter, p denotes a window length of a single user, NZCIndicates the length of the ZC sequence;
generating a ZC sequence according to the root sequence number by the following formula:
Figure FDA0003343066720000042
xu(N) represents a ZC sequence, N is 0-NZC-1, n is a constant, u represents the root sequence number.
11. The apparatus of claim 9, wherein the processor is further configured to read a program in the memory and perform the following:
generating a leader sequence by cyclic shift according to the root sequence number by using the following formula;
xu,v(n)＝xu((n+Cv)mod NZC)
adding a Cyclic Prefix (CP) and a Guard Time (GT) to the leader sequence to generate the first leader sequence;
wherein x isu,v(N) represents a first leader sequence, 0. ltoreq. N. ltoreq.NZC-1, n is a constant, CvDenotes cyclic shift, NZCDenotes the length of the ZC sequence, (n + C)v)mod NZCIs to indicate the utilization of n and CvSum to NZCAnd carrying out a modulus taking operation.
12. The apparatus of claim 9, wherein the processor is further configured to read a program in the memory and perform the following:
sending the first preamble sequence to the network side device;
acquiring a second leader sequence distributed by the network side equipment according to the first leader sequence and acquiring an interleaver distributed by the network side equipment;
selecting a target preamble sequence from the second preamble sequence, and selecting a target interleaver from the interleavers.
13. The apparatus of claim 12, wherein the processor is further configured to read a program in the memory and perform the following:
generating a leader sequence subset according to the second leader sequence;
selecting a target leader sequence from the leader sequence subset, and sending a random access request to the network side equipment;
a target interleaver is selected from the interleavers.
14. The apparatus of claim 9, wherein the processor is further configured to read a program in the memory and perform the following:
mapping the interleaved target leader sequence to a frequency domain through resources;
carrying out OFDM modulation on the signal mapped to the frequency domain to generate a time domain symbol;
constructing a preamble signal according to the time domain symbol, and sending the interleaved target preamble sequence to the network side equipment through the preamble signal.
15. A communication device, comprising: a transceiver, a memory, a processor, and a computer program stored on the memory and executable on the processor; it is characterized in that the preparation method is characterized in that,
the processor is used for reading the program in the memory and executing the following processes:
generating an interleaver and a deinterleaver;
receiving a first leader sequence sent by a terminal;
sending the interleaver and a second preamble sequence to the terminal, wherein the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
receiving an interleaved target leader sequence sent by the terminal;
deinterleaving the target preamble sequence using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target leader sequences;
wherein the target preamble sequence is determined by the terminal according to the first preamble sequence; the first preamble sequence is generated as follows:
acquiring a cyclic shift parameter, wherein the cyclic shift parameter is equal to the window length of a single user, or the cyclic shift parameter is equal to the window length of the single user subtracted from the length of the ZC sequence;
determining a root sequence number corresponding to the cyclic shift parameter;
generating a ZC sequence according to the root sequence number;
and generating the first leader sequence according to the ZC sequence.
16. The apparatus of claim 15, wherein the processor is further configured to read a program in the memory and perform the following:
grouping the first leader sequence to obtain a second leader sequence;
and transmitting the interleaver and the second preamble sequence to the terminal.
17. A signal processing apparatus provided in a terminal, comprising:
the first generation module is used for generating a ZC sequence according to the root serial number;
a second generating module, configured to generate a first preamble sequence according to the ZC sequence, and send the first preamble sequence to a network side device;
a determining module, configured to determine a target preamble sequence and a target interleaver according to the first preamble sequence;
an obtaining module, configured to interleave the target preamble sequence by using the target interleaver, and obtain an interleaved target preamble sequence;
a sending module, configured to send the interleaved target preamble sequence to a network side device;
different terminals respectively use the same target interleaver to interleave different target leader sequences;
wherein the first generating module comprises:
an obtaining submodule, configured to obtain a cyclic shift parameter, where the cyclic shift parameter is equal to a window length of a single user, or the cyclic shift parameter is equal to a length of a ZC sequence minus the window length of the single user;
the determining submodule is used for determining a root sequence number corresponding to the cyclic shift parameter;
and the generating submodule is used for generating the ZC sequence according to the serial number of the root sequence.
18. A signal processing apparatus, provided in a network side device, includes:
a generating module for generating an interleaver and a deinterleaver;
a first receiving module, configured to receive a first preamble sequence sent by a terminal;
a sending module, configured to send the interleaver and a second preamble sequence to the terminal, where the second preamble sequence is obtained according to a first preamble sequence sent by the terminal;
a second receiving module, configured to receive the interleaved target preamble sequence sent by the terminal;
a processing module, configured to perform deinterleaving on the target preamble sequence by using the deinterleaver;
different terminals respectively use the same target interleaver to interleave different target leader sequences;
wherein the target preamble sequence is determined by the terminal according to the first preamble sequence; the first preamble sequence is generated as follows:
acquiring a cyclic shift parameter, wherein the cyclic shift parameter is equal to the window length of a single user, or the cyclic shift parameter is equal to the window length of the single user subtracted from the length of the ZC sequence;
determining a root sequence number corresponding to the cyclic shift parameter;
generating a ZC sequence according to the root sequence number;
and generating the first leader sequence according to the ZC sequence.
19. The apparatus of claim 18, wherein the sending module comprises:
a grouping submodule, configured to group the first preamble sequence to obtain the second preamble sequence;
a sending submodule, configured to send the interleaver and the second preamble sequence to the terminal.
20. A computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the steps in the method according to any one of claims 1 to 6; alternatively, the computer program realizes the steps in the method according to any one of claims 7 to 8 when executed by a processor.
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