CN111510111B - Oscillation module and chip powering-up method - Google Patents

Oscillation module and chip powering-up method Download PDF

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CN111510111B
CN111510111B CN202010342099.9A CN202010342099A CN111510111B CN 111510111 B CN111510111 B CN 111510111B CN 202010342099 A CN202010342099 A CN 202010342099A CN 111510111 B CN111510111 B CN 111510111B
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clock signal
pulses
reaches
trigger signal
voltage
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CN111510111A (en
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袁志勇
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The present disclosure relates to the field of semiconductor integrated circuits, and in particular, to an oscillation module and a chip power-on method. Wherein the oscillation module includes: the first oscillating unit and the second oscillating unit are cascaded; the first oscillation unit is used for outputting a first clock signal when receiving the first trigger signal and generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value; the second oscillation unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal, and generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, wherein the third trigger signal is used for controlling the first oscillation unit to stop outputting the first clock signal. According to the technical scheme, low-voltage starting can be achieved, meanwhile, reset failure of the integrated circuit is avoided, and power-on power consumption of the integrated circuit system is effectively controlled.

Description

Oscillation module and chip powering-up method
Technical Field
The present disclosure relates to the field of semiconductor integrated circuits, and in particular, to an oscillation module and a chip power-on method.
Background
In the technical field of semiconductor integrated circuits, a system Power-On process is a process of slowly climbing a Power supply voltage, in which an integrated circuit system is kept static until the Power supply voltage reaches a predetermined voltage, and a Power-On Reset (POR) circuit releases a POR signal to initialize the integrated circuit system, and after the initialization is completed, the integrated circuit starts to work normally.
However, when the POR signal is released, the power-on reset circuit may have a problem that the voltage reached by the power supply is lower than the voltage capable of ensuring the normal operation of the integrated circuit system. Taking the slow power-on process of the integrated circuit system with the normal working voltage being the high-voltage threshold (1.65V-5.5V) as an example, when the POR signal is released by the power-on reset circuit, the voltage reached by the power supply voltage is about 1V at the minimum, and the normal reset of the integrated circuit system can be adversely affected.
The related art generally adopts a ring oscillator to count time and wait for the power supply voltage to reach the normal working voltage, but the duty ratio precision of a clock signal generated by the ring oscillator is poor, and the power consumption of the clock signal varies greatly with the power supply voltage.
Disclosure of Invention
The application provides an oscillation module and a chip powering-on method, which can effectively control the powering-on power consumption of an integrated circuit system.
As a first aspect of the present application, there is provided an oscillation module including: the first oscillating unit and the second oscillating unit are cascaded;
the first oscillation unit is used for outputting a first clock signal when receiving a first trigger signal and generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value;
the second oscillation unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal, and generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, wherein the third trigger signal is used for controlling the first oscillation unit to stop outputting the first clock signal.
Optionally, the first oscillator comprises an input end, an output end and a control end; the input end of the first oscillator is used for receiving the first trigger signal, and when the first trigger signal is received, the output end of the first oscillator outputs a first clock signal;
the first counter is used for receiving the first clock signal, counting the pulses of the first clock signal, and generating a second trigger signal when the number of the pulses of the first clock signal reaches a first threshold value.
Optionally, a second oscillator, the second oscillator comprising an input and an output; the input end of the second oscillator is used for receiving the second trigger signal, and when the second trigger signal is received, the output end of the second oscillator outputs a second clock signal;
the second counter is used for receiving the second clock signal and counting the pulses of the second clock signal, and when the number of the pulses of the second clock signal reaches a second threshold value, the second counter generates a third trigger signal to the control end of the first oscillator.
As a second aspect of the present application, there is provided a chip power-on method including:
releasing a first trigger signal for triggering the first oscillating unit according to the first aspect of the application when the power supply voltage is determined to be increased to a first target voltage;
when the first trigger signal is received, oscillating to form a first clock signal;
calculating the number of pulses in the first clock signal, and generating a second trigger signal when the number of pulses reaches a first threshold value, wherein the second trigger signal is used for triggering a second oscillating unit according to the first aspect of the application;
when the second trigger signal is received, oscillating to form a second clock signal, and transmitting the second clock signal to the integrated circuit system;
and calculating the number of pulses in the second clock signal, and generating a third trigger signal when the number of pulses reaches a second threshold value, wherein the third trigger signal is used for controlling the stopping of the first clock signal.
Optionally, when the number of pulses reaches the first threshold, the power supply voltage reaches a second target voltage, and the second target voltage is 90% -97% of the normal working voltage.
Optionally, the power supply voltage is gradually increased during the chip power-up method.
Optionally, when the number of pulses reaches the second threshold, the power supply voltage reaches a normal operating voltage.
Optionally, the first target voltage ranges from 50% to 60% of the normal operating voltage.
The technical scheme of the application at least comprises the following advantages: according to the technical scheme, low-voltage starting can be achieved, meanwhile, reset failure of the integrated circuit is avoided, and power-on power consumption of the integrated circuit system is effectively controlled.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of an oscillation module according to an embodiment of the first aspect of the present application;
FIG. 2 is a flowchart of a method for powering on a chip according to an embodiment of the second aspect of the present application;
fig. 3 is a timing diagram during a power supply voltage ramp up in the present application.
100. The first oscillating unit, 110, the first oscillator, 120, the first counter, 200, the second oscillating unit, 210, the second oscillator, 220, the second counter.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
As a first aspect of the present invention, there is provided an oscillation module including a first oscillation unit 100 and a second oscillation unit 200 in cascade, referring to fig. 1;
a first oscillation unit 100 configured to, when receiving a first trigger signal1, oscillate and output a first clock signal ULV clock, and generate a second trigger signal2 when the number of pulses of the first clock signal ULV clock reaches a first threshold;
the second oscillating unit 200 is configured to oscillate and output the second clock signal ULP clock to the integrated circuit system when receiving the second trigger signal2, and generate a third trigger signal3 when the number of pulses of the second clock signal ULP clock reaches a second threshold value, where the third trigger signal3 is used to control the first oscillating unit 100 to stop outputting the first clock signal ULV clock.
The first oscillation unit 100 includes:
a first oscillator 110, the first oscillator 110 comprising an input, an output and a control; the input terminal of the first oscillator 110 is configured to receive the first trigger signal1, and when the first trigger signal1 is received, the output terminal of the first oscillator 110 outputs a first clock signal ULV clock.
The first counter 120 is configured to receive the first clock signal ULV clock and count pulses of the first clock signal ULV clock, and when the number of pulses of the first clock signal ULV clock reaches a first threshold, the first counter 120 generates a second trigger signal2.
The second oscillation unit 200 includes:
a second oscillator 210, the second oscillator 210 comprising an input and an output; the input end of the second oscillator 210 is configured to receive the second trigger signal2, and when the second trigger signal2 is received, the output end of the second oscillator 210 outputs a second clock signal ULP clock.
And a second counter 220, where the second counter 220 is configured to receive the second clock signal ULP clock and count pulses of the second clock signal ULP clock, and when the number of pulses of the second clock signal ULP clock reaches a second threshold, the second counter 220 generates a third trigger signal3 to the control end of the first oscillator 110.
In the power-on process of the integrated circuit, the power supply voltage of the integrated circuit is gradually increased, and when the power supply voltage is increased to a first target voltage V1, a first trigger signal1 which can enable the oscillation module to work is released, wherein the range of the first target voltage V1 is 50% -60% of the normal working voltage V3. When the number of pulses of the first clock signal ULV clock reaches a first threshold value, the power supply voltage reaches a second target voltage V2, and the second target voltage V2 is 90% -97% of the normal working voltage V3. When the second clock signal ULP clock is oscillated and outputted to the integrated circuit system, the integrated circuit system is initialized, and after the initialization is completed, the integrated circuit starts to work normally.
Referring to fig. 3, when the power supply voltage reaches the first target voltage V1, the first oscillating unit 100 of the oscillating module starts to operate, the first oscillating unit 100 starts to oscillate to form a first clock signal ULV clock, counts the number of pulses of the first clock signal ULV clock, when the number of pulses of the first clock signal ULV clock reaches a first threshold, the power supply voltage reaches a second target voltage V2 which is 90% -97% of the normal operating voltage V3, the second oscillating unit 200 generates a second trigger signal2, starts to oscillate to form a second clock signal ULP clock when the second oscillating unit 200 receives the second trigger signal2, outputs the second clock signal ULP clock to the integrated circuit system, counts the number of pulses of the second clock signal ULP clock, and when the number of pulses of the second clock signal ULP clock reaches a second threshold, the power supply voltage reaches the normal operating voltage V3, controls the first oscillating unit 100 to stop outputting the first clock signal ULP clock, i.e. the integrated circuit starts to operate normally.
Illustratively:
an integrated circuit system with a normal operating voltage V3 of 1.65V, when the power voltage reaches a first target voltage V11V, the first oscillating unit 100 of the oscillating module starts to operate, the first oscillating unit 100 starts to oscillate to form a first clock signal ULV clock, counts the number of pulses of the first clock signal ULV clock, when the number of pulses of the first clock signal ULV clock reaches a first threshold value, the second oscillating unit 200 generates a second trigger signal2 when the power voltage reaches a second target voltage V21.6V, starts to oscillate to form a second clock signal ULP clock when the second oscillating unit 200 receives the second trigger signal2, and outputs the second clock signal ULP clock to the integrated circuit system, and the integrated circuit system is initialized according to the second clock signal ULP clock; and counting the number of pulses of the second clock signal ULP clock, and when the number of pulses of the second clock signal ULP clock reaches a second threshold, the power supply voltage reaches a normal working voltage V31.65V, controlling the first oscillating unit 100 to stop outputting the first clock signal ULV clock, i.e. the integrated circuit starts to work normally.
As a second aspect of the present application, there is provided a chip power-on method based on the above oscillation module, referring to fig. 2, the chip power-on method including:
s1: it is determined that the power supply is increased to the first target voltage V1, and the first trigger signal1 is released, and the first trigger signal1 is used to trigger the first oscillating unit 100 according to the first aspect of the present application.
For step S1, during the power-on process of the integrated circuit, the power supply voltage of the integrated circuit is gradually increased, and when the voltage of the power supply is increased to the first target voltage V1, the first trigger signal1 capable of enabling the oscillating module to work is released, wherein the range of the first target voltage V1 is 50% -60% of the normal working voltage V3, so that the oscillating module can be started at a low voltage.
S2: when the first oscillation unit 100 receives the first trigger signal1, the first oscillation unit 100 oscillates to form a first clock signal ULV clock.
Illustratively, when the first oscillator 110 of the first oscillating unit 100 receives the first trigger signal1, the first oscillator 110 oscillates to form a first clock signal ULV clock.
S3: the first oscillating unit 100 calculates the number of pulses of the first clock signal ULV clock, and generates a second trigger signal2 when the number of pulses reaches a first threshold value, where the second trigger signal2 is used to trigger the second oscillating unit 200 according to the first aspect of the present application.
For step S3, when the number of pulses reaches a first threshold, the power supply voltage reaches a second target voltage V2, where the second target voltage V2 is 90% -97% of the normal working voltage V3;
the first counter 120 calculates the number of pulses of the first clock signal ULV clock and generates the second trigger signal2 when the number of pulses reaches the first threshold.
S4: when the second oscillation unit 200 receives the second trigger signal2, it oscillates to form a second clock signal ULP clock, and transmits the second clock signal ULP clock to the integrated circuit system.
Illustratively, when the second oscillator 210 of the second oscillating unit 200 receives the second trigger signal2, the second oscillator 210 oscillates to form a second clock signal ULP clock.
When the power supply voltage reaches 90% -97% of the normal working voltage V3, a second clock signal ULP clock is formed and transmitted to the integrated circuit system, so that the integrated circuit system is initialized, and the oscillation module can be operated with low power consumption while the reset failure of the integrated circuit can be avoided.
S5: and calculating the number of pulses in the second clock signal ULP clock, and generating a third trigger signal3 when the number of pulses reaches a second threshold value, wherein the third trigger signal3 is used for controlling the stopping of the first clock signal ULV clock.
Illustratively, the second counter 220 of the second oscillating unit 200 calculates the number of pulses in the second clock signal ULP clock, and generates the third trigger signal3 when the number of pulses reaches the second threshold.
When the third trigger signal3 is generated, the power supply voltage reaches the normal working voltage V3, the integrated circuit system can work normally, and the first clock signal ULV clock is controlled to stop at the moment, so that the power-on power consumption of the system is effectively controlled.
FIG. 3 is a timing chart of the power-up process of the integrated circuit, wherein a ramp is a ramp state chart of the power supply voltage, and shows the relationship between the power supply voltage value and time in the power supply voltage ramp process, and three nodes Q1 (T1, V1), Q2 (T2, V2) and Q3 (T3, V3) are respectively arranged on the ramp, wherein Q1 represents that the first trigger voltage signal1 is received at the time T1, the power supply voltage ramps up to the first target voltage V1, and a first clock signal ULV clock is formed, and the first clock signal ULV clock is generated until the third trigger voltage signal3 is received at the time T3 and stopped; q2 indicates that at time T2, the second trigger voltage signal2 is received, the power supply voltage rises to the second target voltage V2, and a second clock signal ULP clock is formed, and the second clock signal ULP clock is generated until the third trigger voltage signal3 is received at time T3; q3 indicates that at time T3, the third trigger voltage signal3 is received, and the power supply voltage rises to the normal operation voltage V3.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (5)

1. An oscillating module, characterized in that it comprises: the first oscillating unit and the second oscillating unit are cascaded;
the first oscillation unit is used for outputting a first clock signal when the first trigger signal is received, generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value, and enabling the power supply voltage to reach a second target voltage when the number of pulses reaches the first threshold value;
the second oscillating unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal, generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, controlling the first oscillating unit to stop outputting the first clock signal, and enabling the power supply voltage to reach a normal working voltage when the number of pulses reaches the second threshold value;
the second target voltage is higher than the first target voltage, and the normal operating voltage is higher than the second target voltage;
the first oscillation unit includes:
the first oscillator comprises an input end, an output end and a control end; the input end of the first oscillator is used for receiving the first trigger signal, and when the first trigger signal is received, the output end of the first oscillator outputs a first clock signal;
the first counter is used for receiving the first clock signal and counting the pulses of the first clock signal, and when the number of the pulses of the first clock signal reaches a first threshold value, the first counter generates a second trigger signal;
the second oscillation unit includes:
a second oscillator comprising an input and an output; the input end of the second oscillator is used for receiving the second trigger signal, and when the second trigger signal is received, the output end of the second oscillator outputs a second clock signal;
the second counter is used for receiving the second clock signal and counting the pulses of the second clock signal, and when the number of the pulses of the second clock signal reaches a second threshold value, the second counter generates a third trigger signal to the control end of the first oscillator.
2. A method of chip powering up, characterized in that it is performed based on the oscillating module of claim 1, the method comprising:
releasing a first trigger signal when the power supply voltage is determined to be increased to a first target voltage, wherein the first trigger signal is used for triggering the first oscillating unit;
when the first trigger signal is received, oscillating to form a first clock signal;
calculating the number of pulses in the first clock signal, and generating a second trigger signal when the number of pulses reaches a first threshold value, wherein the second trigger signal is used for triggering the second oscillating unit; when the number of pulses reaches a first threshold, the power supply voltage reaches a second target voltage;
when the second trigger signal is received, oscillating to form a second clock signal, and transmitting the second clock signal to the integrated circuit system;
calculating the number of pulses in the second clock signal, and generating a third trigger signal when the number of pulses reaches a second threshold value, wherein the third trigger signal is used for controlling the stopping of the first clock signal; when the number of pulses reaches a second threshold value, the power supply voltage reaches a normal working voltage;
the second target voltage is higher than the first target voltage, and the normal operating voltage is higher than the second target voltage.
3. The method of powering up a chip of claim 2, wherein the power supply voltage reaches a second target voltage when the number of pulses reaches a first threshold, the second target voltage being 90% to 97% of a normal operating voltage.
4. The method of on-chip power-up of claim 2, wherein the power supply voltage is gradually increased during the method of on-chip power-up.
5. The method of powering up a chip of claim 2, wherein the first target voltage is in the range of 50% to 60% of the normal operating voltage.
CN202010342099.9A 2020-04-27 2020-04-27 Oscillation module and chip powering-up method Active CN111510111B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969631A (en) * 1996-06-14 1999-10-19 Temic Telefunken Microelectronic Gmbh Method and control system for the synchronized transmission of digital data
EP2573683A1 (en) * 2010-05-20 2013-03-27 Renesas Electronics Corporation Data processor and electronic control unit
CN106291148A (en) * 2015-05-20 2017-01-04 中芯国际集成电路制造(上海)有限公司 Test circuit and method of testing thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969631A (en) * 1996-06-14 1999-10-19 Temic Telefunken Microelectronic Gmbh Method and control system for the synchronized transmission of digital data
EP2573683A1 (en) * 2010-05-20 2013-03-27 Renesas Electronics Corporation Data processor and electronic control unit
CN106291148A (en) * 2015-05-20 2017-01-04 中芯国际集成电路制造(上海)有限公司 Test circuit and method of testing thereof

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