CN111510079B - Pseudo-differential structure weak current integrating circuit based on correlated double sampling - Google Patents

Pseudo-differential structure weak current integrating circuit based on correlated double sampling Download PDF

Info

Publication number
CN111510079B
CN111510079B CN202010298601.0A CN202010298601A CN111510079B CN 111510079 B CN111510079 B CN 111510079B CN 202010298601 A CN202010298601 A CN 202010298601A CN 111510079 B CN111510079 B CN 111510079B
Authority
CN
China
Prior art keywords
capacitor
switch
terminal
common mode
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010298601.0A
Other languages
Chinese (zh)
Other versions
CN111510079A (en
Inventor
朱磊
贺林
郭宇锋
蔡志匡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
Original Assignee
Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd, Nanjing University of Posts and Telecommunications filed Critical Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Priority to CN202010298601.0A priority Critical patent/CN111510079B/en
Publication of CN111510079A publication Critical patent/CN111510079A/en
Application granted granted Critical
Publication of CN111510079B publication Critical patent/CN111510079B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a pseudo differential structure weak current integrating circuit based on correlated double sampling, which comprises a differential amplifier A with an input common-mode feedback circuit 1 A parasitic equivalent capacitor C p A dummy capacitor C dum Two symmetrical input common-mode feedback capacitors, two symmetrical feedback capacitors, and two symmetrical self-zeroing capacitors. The invention adopts a relevant double sampling circuit to convert an input current signal into voltage on a holding capacitor, and stores offset and low-frequency noise information of an amplifier through a self-zeroing capacitor. A pseudo-differential structure circuit is used for reducing charge injection and clock feed-through effect when the MOS switch works. An input common mode feedback circuit is introduced to restrain common mode fluctuation of the input end of the amplifier A1 and reduce errors caused by common mode-differential mode conversion.

Description

Pseudo differential structure weak current integrating circuit based on correlated double sampling
Technical Field
The invention designs a CMOS integrated circuit, and particularly relates to a pseudo-differential structure weak current integrating circuit based on correlated double sampling.
Background
In the detection of weak current of a semiconductor, the current of sub pA level needs to be detected. The noise of the circuit mainly comes from the following two aspects. One is the noise of the input signal itself, which is often entrained in weak current signals. At the same time, the amplification circuit itself may also present noise, such as low frequency 1/f noise. And the amplifier circuit also has offset voltage due to the matching problem of the device itself.
A Correlated Double Sampling (CDS) technique is used to remove low frequency noise and amplifier offset. The correlated double sampling circuit charges and discharges the sampling capacitor through two stages of reset and integration to obtain the difference value of the signal level and the reset level, and the offset and the low-frequency noise of the amplifier are stored by a self-zeroing Capacitor (CAZ).
But supply voltage fluctuations will introduce output fluctuations due to charge injection and clock feed-through effects. And the circuit also needs a sufficiently large common mode rejection ratio in order to increase the interference rejection capability of the circuit. At the same time, the circuit also needs to suppress the noise introduced by the post-amplifier.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a pseudo-differential structure weak current integrating circuit based on correlated double sampling, firstly, in a zero clearing stage, a capacitor in the circuit is connected with a reset level signal to clear the charge on the capacitor; secondly, storing the offset and low-frequency noise information of the amplifier by using a self-zeroing capacitor in a self-zeroing stage; the current passes through the closed switch S in the amplification stage 1 Switch six S 6 The weak current integrating circuit can effectively avoid charge injection and clock feed-through effects and has strong anti-jamming capability. The charge integrator is designed into a pseudo-differential structure to avoid charge injection and clock feed-through effect existing in the operation of the MOS switch. By introducing the input common mode feedback circuit, better common mode rejection ratio and power supply rejection ratio are obtained.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
a pseudo differential structure weak current integrating circuit based on correlated double sampling comprises a differential amplifier A with an input common mode feedback circuit 1 Parasitic equivalent capacitance C p Dummy capacitor C dum An input common mode feedback capacitor C ifb1 An input common mode feedback capacitor II C ifb2 A feedback capacitor C f1 A feedback capacitor II C f2 Self-zeroing capacitor-C AZ1 Self-zeroing capacitor two C AZ2 A load capacitor C L1 A load capacitor II C L2 And a differential holding capacitor C H1 A differential holding capacitor II C H2 A switch S 1 And a switch II S 2 And a switch III S 3 And switch four S 4 And a switch five S 5 Six S of switch 6 Seven S of switch 7 Eight S switches 8 Nine S switch 9 And a switch ten S 10 Wherein:
parasitic equivalent capacitance C p Respectively connected with an input current signal and a switch S 1 The first end of (a).
Input common mode feedback capacitor C ifb1 The first ends of the first and second switches are respectively connected with a switch S 1 Second terminal of (1), switch two 2 First terminal of, feedback capacitance C f1 With input common mode feedback circuit differential amplifier A 1 And the first inverting input of the input common mode feedback circuit in (1) and the non-inverting input of the differential amplifier. Input common mode feedback capacitor C ifb1 Second terminal of the differential amplifier A with an input common mode feedback circuit 1 To the output of the common mode feedback circuit.
Feedback capacitor C f1 Second end of the switch III S 3 First terminal of (1), load capacitance one C L1 First terminal of (1), self-zeroing capacitor one C AZ1 And a differential amplifier A with an input common mode feedback circuit 1 The non-inverting output of the differential amplifier. Switch three S 3 The second terminal of the load capacitor is connected with the output common-mode terminal and the load capacitor C L1 The second terminal of (a) is grounded.
Self-zeroing capacitor-C AZ1 Second end of (1) is connected with a switch S 4 First terminal, switch five S 5 The first end of (a). Switch four S 4 Second terminal of the first and second transistors is connected with an output common mode terminal and a differential holding capacitor C H1 The first end of (a). Switch five S 5 Second terminal of (1) is connected with a differential holding capacitor (C) H1 And a signal output terminal.
Dummy capacitor c dum Second end of (2) switch six S 6 First terminal of (1), switch six S 6 The second ends of the two common-mode feedback capacitors are respectively connected with the input common-mode feedback capacitor II C ifb2 First end of, switch seven S 7 First terminal of (1), feedback capacitor two C f2 A differential amplifier A with an input common mode feedback circuit 1 Second inverting input of the input common mode feedback circuitTerminal and the inverting input terminal of the differential amplifier.
Input common mode feedback capacitor II C ifb2 The second end of the switch is connected with the output end of the input common mode feedback circuit and the switch is seven S 7 The second terminal of (a) is coupled to the input common mode level. Feedback capacitor two C f2 The second ends of the two terminals are respectively connected with the switch eight S 8 A differential amplifier A with an input common mode feedback circuit 1 The inverting output terminal of the differential amplifier.
Load capacitance two C L2 First terminal and self-zeroing capacitor two C AZ2 Is connected. Self-zeroing capacitor C AZ2 The second ends of the two switches are respectively connected with a switch nine S 9 First terminal of (1), switch ten S 10 First terminal of (1), switch nine S 9 Second terminal of (2) is connected to output common mode level and differential holding capacitor (II C) H2 The second end of (a). Switch ten S 10 Second ends of the first and second capacitors are respectively connected with a capacitor C H2 Differential holding capacitor two C H2 And a signal output terminal.
Preferably, the following components: the input common mode feedback circuit is a three-input folding transconductance amplifier.
Compared with the prior art, the invention has the following beneficial effects:
the invention avoids the charge injection and clock feed-through effect existing in the working process of the MOS switch through the pseudo-differential structure. By introducing the input common mode feedback circuit, better common mode rejection ratio and power supply rejection ratio are obtained. The simultaneous correlated double sampling circuit converts the input current signal into a differential holding capacitor-C H1 A differential holding capacitor II C H2 Voltage on, through a self-zeroing capacitor-C AZ1 Self-zeroing capacitor two C AZ2 Amplifier mismatch and low frequency noise information are stored.
Drawings
Fig. 1 is a schematic structural diagram of a pseudo-differential structure weak current integrating circuit based on correlated double sampling according to the present invention.
Fig. 2 is a timing diagram of switching of an example of the pseudo-differential structure weak current integration circuit based on correlated double sampling according to the present invention.
Detailed Description
The present invention is further illustrated in the accompanying drawings and described in the following detailed description, it is to be understood that such examples are included solely for the purposes of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications of the invention will become apparent to those skilled in the art after reading the present specification, and it is intended to cover all such modifications as fall within the scope of the invention as defined in the appended claims.
A pseudo-differential structure weak current integrating circuit based on correlated double sampling mainly introduces an amplifier A1 of an input common mode feedback circuit and a correlated double sampling circuit, wherein the output end of the input common mode feedback circuit is connected with the input end of the correlated double sampling circuit, as shown in figure 1, the pseudo-differential structure weak current integrating circuit comprises a differential amplifier A with an input common mode feedback circuit 1 Parasitic equivalent capacitance C p Dummy capacitor C dum And mutually symmetrical input common mode feedback capacitor C ifb1 And an input common mode feedback capacitor II C ifb2 Mutually symmetrical feedback capacitors-C f1 And a feedback capacitor II C f2 Mutually symmetrical self-zeroing capacitors-C AZ1 And self-zeroing capacitor two C AZ2 Mutually symmetrical load capacitors C L1 And a load capacitor II C L2 Mutually symmetrical differential holding capacitors C H1 And a differential holding capacitor II C H2 And a switch I 1 And a switch II S 2 And a switch III S 3 And switch four S 4 And a switch five S 5 Six S of switch 6 Seven S of switch 7 Eight S switches 8 Nine S switch 9 And a switch ten S 10 Said switch is one S 1 And a switch II S 2 And switch three S 3 And a switch four S 4 Switch five S 5 Six S of switch 6 Seven S of switch 7 Eight S switches 8 Nine S switch 9 And a switch ten S 10 The structure is the same, an input common mode feedback (icmpb) is introduced into the amplifier A1, the input common mode feedback circuit is a three-input folded transconductance amplifier, the amplifier A1 is a fully differential folded transconductance amplifier, and a gain bootstrap technique and a source degeneration technique are adopted to improve the gain, wherein:
parasitic equivalent capacitance C p Respectively connected with the inputCurrent signal lin and switch S 1 The first end of (a).
Input common mode feedback capacitor C ifb1 The first ends of the first and second switches are respectively connected with a switch S 1 Second terminal of (1), switch two 2 First terminal of, feedback capacitance C f1 With input common mode feedback circuit differential amplifier A 1 And the first inverting input of the input common mode feedback circuit in (1) and the non-inverting input of the differential amplifier. Input common mode feedback capacitor C ifb1 Second terminal of the differential amplifier A with an input common mode feedback circuit 1 To the output of the input common mode feedback circuit.
Feedback capacitor C f1 Second end of (2) is connected with a switch III 3 First terminal of (1), load capacitance one C L1 First terminal of (1), self-zeroing capacitor one C AZ1 And a differential amplifier A with an input common mode feedback circuit 1 The non-inverting output of the differential amplifier. Switch three S 3 The second terminal of the load capacitor is connected with the output common-mode terminal and the load capacitor is C L1 The second terminal of (a) is grounded.
Self-zeroing capacitor-C AZ1 Second end of (1) is connected with a switch S 4 First terminal, switch five S 5 The first end of (a). Switch four S 4 Second terminal of the first and second transistors is connected with an output common mode terminal and a differential holding capacitor C H1 The first end of (a). Switch five S 5 Second terminal of (2) is connected to a differential holding capacitor one C H1 And a signal output terminal.
Dummy capacitor c dum Second terminal of (2) switch six S 6 First terminal of (1), switch six S 6 The second ends of the two capacitors are respectively connected with an input common mode feedback capacitor II C ifb2 First end of (1), switch seven S 7 First terminal of (1), feedback capacitance two C f2 A differential amplifier A with an input common mode feedback circuit 1 And the second inverting input of the input common mode feedback circuit and the inverting input of the differential amplifier.
Input common mode feedback capacitor two C ifb2 The second end of the switch is connected with the output end of the input common mode feedback circuit and the switch is seven S 7 The second terminal of (a) is coupled to the input common mode level. Feedback capacitor two C f2 Respectively connected at the second endsEight closing S 8 A differential amplifier A with an input common mode feedback circuit 1 The inverting output terminal of the differential amplifier.
Load capacitance two C L2 First terminal and self-zeroing capacitor two C AZ2 Is connected to the first end of the first housing. Self-zeroing capacitor C AZ2 The second ends of the two switches are respectively connected with a switch nine S 9 First terminal, switch ten S 10 First end of (2), switch nine S 9 Second terminal of (2) is connected to output common mode level and differential holding capacitor (II C) H2 The second end of (a). Switch ten S 10 Second ends of the first and second capacitors are respectively connected with a capacitor C H2 Differential holding capacitor two C H2 And a signal output terminal.
Because the capacitance Cp cannot be measured accurately, there is always a mismatch between the capacitance Cp and the capacitance dum. Thus, an input common mode feedback circuit is added to the amplifier A1. The input common mode feedback circuit is a three-input folding transconductance amplifier. The output of the ICMFB circuit is coupled back to the input of amplifier A1 via two equal capacitors Cifb1, cifb 2.
Meanwhile, in order to suppress the noise contribution introduced by the subsequent amplifier, the amplifier A1 needs a sufficiently large gain. While amplifier A1 also has as wide an input common mode range as possible.
The working principle of the present embodiment is described in detail below with reference to the switch timing setting, as shown in fig. 2:
switch one S 1 Six S of switch 6 From a clock phi 1 Control, switch two S 2 Seven S of switch 7 And switch three S 3 Eight S switches 8 Controlled by clock RST, switching on or off four S 4 Nine S switch 9 From a clock phi 2 Control, switch five S 5 And a switch ten S 10 From a clock phi 1 And (5) controlling.
Stage 1, zero clearing stage: RST high, clock phi 1 Low level, clock phi 2 High level, switch one S 1 Six S of switch 66 Open, switch two S 2 Seven S of switch 7 And switch three S 3 Eight S switches 8 And a switch four S 4 Nine S switch 9 The closing process is carried out in a closed mode,input common mode feedback capacitor C ifb1 And an input common mode feedback capacitor II C ifb2 A feedback capacitor C f1 A feedback capacitor II C f2 A load capacitor C L1 A load capacitor II C L2 Self-zeroing capacitor-C AZ1 Self-zeroing capacitor two C AZ2 The charge on is cleared.
Stage 2, self-zeroing stage: low level of clock Rst, clock phi 1 Low level, clock phi 2 High level, switch one S 1 And a switch II S 2 And switch three S 3 Six S of switch 6 Seven S of switch 7 Eight S switches 8 Cut off, switch four S 4 Nine S switch 9 And (5) closing. The amplifier constitutes an amplifying circuit. Amplifying the injected charge, amplifier offset, and KT/C noise caused by the MOS switch, storing the amplification result in a self-zeroing capacitor-C AZ1 And self-zeroing capacitor II C AZ2 In (1).
Stage 3, amplification stage: clock phi 1 High level, clock phi 2 Low level. Self-zeroing capacitor-C AZ1 And self-zeroing capacitor II C AZ2 Are disconnected from analog ground and are respectively connected to a differential holding capacitor C H1 A differential holding capacitor II C H2 The current source passes through the closed switch-S 1 Sending the signal into an amplifier for amplification.
In the correlated double sampling technique, the signal is only at the end of phase 3, i.e. at the clock Φ 1 The end of the high level is active, i.e. the active output is embodied in discrete form. This is not conducive to subsequent signal readout, analog-to-digital conversion, and digital processing. Therefore, a pair of differential holding capacitors-C is added at the rear end of the correlated double sampling charge integrator H1 A differential holding capacitor II C H2 The output of the amplifier is converted to a continuous signal.
In the embodiment, the clock adopts an off-chip input square wave clock signal with unknown duty ratio, and comprises a frequency division circuit, a non-overlapping clock generator and a pulse generator with controllable width.
In summary, the invention is based onA related double-sampling weak current integrating circuit with a pseudo differential structure; the charge integrator design with a pseudo-differential structure is adopted to eliminate charge injection and clock feed-through effects existing in the operation of the MOS switch. Meanwhile, the structure can reduce output fluctuation caused by power supply voltage fluctuation. While introducing input common mode feedback in A1 to solve C dum And C p To suppress the amplifier a 1 Common mode ripple at the input and errors due to common mode-to-differential conversion. Using a smaller feedback capacitor C f1 ，C f2 And an amplifier A with larger open loop gain 1 So that the contribution of noise introduced by the subsequent amplifier stage can be suppressed. Amplifier offset and low-frequency noise information are stored by using a correlated double-sampling circuit through a self-return-to-zero capacitor, and weak current is converted into a sampling capacitor CH 1 ,CH 2 The output of the amplifier A1 is converted into a continuous signal.
The invention adopts a relevant double sampling circuit to convert an input current signal into voltage on a holding capacitor, and stores offset and low-frequency noise information of an amplifier through a self-zeroing capacitor. The circuit with the pseudo-differential structure is used for reducing charge injection and clock feed-through effect when the MOS switch works. An input common mode feedback circuit is introduced to restrain common mode fluctuation of the input end of the amplifier A1 and reduce errors caused by common mode-differential mode conversion.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (7)

1. A pseudo-differential structure weak current integrating circuit based on correlated double sampling is characterized by comprising a differential amplifier A with an input common mode feedback circuit 1 Parasitic equivalent capacitance C p Dummy capacitor C dum An input common mode feedback capacitor C ifb1 And an input common mode feedback capacitor II C ifb2 A feedback capacitor C f1 And a feedback capacitor II C f2 Self-zeroing capacitorA C AZ1 Self-zeroing capacitor two C AZ2 A load capacitor C L1 A load capacitor II C L2 Differential holding capacitor-C H1 And a differential holding capacitor II C H2 And a switch I 1 And a switch II S 2 And switch three S 3 And switch four S 4 Switch five S 5 Six S of switch 6 Seven S of switch 7 Eight S of switch 8 Nine S switch 9 And a switch ten S 10 Wherein:
parasitic equivalent capacitance C p Respectively connected with an input current signal and a switch S 1 The first end of (a);
input common mode feedback capacitor C ifb1 The first ends of the first and second switches are respectively connected with a switch S 1 Second terminal of (1), switch two 2 First terminal of (1), feedback capacitance one C f1 With input common mode feedback circuit differential amplifier A 1 The first inverting input end of the input common mode feedback circuit and the non-inverting input end of the differential amplifier; input common mode feedback capacitor C ifb1 Second terminal of the differential amplifier A with an input common mode feedback circuit 1 An output terminal of the input common mode feedback circuit;
feedback capacitor C f1 Second end of (2) is connected with a switch III 3 First terminal, load capacitance C L1 First terminal of (1), self-zeroing capacitor one C AZ1 And a differential amplifier A with an input common mode feedback circuit 1 The non-inverting output terminal of the differential amplifier; switch three S 3 The second terminal of the load capacitor is connected with the output common-mode terminal and the load capacitor is C L1 The second terminal of (a) is grounded;
self-zeroing capacitor-C AZ1 Second end of (2) is connected with a switch IV 4 First terminal of (2), switch five S 5 A first end of (a); switch four S 4 Second terminal of the first and second transistors is connected with an output common mode terminal and a differential holding capacitor C H1 A first end of (a); switch five S 5 Second terminal of (2) is connected to a differential holding capacitor one C H1 A second terminal and a signal output terminal;
dummy capacitor c dum Second terminal of (2) switch six S 6 First terminal of (1), switch six S 6 Second end portion ofConnected with an input common mode feedback capacitor II C ifb2 First end of (1), switch seven S 7 First terminal of (1), feedback capacitance two C f2 A differential amplifier A with an input common mode feedback circuit 1 The second inverting input terminal of the input common mode feedback circuit and the inverting input terminal of the differential amplifier;
input common mode feedback capacitor two C ifb2 The second end of the switch is connected with the output end of the input common mode feedback circuit and the switch is seven S 7 The second terminal of (a) is connected to an input common mode level; feedback capacitor two C f2 The second ends of the two terminals are respectively connected with the switch eight S 8 A differential amplifier A with an input common mode feedback circuit 1 The inverting output terminal of the differential amplifier;
load capacitance two C L2 First terminal and self-zeroing capacitor two C AZ2 Is connected with the first end of the first connecting pipe; self-zeroing capacitor C AZ2 The second ends of the two switches are respectively connected with a switch nine S 9 First terminal, switch ten S 10 First terminal of (1), switch nine S 9 Is connected to the output common mode level and the differential holding capacitor two C H2 A second end of (a); switch ten S 10 Second ends of the first and second capacitors are respectively connected with a capacitor C H2 Differential holding capacitor two C H2 And a signal output terminal.
2. The pseudo-differential structure weak current integrating circuit based on correlated double sampling according to claim 1, wherein: the input common mode feedback circuit is a three-input folded transconductance amplifier.
3. The pseudo-differential structure weak current integrating circuit based on correlated double sampling according to claim 1, wherein: the input common mode feedback capacitor C ifb1 An input common mode feedback capacitor II C ifb2 And (4) symmetrical.
4. The pseudo-differential structure weak current integration circuit based on correlated double sampling according to claim 1, characterized in that: the feedback capacitor C f1 A feedback capacitor II C f2 And (4) symmetrical.
5. The pseudo-differential structure weak current integrating circuit based on correlated double sampling according to claim 1, wherein: the self-zeroing capacitor C AZ1 Self-zeroing capacitor two C AZ2 And (4) symmetrical.
6. The pseudo-differential structure weak current integration circuit based on correlated double sampling according to claim 1, characterized in that: the load capacitor C L1 A load capacitor II C L2 And (4) symmetrical.
7. The pseudo-differential structure weak current integrating circuit based on correlated double sampling according to claim 1, wherein: the differential holding capacitor C H1 A differential holding capacitor II C H2 And (4) symmetrical.
CN202010298601.0A 2020-04-16 2020-04-16 Pseudo-differential structure weak current integrating circuit based on correlated double sampling Active CN111510079B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010298601.0A CN111510079B (en) 2020-04-16 2020-04-16 Pseudo-differential structure weak current integrating circuit based on correlated double sampling

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010298601.0A CN111510079B (en) 2020-04-16 2020-04-16 Pseudo-differential structure weak current integrating circuit based on correlated double sampling

Publications (2)

Publication Number Publication Date
CN111510079A CN111510079A (en) 2020-08-07
CN111510079B true CN111510079B (en) 2022-10-04

Family

ID=71871050

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010298601.0A Active CN111510079B (en) 2020-04-16 2020-04-16 Pseudo-differential structure weak current integrating circuit based on correlated double sampling

Country Status (1)

Country Link
CN (1) CN111510079B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114501264B (en) * 2021-03-31 2023-03-21 西安电子科技大学 Capacitor-voltage converter based on related double amplification technology
CN117220680A (en) * 2023-08-24 2023-12-12 贵州振华风光半导体股份有限公司 Sample hold circuit and analog-to-digital converter
CN118033228B (en) * 2024-04-10 2024-08-02 深圳大学 Microcurrent detection device and microcurrent detection method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104270122B (en) * 2014-09-16 2017-03-29 中国科学院微电子研究所 Duty ratio correction circuit
CN107104648B (en) * 2016-02-19 2019-12-17 深圳市汇顶科技股份有限公司 amplifying circuit
CN107005248B (en) * 2017-02-17 2020-07-28 深圳市汇顶科技股份有限公司 Correlated double sampling integrating circuit
CN208001332U (en) * 2018-01-17 2018-10-23 厦门理工学院 A kind of reading circuit of fully integrated charge coupling device

Also Published As

Publication number Publication date
CN111510079A (en) 2020-08-07

Similar Documents

Publication Publication Date Title
CN111510079B (en) Pseudo-differential structure weak current integrating circuit based on correlated double sampling
US10840862B2 (en) Chopper stabilized amplifier with parallel notch filters
Baschirotto et al. A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing
EP2251977B1 (en) Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers
JP2779267B2 (en) Preamplifier circuit
US7292095B2 (en) Notch filter for ripple reduction in chopper stabilized amplifiers
US9496833B2 (en) Apparatus and methods for multi-channel autozero and chopper amplifiers
US8072262B1 (en) Low input bias current chopping switch circuit and method
US8400339B2 (en) Correlated-level-shifting and correlated-double-sampling switched-capacitor gain stages, systems implementing the gain stages, and methods of their operation
TWI451692B (en) Pseudo differential switched capacitor circuit
US20090273392A1 (en) Methods and apparatus for reducing non-ideal effects in correlated double sampling compensated circuits
US20060197574A1 (en) Auto-zero circuit
US8134401B2 (en) Systems and methods of low offset switched capacitor comparators
US11159170B1 (en) Differential converter with offset cancelation
US10396725B2 (en) Amplifier and reset method thereof
US8004444B2 (en) ADC chopping transconductor having two pairs of cascode transistors
EP3661054B1 (en) Preamplifier circuit with floating transconductor
CN109075755B (en) Distance sensor receiving analog front-end circuit and distance sensor
CN115865082A (en) Analog signal processing circuit and DC offset voltage elimination method
US7888996B1 (en) Chopper stabilized operational amplifier
EP2293434B1 (en) Switched amplifier circuit arrangement and method for switched amplification
CN108199700B (en) High-precision comparator circuit
Wang et al. A fast offset-free sample-and-hold circuit
US20070164888A1 (en) Robust reference generation circuit for A/D converter
US20010020869A1 (en) Class AB single-stage advanced operational amplifier

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 210000, 66 new model street, Gulou District, Jiangsu, Nanjing

Applicant after: NANJING University OF POSTS AND TELECOMMUNICATIONS

Applicant after: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd.

Address before: Yuen Road Ya Dong Qixia District of Nanjing City, Jiangsu province 210000 New District No. 9

Applicant before: NANJING University OF POSTS AND TELECOMMUNICATIONS

Applicant before: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd.

GR01 Patent grant
GR01 Patent grant