CN111510079B - Pseudo-differential structure weak current integrating circuit based on correlated double sampling - Google Patents

Abstract

The invention discloses a pseudo differential structure weak current integrating circuit based on correlated double sampling, which comprises a differential amplifier A with an input common-mode feedback circuit ₁ A parasitic equivalent capacitor C _p A dummy capacitor C _dum Two symmetrical input common-mode feedback capacitors, two symmetrical feedback capacitors, and two symmetrical self-zeroing capacitors. The invention adopts a relevant double sampling circuit to convert an input current signal into voltage on a holding capacitor, and stores offset and low-frequency noise information of an amplifier through a self-zeroing capacitor. A pseudo-differential structure circuit is used for reducing charge injection and clock feed-through effect when the MOS switch works. An input common mode feedback circuit is introduced to restrain common mode fluctuation of the input end of the amplifier A1 and reduce errors caused by common mode-differential mode conversion.

Description

A Pseudo-Differential Weak Current Integrator Circuit Based on Correlated Double Sampling

technical field

The invention designs a CMOS integrated circuit, in particular to a weak current integrating circuit of pseudo-differential structure based on correlated double sampling.

Background technique

When the semiconductor weak current is detected, it is necessary to detect the current of the sub-pA level. The noise of the circuit mainly comes from the following two aspects. One is the noise of the input signal itself, which is often entrained in the weak current signal. At the same time, the amplifier circuit itself also has noise, such as low-frequency 1/f noise. And due to the matching problem of the device itself, there will be an offset voltage in the amplifier circuit.

Correlated double sampling (CDS) technique is used to eliminate low frequency noise and amplifier offset. The correlated double sampling circuit charges and discharges the sampling capacitor through two stages of reset and integration, and obtains the difference between the signal level and the reset level, and uses the auto-zero capacitor (CAZ) to store the offset and low-frequency noise of the amplifier.

But supply voltage fluctuations will introduce output fluctuations due to charge injection and clock feedthrough effects. And in order to increase the anti-interference ability of the circuit, the circuit also needs a large enough common mode rejection ratio. At the same time, the circuit also needs to suppress the noise introduced by the post-amplifier.

SUMMARY OF THE INVENTION

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a pseudo-differential structure weak current integration circuit based on correlated double sampling. In the present invention, in the zero-clearing stage, the capacitor in the circuit is connected to the reset level signal, and the The charge on the capacitor is cleared to zero; secondly, the self-returning capacitor is used to store the offset and low-frequency noise information of the amplifier; in the amplification stage, the current is sent to the amplifier through the closed switch one S ₁ and the switch six S ₆ to amplify the signal. , the invention can effectively avoid charge injection and clock feed-through effects, and has a weak current integrating circuit with strong anti-interference ability. The charge integrator is designed as a pseudo-differential structure to avoid charge injection and clock feed-through effects when MOS switches operate. By introducing the input common mode feedback circuit, a better common mode rejection ratio and power supply rejection ratio can be obtained.

Technical scheme: In order to realize the above-mentioned purpose, the technical scheme adopted in the present invention is:

A pseudo-differential structure weak current integration circuit based on correlated double sampling, comprising a differential amplifier A ₁ with an input common mode feedback circuit, a parasitic equivalent capacitance C _p , a dummy capacitor C _dum , an input common mode feedback capacitor C _ifb1 , an input Common mode feedback capacitor two C _ifb2 , feedback capacitor one C _f1 , feedback capacitor two C _f2 , auto-zero capacitor one C _{AZ1 , auto-zero capacitor two C AZ2 ,} load capacitor one C _L1 , load capacitor two C _L2 , differential hold Capacitor one _CH1 , differential hold capacitor two _CH2 , switch one S ₁ , switch two S ₂ , switch three S ₃ , switch four S ₄ , switch five S ₅ , switch six S ₆ , switch seven S ₇ , switch eight S _8. Switch nine S ₉ , switch ten S ₁₀ , of which:

The first end of the parasitic equivalent capacitance C _p is respectively connected to the input current signal and the first end of the switch-S ₁ .

The first end of input common mode feedback capacitor-C _ifb1 is respectively connected to the second end of switch one S1, the _first end of switch _two S2, the first end of feedback capacitor one C _f1 , and the differential amplifier with input common mode feedback circuit The _first inverting input terminal of the input common mode feedback circuit and the non-inverting input terminal of the differential amplifier in A1. The second end of the input common mode feedback capacitor C _ifb1 is connected to the output end _of the input common mode feedback circuit in the differential amplifier A1 with the input common mode feedback circuit.

The second end of feedback capacitor-C _f1 is connected to the first end of switch _three S3, the first end of load capacitor-C _L1 , the first end of auto-zero capacitor-C _AZ1 and the differential amplifier A with input common mode feedback circuit ₁ in the non-inverting output of the differential amplifier. The second terminal of the switch _three S3 is connected to the output common mode terminal, and the second terminal of the load capacitor one C _L1 is grounded.

The second end of the auto-zero capacitor C _AZ1 is connected to the first end of the switch _four S4 and the first end of the switch _five S5. The second terminal of the switch _four S4 is connected to the output common mode terminal and the first terminal of the differential holding capacitor one _CH1 . The second end of the switch _five S5 is connected to the second end of the differential holding capacitor one C _H1 and the signal output end.

The second end of the dumb capacitor c _dum is connected to the first end of the switch _{six S6} , and the second end of the switch six S6 is respectively connected to the first end of the input common mode feedback capacitor two C _ifb2 , the first end of the switch _seven S7, The first end of the feedback capacitor C _f2 , the second inverting input end _of the input common mode feedback circuit in the differential amplifier A1 with the input common mode feedback circuit, and the inverting input end of the differential amplifier.

The second end of the input common mode feedback capacitor C _ifb2 is connected to the output end of the input common mode feedback circuit, and the second end of the switch _seven S7 is connected to the input common mode level. The second end of the feedback capacitor 2 C _f2 is respectively connected to the first end of the switch 8 S ₈ and the inverting output end of the differential amplifier in the differential amplifier A ₁ with an input common mode feedback circuit.

The first end of the second load capacitor C _L2 is connected to the first end of the second auto-zero capacitor C _AZ2 . The second end of the auto-zero capacitor C _AZ2 is respectively connected to the first end of the switch nine _S9 and the first end of the switch _ten S10, and the second end of the switch _nine S9 is connected to the output common mode level and the differential holding capacitor two C _H2 the second end. The second terminal of the switch _ten S10 is respectively connected to the differential holding capacitor two _CH2 of the capacitor _CH2 and the signal output terminal.

Preferably: the input common mode feedback circuit is a three-input folded transconductance amplifier.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention avoids the charge injection and clock feed-through effects existing in the operation of the MOS switch through the pseudo-differential structure. By introducing the input common mode feedback circuit, a better common mode rejection ratio and power supply rejection ratio can be obtained. At the same time, the correlated double sampling circuit converts the input current signal into the voltage on the differential holding capacitor 1 _CH1 and the differential holding capacitor 2 _CH2 , and the offset and low-frequency noise of the storage amplifier are passed through the auto-zero capacitor 1 C _{AZ1 and the auto-zero capacitor 2 C AZ2 .} information.

Description of drawings

FIG. 1 is a schematic structural diagram of a pseudo-differential structure weak current integrating circuit based on correlated double sampling proposed by the present invention.

FIG. 2 is a switching timing diagram of a pseudo-differential structure weak current integrating circuit based on correlated double sampling proposed by the present invention in an example.

Detailed ways

Below in conjunction with the accompanying drawings and specific embodiments, the present invention will be further clarified. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. Modifications in the form of valence all fall within the scope defined by the appended claims of the present application.

A pseudo-differential structure weak current integrating circuit based on correlated double sampling mainly introduces the amplifier A1 of the input common mode feedback circuit and the correlated double sampling circuit, and the output end of the input common mode feedback circuit is connected with the input end of the correlated double sampling circuit, such as As shown in FIG. 1 , it includes a differential amplifier A ₁ with an input common mode feedback circuit, a parasitic equivalent capacitance C _p , a dummy capacitor C _dum , a symmetrical input common mode feedback capacitor one C _ifb1 and an input common mode feedback capacitor two C _ifb2 , mutually symmetrical feedback capacitor one C _f1 and two feedback capacitors C _f2 , mutually symmetrical auto-zero capacitor one C _AZ1 and two auto-zero capacitor two C _AZ2 , mutually symmetrical load capacitor one C _L1 and load capacitor two C _L2 , Symmetrical differential hold capacitor one C _H1 and differential hold capacitor two C _H2 , switch one S ₁ , switch two S ₂ , switch three S ₃ , switch four S ₄ , switch five S ₅ , switch six S ₆ , switch seven S _7. Switch eight _S8 , switch nine _S9 , switch _ten S10, switch _one S1, switch _two S2, switch _three S3, switch _four S4, switch _five S5, switch six _S6 , switch Seven S ₇ , eight switches S ₈ , nine switches S ₉ , and ten switches S ₁₀ have the same structure. Input common mode feedback (ICMFB) is introduced into amplifier A1, and the input common mode feedback circuit is a one-three-input folding type. Transconductance amplifier, amplifier A1 is a fully differential folded transconductance amplifier, and uses gain bootstrap technology and source degeneration technology to improve its gain, where:

The first end of the parasitic equivalent capacitance _Cp is respectively connected to the input current signal lin and the _first end of the switch-S1.

The first end of input common mode feedback capacitor-C _ifb1 is respectively connected to the second end of switch one S1, the _first end of switch _two S2, the first end of feedback capacitor one C _f1 , and the differential amplifier with input common mode feedback circuit The _first inverting input terminal of the input common mode feedback circuit and the non-inverting input terminal of the differential amplifier in A1. The second end of the input common mode feedback capacitor C _ifb1 is connected to the output end _of the input common mode feedback circuit in the differential amplifier A1 with the input common mode feedback circuit.

The second end of feedback capacitor-C _f1 is connected to the first end of switch _three S3, the first end of load capacitor-C _L1 , the first end of auto-zero capacitor-C _AZ1 and the differential amplifier A with input common mode feedback circuit ₁ in the non-inverting output of the differential amplifier. The second terminal of the switch _three S3 is connected to the output common mode terminal, and the second terminal of the load capacitor one C _L1 is grounded.

The second end of the auto-zero capacitor C _AZ1 is connected to the first end of the switch _four S4 and the first end of the switch _five S5. The second terminal of the switch _four S4 is connected to the output common mode terminal and the first terminal of the differential holding capacitor one _CH1 . The second end of the switch _five S5 is connected to the second end of the differential holding capacitor one C _H1 and the signal output end.

The second end of the dumb capacitor c _dum is connected to the first end of the switch _{six S6} , and the second end of the switch six S6 is respectively connected to the first end of the input common mode feedback capacitor two C _ifb2 , the first end of the switch _seven S7, The first end of the feedback capacitor C _f2 , the second inverting input end _of the input common mode feedback circuit in the differential amplifier A1 with the input common mode feedback circuit, and the inverting input end of the differential amplifier.

The second end of the input common mode feedback capacitor C _ifb2 is connected to the output end of the input common mode feedback circuit, and the second end of the switch _seven S7 is connected to the input common mode level. The second end of the feedback capacitor 2 C _f2 is respectively connected to the first end of the switch 8 S ₈ and the inverting output end of the differential amplifier in the differential amplifier A ₁ with an input common mode feedback circuit.

The first end of the second load capacitor C _L2 is connected to the first end of the second auto-zero capacitor C _AZ2 . The second end of the auto-zero capacitor C _AZ2 is respectively connected to the first end of the switch nine _S9 and the first end of the switch _ten S10, and the second end of the switch _nine S9 is connected to the output common mode level and the differential holding capacitor two C _H2 the second end. The second terminal of the switch _ten S10 is respectively connected to the differential holding capacitor two _CH2 of the capacitor _CH2 and the signal output terminal.

Because the size of the capacitor Cp cannot be accurately measured, there is always a mismatch between the capacitor Cp and the capacitor dum. Therefore, the input common mode feedback circuit is added to the amplifier A1. The input common mode feedback circuit is a three-input folded transconductance amplifier. The output of the ICMFB circuit is coupled back to the input of amplifier A1 through two equal capacitors Cifb1 and Cifb2.

At the same time, in order to suppress the noise contribution introduced by the subsequent amplifier, the amplifier A1 needs a sufficiently large gain. At the same time, amplifier A1 should also have the widest possible input common mode range.

The working principle of this embodiment will be described in detail below in conjunction with the switch timing settings, as shown in Figure 2:

Switch one S ₁ , switch six S ₆ are controlled by clock Φ ₁ , switch two S ₂ , switch seven S ₇ , switch three S ₃ , switch eight S ₈ are controlled by clock RST, switch four S ₄ , switch nine S ₉ are controlled by clock Controlled by _Φ2 , switch _five S5 and switch _ten S10 are controlled by clock _Φ1 .

Stage ₁ , clearing stage: clock RST high level, clock Φ1 low level, clock Φ2 high level, switch _one S1, switch _{six S66 off} , switch _two S2, switch _seven S7, switch Three S ₃ , switch eight S ₈ , switch four S ₄ , switch nine S ₉ are closed, input common mode feedback capacitor one C _ifb1 , input common mode feedback capacitor two C _ifb2 , feedback capacitor one C _f1 , feedback capacitor two C _f2 , The charge on the load capacitor 1 C _L1 , the load capacitor 2 C _L2 , the auto-zero capacitor 1 C AZ1 , and the auto-zero capacitor 2 C _{AZ2 are} cleared to zero.

Stage 2, auto-zero stage: low level of clock Rst, low level of clock Φ ₁ , high level of clock Φ ₂ , switch one S ₁ , switch two S ₂ , switch three S ₃ , switch six S ₆ , switch seven S7, switch _eight S8 is open, switch _four S4, switch _{nine S9} is closed. The amplifier constitutes an amplifying circuit. Amplify the injected charge caused by the MOS switch, the offset of the amplifier, and the KT/C noise, and store the amplified results in the auto-zero capacitor 1 C _AZ1 and the auto-zero capacitor 2 C _AZ2 .

Stage 3, amplification stage: the clock Φ ₁ is at a high level, and the clock Φ ₂ is at a low level. The right ends of the auto-zero capacitor 1 C _AZ1 and the auto-zero capacitor 2 C _AZ2 are disconnected from the analog ground, and are respectively connected to the differential hold capacitor 1 _CH1 and the differential hold capacitor 2 _CH2 , and the current source is sent through the closed switch ₁ S1 into the amplifier for amplification.

In the correlated double sampling technique, the signal is only valid at the end of phase 3, that is, at the end of the high level of the clock Φ ₁ , that is to say, the valid output is embodied in discrete form. This is detrimental to subsequent signal readout, analog-to-digital conversion and digital processing. Therefore, we add a pair of differential holding capacitors to the rear end of the correlated double sampling charge integrator. Differential holding capacitors one _CH1 and two differential holding capacitors _CH2 are used to convert the output of the amplifier into a continuous signal.

In this embodiment, the clock adopts an off-chip input square wave clock signal with unknown duty cycle, which includes a frequency divider circuit by two, a frequency divider circuit by four, a non-overlapping clock generator and a pulse generator with a controllable width.

To sum up, the present invention proposes a pseudo-differential structure weak current integration circuit based on correlated double sampling, and adopts a charge integrator design of pseudo-differential structure to eliminate the charge injection and clock feedthrough effects existing in the MOS switch during operation. At the same time, the structure can also reduce the output fluctuation caused by the fluctuation of the power supply voltage. At the same time, input common mode feedback is introduced in A1 to solve the mismatch between C _dum and C _p , and suppress the common mode fluctuation at the input _of amplifier A1 and the error caused by the common mode-differential mode conversion. Using smaller feedback capacitors C _f1 , C _f2 and amplifier A ₁ with larger open-loop gain can suppress the contribution of noise introduced by subsequent amplifier stages. The correlated double sampling circuit is used to store the amplifier offset and low-frequency noise information by using the auto-zero capacitor, and the weak current is converted into the voltage on the sampling capacitors CH ₁ and CH ₂ , and the output of the amplifier A1 is converted into a continuous signal.

The invention adopts the correlated double sampling circuit to convert the input current signal into the voltage on the holding capacitor, and stores the offset and low-frequency noise information of the amplifier through the self-returning capacitor. A circuit with a pseudo-differential structure is used to reduce the charge injection and clock feedthrough effects when the MOS switch operates. The input common mode feedback circuit is introduced to suppress the common mode fluctuation at the input end of amplifier A1 and reduce the error caused by the common mode-differential mode conversion.

The above is only the preferred embodiment of the present invention, it should be pointed out that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can also be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims (7)

1. a pseudo-differential structure weak current integrating circuit based on correlated double sampling, it is characterized in that: comprise the differential amplifier A ₁ of band input common mode feedback circuit, parasitic equivalent capacitance C _p , dummy capacitance C _dum , input common mode feedback Capacitor one C _ifb1 , input common mode feedback capacitor two C _ifb2 , feedback capacitor one C _f1 , feedback capacitor two C _f2 , auto-zero capacitor one C _{AZ1 , auto-zero capacitor two C AZ2 ,} load capacitor one C _L1 , load capacitor Two C _L2 , a differential hold capacitor C _H1 , a differential hold capacitor two C _H2 , a switch one S ₁ , a switch two S ₂ , a switch three S ₃ , a switch four S ₄ , a switch five S ₅ , a switch six S ₆ , a switch seven S ₇ , switch eight S ₈ , switch nine S ₉ , switch ten S ₁₀ , of which: The first end of the parasitic equivalent capacitance _Cp is respectively connected to the input current signal and the _first end of the switch-S1; The first end of input common mode feedback capacitor-C _ifb1 is respectively connected to the second end of switch one S1, the _first end of switch _two S2, the first end of feedback capacitor one C _f1 , and the differential amplifier with input common mode feedback circuit The _first inverting input terminal of the input common mode feedback circuit and the non-inverting input terminal of the differential amplifier in A1 _; the second terminal of the input common mode feedback capacitor C _ifb1 is connected to the differential amplifier A1 with the input common mode feedback circuit Input the output terminal of the common mode feedback circuit; The second end of feedback capacitor-C _f1 is connected to the first end of switch _three S3, the first end of load capacitor-C _L1 , the first end of auto-zero capacitor-C _AZ1 and the differential amplifier A with input common mode feedback circuit The non-inverting output terminal of the differential amplifier in ₁ ; the second terminal of the switch _three S3 is connected to the output common mode terminal, and the second terminal of the load capacitor one C _L1 is grounded; The second end of the auto-zero capacitor C _AZ1 is connected to the first end of the switch _four S4 and the first end of the switch _five S5; the second end of the switch _four S4 is connected to the output common mode terminal and the differential holding capacitor C _H1 The first end of the switch ₅ S5 is connected to the second end of the differential holding capacitor C _H1 and the signal output end; The second end of the dumb capacitor c _dum is connected to the first end of the switch _{six S6} , and the second end of the switch six S6 is respectively connected to the first end of the input common mode feedback capacitor two C _ifb2 , the first end of the switch _seven S7, The first end of the feedback capacitor C _f2 , the second inverting input end _of the input common mode feedback circuit in the differential amplifier A1 with the input common mode feedback circuit, and the inverting input end of the differential amplifier; The second end of the input common mode feedback capacitor two C _ifb2 is connected to the output end of the input common mode feedback circuit, the second end of the switch _seven S7 is connected to the input common mode level; the second end of the feedback capacitor two C _f2 is respectively connected to the switch eight The first end of _S8 , the inverting output end _of the differential amplifier in the differential amplifier A1 with the input common mode feedback circuit; The first end of the load capacitor 2 C _L2 is connected to the first end of the auto-zero capacitor 2 C _AZ2 ; the second end of the auto-zero capacitor C _AZ2 is respectively connected to the first end of the switch 9 S ₉ and the second end of the switch 10 S ₁₀ . One end, the second end of the switch _nine S9 is connected to the output common mode level and the second end of the differential holding capacitor two _{CH2; the second end of the switch ten S10 is respectively connected to the differential holding capacitor two C H2 of the} capacitor _CH2 and the signal output. 2 . The weak current integrating circuit of pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the input common mode feedback circuit is a three-input folded transconductance amplifier. 3 . 3 . The weak current integrating circuit of pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the input common mode feedback capacitor one C _ifb1 and the input common mode feedback capacitor two C _ifb2 are symmetrical. 4 . 4 . The weak current integrating circuit of pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the feedback capacitor one C _f1 and the feedback capacitor two C _f2 are symmetrical. 5 . 5 . The weak current integration circuit of pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the auto-zero capacitor one C AZ1 and the auto-zero capacitor two C _AZ2 are symmetrical. ₆ . 6 . The weak current integrating circuit of pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the load capacitor one C _L1 and the load capacitor two C _L2 are symmetrical. 7 . 7 . The weak current integrating circuit with pseudo-differential structure based on correlated double sampling according to claim 1 , wherein the differential holding capacitor 1 _CH1 and the differential holding capacitor 2 _CH2 are symmetrical. 8 .

Images