CN111506467B

CN111506467B - Signal processing method, electronic device, and computer-readable storage medium

Info

Publication number: CN111506467B
Application number: CN201910100399.3A
Authority: CN
Inventors: 莫英; 胡军; 周杰
Original assignee: Nokia Shanghai Bell Co Ltd; Nokia Solutions and Networks Oy
Current assignee: Nokia Shanghai Bell Co Ltd; Nokia Solutions and Networks Oy
Priority date: 2019-01-31
Filing date: 2019-01-31
Publication date: 2023-07-11
Anticipated expiration: 2039-01-31
Also published as: CN111506467A

Abstract

Embodiments of the present disclosure relate to a signal processing method, an electronic device, and a computer-readable storage medium. The method implemented on the tested device side comprises the following steps: acquiring a plurality of signals from a plurality of logic modules in a programmable logic device operating in a same clock domain; generating a vector stream comprising a plurality of vectors representing a plurality of signals, respectively; adding timing information to the vector stream indicating a timing at which the plurality of signals are acquired; encapsulating the vector stream to which the timing information is added to generate encapsulated data; and sending the encapsulated data to a remote server for analysis. The method implemented at the remote server side comprises the following steps: receiving the encapsulated data; determining timing information from the package data; determining a vector stream from the encapsulated data based on the timing information; and analyzing the programmable logic device using the vector flow. Therefore, a large number of on-chip signals can be conveniently monitored and acquired, the signal tracking and analyzing capability is enhanced, and the remote analysis can be realized, so that the cost is greatly saved and the convenience is improved.

Description

Signal processing method, electronic device, and computer-readable storage medium

Technical Field

Embodiments of the present disclosure relate to the field of signal processing, and more particularly, to a signal processing method, an electronic device, and a computer-readable storage medium for use in a programmable logic device.

Background

As Field Programmable Gate Array (FPGA) device densities increase, it is impractical to connect probes of test equipment to these devices under test. The capture of on-chip signals has become an effective method of locating device faults.

Traditionally, devices under test are connected to a test environment on a host via a dedicated transducer by using a local joint test group (JTAG) port in the field. The specialized converter and the debug tools used in the test environment will vary from one vendor of the FPGA to another. In addition, the on-chip debug module is mainly composed of the following parts: the JTAG bridge is used for converting the internal parallel interface into a JTAG serial interface; a controller for performing data capture, event triggering, and on-chip management of Random Access Memory (RAM); a capturing unit for capturing a port signal; a trigger port disposed between the capture unit and a controller that performs a trigger function. In this case, a huge block RAM is required to be used to cache the captured data. Furthermore, complex trigger conditions will consume considerable on-chip routing and resources, and a greater number of captured signals and longer monitoring times will also consume a significant amount of on-chip RAM resources.

Disclosure of Invention

In general, embodiments of the present disclosure provide a signal processing method, an electronic device, and a computer-readable storage medium for use in a programmable logic device.

In one aspect of the disclosed embodiments, a signal processing method implemented on a device-under-test side is provided. The method comprises the following steps: acquiring a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in the same clock domain; generating a vector stream comprising a plurality of vectors representing the plurality of signals, respectively; adding timing information to the vector stream, the timing information indicating a timing at which the plurality of signals are acquired; encapsulating the vector stream to which the timing information is added to generate encapsulated data; and sending the encapsulated data to a remote server for analysis of the programmable logic device.

In another aspect of the disclosed embodiments, a signal processing method implemented at a remote server side is provided. The method comprises the following steps: receiving, at a remote server, encapsulated data corresponding to a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in a same clock domain; determining timing information from the package data, the timing information indicating a timing at which the plurality of signals are acquired; determining a vector stream comprising a plurality of vectors representing the plurality of signals, respectively, from the encapsulation data based on the timing information; and performing an analysis of the programmable logic device using the vector stream.

In another aspect of the disclosed embodiments, an electronic device is provided. The apparatus includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to perform the signal processing method implemented on the device-under-test side described above.

In another aspect of the disclosed embodiments, an electronic device is provided. The apparatus includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to perform the signal processing method implemented on the remote server side as described above.

In another aspect of the disclosed embodiments, a computer-readable storage medium is provided. The apparatus comprises machine executable instructions which, when executed by the apparatus, cause the apparatus to perform the signal processing method implemented on the device under test side as described above.

In another aspect of the disclosed embodiments, a computer-readable storage medium is provided. This includes machine executable instructions which, when executed by a device, cause the device to perform the signal processing method implemented on the remote server side as described above.

According to the scheme of the embodiment of the disclosure, a large number of on-chip signals can be conveniently monitored and acquired, so that the signal tracking and analyzing capability can be enhanced. In addition, the acquired on-chip signals can be transmitted to a remote server through a network, so that signal tracking and analysis can be remotely performed, thereby greatly saving cost and improving convenience.

It should be understood that the description in this summary is not intended to limit key or critical features of the disclosed embodiments, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 illustrates a schematic diagram of an exemplary scenario in which embodiments of the present disclosure may be implemented;

FIG. 2 illustrates a flow chart of a signal processing method implemented at a device under test according to an embodiment of the disclosure;

FIG. 3 shows a schematic diagram of an example signal processing process implemented at a device under test, according to an embodiment of the disclosure;

FIG. 4 shows a schematic diagram of an interleaving process according to an embodiment of the present disclosure;

fig. 5 shows a flowchart of a signal processing method implemented at a remote server side according to an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of an example signal processing process implemented at a remote server side according to an embodiment of the disclosure; and

fig. 7 shows a schematic block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the embodiments of the present disclosure have been illustrated in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

The term "circuitry" as used herein refers to one or more of the following:

(a) Hardware-only circuit implementations (such as analog-only and/or digital-circuit implementations); and

(b) A combination of hardware circuitry and software, such as (if applicable): (i) A combination of analog and/or digital hardware circuitry and software/firmware, and (ii) any portion of a hardware processor and software (including digital signal processors, software, and memory that work together to cause an apparatus, such as an Optical Line Terminal (OLT) or other computing device, to perform various functions); and

(c) Hardware circuitry and/or a processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but may not have software when software is not required for operation.

The definition of circuit applies to all scenarios in which this term is used in this application, including in any claims. As another example, the term "circuitry" as used herein also covers an implementation of only a hardware circuit or processor (or multiple processors), or a portion of a hardware circuit or processor, or its accompanying software or firmware. For example, if applicable to the particular claim element, the term "circuitry" also covers a baseband integrated circuit or processor integrated circuit or similar integrated circuit in an OLT or other computing device.

The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". Related definitions of other terms will be given in the description below.

In the aforementioned conventional scheme for on-chip signal acquisition, JATG ports are employed as data and controller local ports. It is often necessary to use fly-wire solder JATG ports so FPGA designers must be field supported in the field for debugging. To capture critical signals, it is often necessary to destroy the existing test environment, i.e., destroy the fault scenario. In some cases, fault reproduction is very time consuming. Thus, the conventional solution is very inflexible and cannot work remotely. Furthermore, the JATG port is a specific low-speed serial port, which directly results in inefficiency of the debugging process.

In addition, in conventional schemes, several tools and complex steps are required to obtain the exact network name of the target signal from the optimization hierarchy, set up valid test vectors, download bits to the circuit under test, and capture the signal waveform. This still does not include normal FPGA development steps. In most cases, the time of the compiling step is even doubled. Therefore, the workflow of the conventional scheme is very complex.

As mentioned previously, different FPGA vendors have different debug tools and procedures that are incompatible with each other and very cumbersome and difficult to use. In many cases, even the same tool from the same vendor cannot be used for different device families. Thus, the debugging tools and procedures used in conventional schemes are not compatible.

Furthermore, in conventional schemes, signals in only one clock domain can be captured simultaneously. The frequency of the operating clock cannot be too fast due to the limited FPGA capability. Typically, 150MHz reaches almost a critical value. Thus, merely increasing the frequency to process signals from different clock domains would not solve this problem. By conventional methods, signals of different clock domains cannot be compared or analyzed simultaneously on a screen.

Moreover, the operating mechanism of the conventional scheme relies on-chip RAM capacity. Since on-chip RAM resources are very limited, no more captured data can be recorded. This severely limits the ability to debug complex problems.

In summary, due to the complex procedures, inflexible modes of operation, various incompatible interfaces and tools, traditional solutions cannot work in complex debug environments nor can they work remotely, especially when faced with complex problems in large systems, such as multiple time domains, across chips, across cards, across racks, and even across sites. In this case, large data of a large number of signals over a large time span needs to be obtained, and a more complex calculation model should be used. All of this is difficult to achieve with conventional schemes that rely primarily on FGPA on-chip resources. In addition, due to the physical limitation of the FPGA, the working clock does not exceed 200MHz, the size of the on-chip RAM is very small, and the traditional oversampling method cannot compare multiple time domain signals and analyze large data.

In view of this, the present inventors propose an improved signal processing scheme that allows a large number of on-chip signals to be monitored and acquired easily, and the acquired on-chip signals can be transmitted to a remote server over a network. Thus, the signal tracking and analyzing capability can be enhanced, and the signal tracking and analyzing can be performed remotely, thereby greatly saving the cost and improving the convenience. This is described in more detail below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic diagram of an exemplary scenario 100 in which embodiments of the present disclosure may be implemented. Fig. 1 shows devices under

test

110 and 120. The devices under

test

110 and 120 may be programmable logic devices such as FPGAs, complex Programmable Logic Devices (CPLDs), and the like. It should be appreciated that devices under

test

110 and 120 may be any suitable programmable logic device known in the art or developed in the future. The devices under

test

110 and 120 may be arranged on any same or different circuit board (not shown) and need not be removed during testing, i.e., the testing environment need not be destroyed. Accordingly, no trouble reproduction is required, thereby improving the convenience of the test.

As shown in fig. 1, the device under test 110 may include

logic modules

111, 112, 113, 114. In this example, the

logic modules

111, 112 operate in a first clock domain and the

logic modules

113, 114 operate in a second clock domain that is different from the first clock domain. The device under test 120 may include

logic modules

121, 122, 123, 124. In this example, logic blocks 121, 122 operate in a third clock domain and logic blocks 123, 124 operate in a fourth clock domain that is different from the third clock domain. It should be appreciated that any of devices under

test

110 and 120 may include a greater or lesser number of logic modules, and is not limited to the four shown in FIG. 1. And it should be understood that the logic modules in devices under

test

110 and 120 may operate in a greater or lesser number of clock domains, and are not limited to the two clock domains listed herein. Although fig. 1 only shows devices under

test

110 and 120, it should be understood that embodiments of the present disclosure may be applicable in scenarios involving fewer or greater numbers of devices under test.

In embodiments of the present disclosure, devices under

test

110 and 120 may be located in the same or different geographic locations. For example, device under test 110 may be located at a sender in a communication system, while device under test 120 may be located at a receiver in the communication system. As shown in fig. 1, signals of devices under

test

110 and 120 in operation may be captured and transmitted to remote server 130 over network 120 in accordance with embodiments of the present disclosure.

The network 120 may be a communication network or communication channel based on various generic interfaces. Common interfaces such as Central Processing Unit (CPU) local bus, ethernet, peripheral Component Interconnect Express (PCIE), etc. The remote server 130 may be a host, computing device, monitor terminal, or the like. The remote server 130 may perform various tests and analyses on the devices under

test

110 and 120.

Fig. 2 shows a flowchart of a signal processing method 200 implemented on the device-under-test side according to an embodiment of the present disclosure. The method 200 may be implemented, for example, at the device under test 110 of fig. 1.

As shown in fig. 2, at block 210, a plurality of signals from a plurality of logic blocks (e.g., logic blocks 111-112, or 113-114) in a programmable logic device (e.g., device under test 110) are acquired, the plurality of logic blocks operating in the same clock domain (e.g., a first clock domain, or a second clock domain). Fig. 3 shows a schematic diagram of an example signal processing procedure 300 implemented on the device-under-test side according to an embodiment of the disclosure. The process 300 may be implemented, for example, at the device under test 110 of fig. 1. As shown in FIG. 3, logic blocks 111-112 operate in a first clock domain 301 and logic blocks 113-114 operate in a second clock domain 302.

In an embodiment of the present disclosure, the signals of the respective logic modules may be acquired in response to a monitoring request from the outside. In alternative embodiments, the signal of the predetermined logic module may be periodically acquired. According to embodiments of the present disclosure, signals from logic modules in device under test 110 may be captured without interrupting the operation of device under test 110. Thereby, a direct debugging of the signal in case of a fault as well as monitoring of the signal in case of a normal situation can be achieved.

At block 220, a vector stream is generated that includes a plurality of vectors that respectively represent a plurality of signals. In embodiments of the present disclosure, for each of a plurality of signals, a vector representing the signal may be generated. A vector stream is generated by combining these generated vectors. It will be appreciated that the vector stream corresponds to a particular clock domain. For example, as shown in fig. 3, vector 303 may be generated for signals from logic module 111 and vector 304 may be generated for signals from logic module 112.

Vectors

303 and 304 may then be combined into vector stream 307. Similarly, vector 305 may be generated for signals from logic module 113 and vector 306 may be generated for signals from logic module 114.

Vectors

305 and 306 may then be combined into vector stream 308. It should be appreciated that the vectors and combined vectors may be generated in any suitable manner known in the art or developed in the future and are not described in detail herein to avoid obscuring the present invention.

At block 230, timing information is added to the vector stream, the timing information indicating the timing at which the plurality of signals were acquired. In embodiments of the present disclosure, a system time stamp (system time) is introduced to define a uniform time unit and time precision to facilitate management of signals from different clock domains, considering that there may be multiple clock domains in and between devices under test.

In embodiments of the present disclosure, timing information may be added to the vector stream based on the system time stamp. In one embodiment, a respective time code may be added to each vector in the vector stream by a time code generator generating a time code stream indicative of the timing information and interleaving the time code stream with the vector stream. As shown in fig. 3, for the first clock domain 301, a time code stream is generated by a time code generator 309 in synchronization with the system time stamp, and the time code stream is interleaved 311 with the vector stream 307, thereby adding a corresponding time code for each

vector

303 and 304. Similarly, for the second clock domain 302, a time code stream is generated by a time code generator 310 in synchronization with the system time stamp, which is interleaved 312 with the vector stream 308, adding a corresponding time code for each

vector

305 and 306. Described in more detail below in conjunction with fig. 4.

Fig. 4 shows a schematic diagram of an interleaving process 400 according to an embodiment of the disclosure. As shown in fig. 4, a time code stream is generated by a time code generator 309 in synchronization with a time stamp 401 generated by a system clock, and the time code stream is interleaved 311 with a vector stream 303 to obtain an interleaved stream 402. Similarly, a time code stream is generated by a time code generator 310 in synchronization with a system time stamp 401, which is interleaved 312 with a vector stream 304, resulting in an interleaved stream 403. Both the interleaved stream 402 and the interleaved stream 403 are synchronized with the system time stamp 401 at point in time 404.

A clock domain requires a time code generator that continuously generates a time code stream. In one embodiment, the time code stream may be periodically generated to introduce timing information into the vector stream. Thus, it is possible to avoid increasing the operating frequency beyond the capability of the device under test and to record a large amount of captured data locally. This allows easy comparison of multiple time domain signals and analysis of large data. In alternative embodiments, the time code stream may also be a random code stream.

According to embodiments of the present disclosure, the time code format may be very flexible. In one embodiment, the time code may include a preamble, a time minute second, a synchronization count, and a sub-synchronization count. The preamble may be used to identify a time code field. Time minutes and seconds may be used to record time information. The sync count may be used to record the phase of a system time stamp that marks the system synchronization point, which is shown as 404 in fig. 4. At this point in time, all clocks used in the system are in phase. The sub-sync count may be used to distinguish the order of the encapsulated data. In another embodiment, the time code may also end with system configuration information. System configuration information such as clock domain Identification (ID), frequency information, management code, and the like. It should be appreciated that embodiments of the present disclosure are not so limited, as any other suitable form of timing information may be employed to synchronize between vector streams in different clock domains.

Returning to fig. 2, at block 240, the vector stream with the timing information added is encapsulated to generate encapsulated data. According to an embodiment of the present disclosure, a stream slicing process may be performed on a vector stream to which timing information is added to obtain a plurality of slice data. Each slice data of the plurality of slice data is configured in a predetermined format to generate corresponding encapsulated data.

As shown in fig. 3, the vector stream subjected to the stream slicing process 313 is divided into a plurality of slice data. And encapsulating each slice of data into encapsulated data according to an encapsulation format required by network transmission. Such as ethernet encapsulation format, PCIE encapsulation format, etc. The resulting plurality of encapsulated data is placed into a queue buffer 315 to await scheduling. Similarly, the vector stream subjected to the stream slicing process 314 is divided into a plurality of slice data, and packaged into packaged data in a predetermined format, and then put into the queue buffer 316 to wait for scheduling.

At block 250, the encapsulated data is sent to a remote server (e.g., remote server 130 of FIG. 1) for analysis of the programmable logic device. In embodiments of the present disclosure, the encapsulated data may be sent to a remote server over any suitable network (e.g., network 120 of fig. 1). In embodiments of the present disclosure, the transmission of the encapsulated data may be performed in the form of a stream by scheduling between the encapsulated data of different clock domains. As shown in fig. 3, the encapsulated data is sent via a schedule 317 between a queue buffer 315 corresponding to the first clock domain 301 and a queue buffer 316 corresponding to the second clock domain 302. For example, in response to scheduling for the queue buffer 315, the encapsulated data in the queue buffer 315 is placed in a first-in-first-out (FIFO) manner into the transmit buffer 318 to await transmission. Similarly, in response to scheduling for queue buffer 316, encapsulated data in queue buffer 316 is also placed into transmit buffer 318 to await transmission. Accordingly, the encapsulated data in the transmit buffer 318 will be transmitted stepwise to the remote server 130 in a FIFO manner over the network 120.

According to the signal processing method of the embodiment of the present disclosure, since captured signal data is managed and transmitted in the form of a stream, interleaved stream data is converted in a continuous manner rather than a burst mode, and thus the buffer size can be very small. In addition, since the interleaved stream data can be transmitted to the remote server using various general interfaces such as a CPU bus, ethernet, PCIE, etc., the debugging process can be speeded up, the debugging cost can be saved, and various vendor tools can be independently used, thereby greatly promoting compatibility and convenience. In addition, the captured data will be stored on a remote server rather than in the programmable logic device local RAM, thus saving local RAM storage. At the same time, the amount of captured data can be very large and can be grouped, sliced, and ordered in various ways, whereby an interactive analysis of the polishing waveform, curve, and even real-time data can be created.

A signal processing method implemented at a remote server side according to an embodiment of the present disclosure is described below with reference to fig. 5 and 6. Fig. 5 shows a flowchart of a signal processing method 500 implemented at a remote server side according to an embodiment of the present disclosure. The method 500 may be implemented, for example, at the remote server 130 of fig. 1.

As shown in fig. 5, at block 510, package data is received that corresponds to a plurality of signals from a plurality of logic modules in a programmable logic device that operate in a same clock domain. Corresponding to the process described in fig. 2 and 3, the encapsulated data from the device side under test will be received at the remote server 130 over the network.

At block 520, timing information is determined from the package data, the timing information indicating a timing at which the plurality of signals were acquired. According to an embodiment of the present disclosure, the encapsulated data is parsed according to a network transmission format, thereby obtaining sliced data. The slice data corresponds to a portion of a vector stream including a plurality of vectors representing the plurality of signals to which timing information is added. For example, slice data is parsed based on a time code format to determine timing information.

At block 530, a vector stream including a plurality of vectors respectively representing the plurality of signals is determined from the encapsulation data based on the timing information. According to an embodiment of the present disclosure, slice data parsed from the package data is placed into a queue buffer corresponding to a corresponding clock domain based on timing information. Thus, vectors belonging to the same clock domain will be allocated to the same queue buffer. Thus, from the queue buffer, a vector flow can be determined.

Fig. 6 shows a schematic diagram of an example signal processing procedure 600 implemented on the remote server 130 side, according to an embodiment of the disclosure. As shown in fig. 6, the remote server 130 may receive 601 the encapsulated data. Slice data and timing information are determined by parsing 602 the encapsulated data. From the timing information, a clock domain may be determined and slice data placed into a queue buffer corresponding to the clock domain among the queue buffers 603-606. In this example, queue buffers 603 and 604 correspond to

vector streams

307 and 308, respectively, of FIG. 3. Thus, vector streams 307 and 308 may be retrieved from

queue buffers

603 and 604.

According to an embodiment of the present disclosure, the vector stream determined at block 530 may be stored. For example, as shown in FIG. 6, the obtained vector stream may be recorded 607 as a file for subsequent use. In one embodiment, the vector stream may be stored locally in an internal memory of the remote server 130. In an alternative embodiment, the vector stream may be stored in an external memory associated with the remote server 130. The embodiments of the present disclosure are not limited in this regard. Compared with the traditional scheme, according to the embodiment of the disclosure, the captured data can be stored at the remote server without storing a large amount of data in the limited storage space of the device under test, so that the storage space of the device under test can be greatly saved, and the test convenience is improved.

As shown in fig. 5, at block 540, an analysis of a programmable logic device (e.g., device under test 110) may be performed using vector flow. According to the processing of blocks 510-530 described above, a plurality of different vector streams (e.g., different vector streams in queue buffers 603-606) may be obtained for different clock domains. These vector streams represent all of the signal data captured from the device under test and can be used for various tests and analyses.

In one embodiment, a first vector stream and a second vector stream corresponding to a first clock domain and a second clock domain, respectively, may be obtained from a plurality of vector streams; aligning the timelines of the first and second vector streams; interpolating the first vector stream and the second vector stream based on the first clock domain and the second clock domain, respectively; and presenting a first signal and a second signal corresponding to the interpolated first vector stream and the interpolated second vector stream. So that a comparative analysis is performed between the first signal and the second signal.

For example, as shown in fig. 6, the time lines of the vector streams of the different clock domains may be aligned 609 based on the synchronization count in the timing information, and the interpolation process of the vector streams of the different clock domains is completed using the frequency information and the sub-synchronization count in the timing information. The interpolated vector stream is converted into waveforms by graphics driver 610 for presentation 611. And further can perform comparison analysis between different waveform groups.

It should be understood that the disclosed embodiments are not limited to this form, but rather may utilize vector flow for analysis in any other suitable manner. For example, as shown in FIG. 6, the acquired vector streams may be sent to a conventional analysis tool 608, such as ModelSim, matLab, etc., to perform analysis. By using resources on a remote server, very large captured data can be recorded and very complex analysis can be implemented, such as complex protocol self-analysis, eigenvalue analysis collected from multiple cards of the whole system, and various transformation analysis (FFT/Laplace/Z/wavelet, etc.).

It can be seen that the signal processing method of the embodiment of the present disclosure fully utilizes the powerful functions of the remote server in terms of both hardware and software. At the same time, it reduces the consumption of on-chip resources for implementing more user functions. In addition, the implementation of the method can more easily use existing generic IP, popular statistics and analysis tools, AI extension libraries, etc. Therefore, the method has good compatibility and convenience.

Corresponding to the method, the embodiment of the disclosure also provides a corresponding device. The apparatus capable of performing the method 200 may include corresponding means for performing the various steps of the method 200. These components may be implemented in any suitable manner. For example, it may be implemented by a circuit or a software module. In some embodiments, the apparatus may be implemented on a device under test (on-chip). In alternative embodiments, it may also be implemented by externally attaching to the device under test.

In some embodiments, an apparatus may include means for acquiring a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in a same clock domain; means for generating a vector stream comprising a plurality of vectors representing the plurality of signals, respectively; means for adding timing information to the vector stream, the timing information indicating a timing at which the plurality of signals are acquired; means for encapsulating the vector stream to which the timing information is added to generate encapsulated data; and means for sending the encapsulated data to a remote server for analysis of the programmable logic device.

In some embodiments, the means for adding the timing information comprises: means for generating a time code stream indicative of the timing information by a time code generator; and means for interleaving the time code stream with the vector stream to add a respective time code for each vector in the vector stream.

In some embodiments, the means for generating the encapsulation data comprises: means for performing stream slicing processing on the vector stream to which the timing information is added to obtain a plurality of slice data; and means for configuring each slice data of the plurality of slice data in a predetermined format to generate corresponding encapsulated data.

In some embodiments, the means for transmitting the encapsulated data comprises: means for placing the encapsulated data in a queue buffer corresponding to the clock domain; and means for sending the encapsulated data to the remote server in response to scheduling between different queue buffers corresponding to different clock domains.

In some embodiments, the programmable logic device is an FPGA.

Additionally, an apparatus capable of performing the method 500 may include corresponding means for performing the various steps of the method 500. These components may be implemented in any suitable manner. For example, it may be implemented by a circuit or a software module. The apparatus may be implemented at a remote server.

In some embodiments, an apparatus comprises: means for receiving encapsulated data, the encapsulated data corresponding to a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in a same clock domain; means for determining timing information from the package data, the timing information indicating a timing at which the plurality of signals are acquired; means for determining a vector stream comprising a plurality of vectors representing the plurality of signals, respectively, from the encapsulation data based on the timing information; and means for performing an analysis of the programmable logic device using the vector stream.

In some embodiments, the means for determining the timing information comprises: means for parsing the encapsulated data to determine slice data; and means for determining the timing information from the slice data.

In some embodiments, the means for determining the vector stream comprises: means for placing the slice data into a queue buffer corresponding to the clock domain based on the timing information; and means for determining the vector flow from the queue buffer.

In some embodiments, the apparatus further comprises: means for storing the vector stream.

In some embodiments, the means for performing the analysis comprises: means for obtaining a second vector flow corresponding to a second clock domain different from the clock domain; means for aligning the time lines of the vector stream and the second vector stream; means for performing a corresponding interpolation process on the vector stream and the second vector stream based on the clock domain and the second clock domain, respectively; and means for presenting signals corresponding to the interpolated vector stream and the second vector stream, respectively.

In some embodiments, the programmable logic device is an FPGA.

Fig. 7 illustrates a schematic block diagram of an electronic device 700 suitable for implementing embodiments of the present disclosure. The apparatus 700 may be used to implement the device under test and the remote server itself or a portion thereof in accordance with embodiments of the present disclosure.

As shown, device 700 may include one or more processors 710, one or more memories 720 coupled to processors 710, and one or more transmitters and/or receivers (TX/RX) 740. Processor 710 and memory 720 form a processing means 750 for causing implementation of embodiments of the present disclosure. TX/RX 740 is coupled to processing device 750.

Processor 710 may be of any suitable type suitable to the local technical environment and may include, but is not limited to, one or more of a general purpose computer, a special purpose computer, a microcontroller, a digital signal controller (DSP), and a processor based on a multi-core processor architecture. The device 700 may have multiple processors, such as an application specific integrated circuit chip that is slaved in time to a clock that is synchronized to the master processor.

Memory 720 may be of any suitable type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as non-transitory computer readable storage media, semiconductor-based storage devices, magnetic storage devices and systems, optical storage devices and systems, fixed memory, and removable memory, as non-limiting examples.

Memory 720 stores at least a portion of program 730. TX/RX 740 is used for two-way communication. TX/RX 740 has at least one antenna to facilitate communications, but in practice the device may have several antennas. The communication interface may represent any interface required to communicate with other network elements.

Program 730 may include program instructions that, when executed by an associated processor 710, enable device 700 to operate in accordance with embodiments of the present disclosure, as described with reference to fig. 2-6. That is, embodiments of the present disclosure may be implemented by computer software executable by the processor 710 of the device 700, or by hardware, or by a combination of software and hardware.

In general, the various example embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof. Examples of hardware devices that may be used to implement embodiments of the present disclosure include, but are not limited to: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.

By way of example, embodiments of the present disclosure may be described in the context of machine-executable instructions, such as program modules, being included in devices on a real or virtual processor of a target. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between described program modules. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed device, program modules may be located in both local and remote memory storage media.

Computer program code for carrying out methods of the present disclosure may be written in one or more programming languages. These computer program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the computer or other programmable data processing apparatus, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of this disclosure, computer program code or related data may be carried by any suitable carrier to enable an apparatus, device, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

Examples of signals may include electrical, optical, radio, acoustical or other form of propagated signals, such as carrier waves, infrared signals, etc.

A machine-readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a machine-readable storage medium include an electrical connection with one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

In addition, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking or parallel processing may be beneficial. Likewise, although the foregoing discussion contains certain specific implementation details, this should not be construed as limiting the scope of any invention or claims, but rather as describing particular embodiments that may be directed to particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A signal processing method, comprising:

acquiring a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in the same clock domain;

generating a plurality of vectors representing the plurality of signals, respectively;

generating a vector stream by merging the plurality of vectors;

adding timing information to the vector stream, the timing information indicating a timing at which the plurality of signals are acquired;

encapsulating the vector stream to which the timing information is added to generate encapsulated data; and

the encapsulated data is sent to a remote server for analysis of the programmable logic device.

2. The method of claim 1, wherein adding the timing information comprises:

generating a time code stream indicating the timing information by a time code generator; and

the time code stream is interleaved with the vector stream to add a respective time code for each vector in the vector stream.

3. The method of claim 1, wherein generating the package data comprises:

performing stream slicing processing on the vector stream added with the time sequence information to obtain a plurality of slice data; and

Each slice data of the plurality of slice data is configured in a predetermined format to generate corresponding encapsulated data.

4. The method of claim 1, wherein transmitting the encapsulated data comprises:

placing the encapsulated data into a queue buffer corresponding to the clock domain; and

the encapsulated data is sent to the remote server in response to scheduling between different queue buffers corresponding to different clock domains.

5. The method of claim 1, wherein the programmable logic device is a Field Programmable Gate Array (FPGA).

6. A signal processing method, comprising:

receiving, at a remote server, encapsulated data corresponding to a plurality of signals from a plurality of logic modules in a programmable logic device, the plurality of logic modules operating in a same clock domain;

determining timing information from the package data, the timing information indicating a timing at which the plurality of signals are acquired;

determining a vector stream comprising a plurality of vectors representing the plurality of signals, respectively, from the encapsulation data based on the timing information; and

and analyzing the programmable logic device by using the vector flow.

7. The method of claim 6, wherein determining the timing information comprises:

analyzing the encapsulation data to determine slice data; and

the timing information is determined from the slice data.

8. The method of claim 7, wherein determining the vector stream comprises:

based on the time sequence information, placing the slice data into a queue buffer corresponding to the clock domain; and

the vector flow is determined from a queue buffer.

9. The method of claim 6, further comprising:

the vector stream is stored.

10. The method of claim 6, wherein performing the analysis comprises:

acquiring a second vector flow corresponding to a second clock domain different from the clock domain;

aligning the time lines of the vector stream and the second vector stream;

performing corresponding interpolation processing on the vector stream and the second vector stream based on the clock domain and the second clock domain respectively; and

signals respectively corresponding to the interpolated vector stream and the second vector stream are presented.

11. The method of claim 6, wherein the programmable logic device is a Field Programmable Gate Array (FPGA).

12. An electronic device, comprising:

a processor; and

a memory coupled with the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to:

generating a vector stream by merging the plurality of vectors;

13. The apparatus of claim 12, wherein adding the timing information comprises:

14. The apparatus of claim 12, wherein generating the package data comprises:

15. The apparatus of claim 12, wherein transmitting the encapsulated data comprises:

16. The apparatus of claim 12, wherein the programmable logic device is a Field Programmable Gate Array (FPGA).

17. An electronic device, comprising:

a processor; and

and analyzing the programmable logic device by using the vector flow.

18. The apparatus of claim 17, wherein determining the timing information comprises:

analyzing the encapsulation data to determine slice data; and

the timing information is determined from the slice data.

19. The apparatus of claim 18, wherein determining the vector flow comprises:

the vector flow is determined from a queue buffer.

20. The apparatus of claim 17, the acts further comprising:

the vector stream is stored.

21. The apparatus of claim 17, wherein performing the analysis comprises:

aligning the time lines of the vector stream and the second vector stream;

22. The apparatus of claim 17, wherein the programmable logic device is a Field Programmable Gate Array (FPGA).

23. A computer readable storage medium comprising machine executable instructions which, when executed by a device, cause the device to perform the method of any of claims 1-5.

24. A computer readable storage medium comprising machine executable instructions which, when executed by a device, cause the device to perform the method of any of claims 6-11.