CN111506448B - Rapid reconstruction method of two-dimensional processor array - Google Patents
Rapid reconstruction method of two-dimensional processor array Download PDFInfo
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Abstract
The invention discloses a quick reconstruction method of a two-dimensional processor array, which comprises the steps of defining the partial order relation and the interval of a logic column, constructing an initial logic column, defining an unavailable processor unit, constructing a subsequent logic column, correcting the unconnected processor unit and constructing the maximum logic array. The flexible method for rapidly reconstructing the two-dimensional processor array constructs the local optimal logic array in the interval in sequence from left to right through the idea of dynamic planning, so that the maximum logic array is generated in polynomial time, the utilization rate of a processor unit without faults in the processor is improved to the maximum extent, and the stability of a system is greatly improved. Experimental verification shows that the proposed method can generate a larger logic array rapidly compared to the prior art.
Description
Technical Field
The invention relates to the technical field of reconstruction arrays, in particular to a rapid reconstruction method of a two-dimensional processor array.
Background
With the increasing demands of large-scale data processing on system processor performance, it has been difficult for conventional single-processor systems to meet the ever-increasing demands for high-density computing processing. Theoretical research on multiprocessor systems has been advanced in recent years, and with the rapid development of nanotechnology and the continuous progress of semiconductor processes, a large number of homogeneous Processing units (PEs) can be integrated on a single chip or silicon wafer to constitute an efficient and stable multiprocessor system.
However, as Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) technologies and technologies continue to develop and mature, the integration density of electronic systems continues to increase, the structures and functions become increasingly complex, the number of integrated processing units on a single chip exponentially increases, the possibility of defects in the array production process increases, and as the applications become increasingly complex, the demand increases, so that the probability of errors occurring in the processor units during use increases, and the failed processor units will affect the reliability of the entire system. Therefore, there is a need for an efficient fault tolerant technique for reconfiguring Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) processor arrays containing failing processor units to fully exploit the system and improve the system reliability.
Disclosure of Invention
The invention aims to solve the problem that the reliability of the whole system is influenced by a fault processor unit of the conventional processor array, and provides a quick reconstruction method of a two-dimensional processor array.
In order to solve the problems, the invention is realized by the following technical scheme:
a fast reconstruction method of a two-dimensional processor array comprises the following steps:
step 1: constructing an initial logic column C 1 Namely:
step 1.1, forming the first physical column of the current physics into an initial preprocessing logic column P _ C 1 ：
If the initial pre-processing logic row P _ C 1 If the number f of the middle fault-free processor units is more than or equal to k, the logic column P _ C is preprocessed from the beginning 1 Selecting k non-fault processor units to form an initial logic column C 1 ；
If the initial pre-processing logic row P _ C 1 If the number f of the processor units without faults is less than k, turning to the step 1.2;
step 1.2, compare initial pre-processing logic column P _ C 1 And selecting the fault processor unit with the smallest k-f physical column indexes to perform in the range of the current physical arrayCompensation;
step 1.3, from the compensated initial preprocessed logic sequence P _ C 1 Selecting k non-fault processor units to form an initial logic column C 1 ；
Step 1.4, start logic column C 1 Arranging the k fault-free processor units according to a set priority rule; and will participate in constructing the initial logical column C 1 The k fault-free processor units are removed from the current physical array;
step 2, based on the ith logic column C i Constructing the i +1 th logic column C i+1 Namely:
step 2.1, all processor units on the right side of the ith physical column are selected from the current physical array to form an i +1 th preprocessing logic column P _ C i+1 ：
If the i +1 st preprocessed logic row P _ C i+1 If the number f of the non-fault processor units is more than or equal to k, the logic column P _ C is preprocessed from the i +1 th i+1 Selecting k non-fault processor units to form the (i + 1) th logic column C i+1 ；
If the i +1 th preprocessed logic row P _ C i+1 If the number f of the fault-free processor units is less than k, then the step 2.2 is carried out;
step 2.2, the i +1 th preprocessing logic column P _ C i+1 Corresponding physical column as left boundary C l Then find the i +1 th preprocessed logic column P _ C i+1 The first non-faulty processor element to the right of all faulty processor elements in the cluster, and by comparing the physical column indices of these non-faulty processor elements, the physical column in which the non-faulty processor element with the largest physical column index is located is taken as the right boundary C r Obtaining the range of the current boundary interval;
step 2.3, compare the i +1 th preprocessing logic column P _ C i+1 Selecting the fault processor unit with the smallest k-f physical column indexes to compensate in the current boundary interval range;
step 2.4, from the compensated i +1 th preprocessed logic column P _ C i+1 Selecting k fault-free processor sheetsThe elements form the (i + 1) th logic column C i+1 ；
Step 2.5, the (i + 1) th logic column C i+1 Arranging the k fault-free processor units according to a set priority rule; and will participate in the construction of the (i + 1) th logical column C i+1 The k non-faulty processor elements are removed from the current physical array;
step 3, judging whether the number of the residual fault-free processor units on the current physical array is more than or equal to the number k of the fault-free processor units in the set logic array: if yes, returning to the step 2; otherwise, go to step 4;
step 4, forming all the constructed logic columns into final logic array output;
k is the number of the fault-free processor units in the set logic column; i =1,2, ….
As an improvement, in each logic column C i After the construction is completed, the processor unit u without fault in the current physical array which satisfies one of the following two conditions needs to be eliminated:
the first condition is as follows: col (α) < col (β), row (u) = row (α) and col (α) < col (u) < col (β);
case two: col (. Alpha.) < col (. Beta.), row (u) = row (beta.) and col (. Alpha.) < col (u) < col (beta)
Wherein: alpha and beta represent the logic column C i Two of the failure-free processor units which are continuous in sequence; col (·) denotes a physical column index, row (·) denotes a physical row index; i =1,2, ….
As a further improvement, the logic column C starts from the second logic column and is arranged at the i +1 th logic column i+1 After the construction is completed, the processor unit u without fault in the current physical array, which satisfies one of the following four conditions, needs to be further rejected:
the first condition is as follows: row (u) > row (p), row (u) < row (v) and col (p) = col (u);
case two: row (w) ≦ row (p) -1, col (w) = col (v) and row (w) < row (p);
case three: col (u) < col (q), row (v) = row (u) and row (u) ≦ row (q) -1;
case four: col (u) = col (w);
wherein: p, u and q are the ith logical column C i Three in the sequence of the non-fault processor units, v and w are the (i + 1) th logic column C i+1 Two consecutive non-faulty processor units in the sequence that correspond to the same location of non-faulty processor units p and u, respectively, row (-) represents the physical row index; i =1,2, ….
In step 1.2, if the initial pre-processing logic row P _ C 1 And if the physical column indexes of the middle fault processor units are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the current physical array range.
As a modification, after step 1.2 and before step 1.3, the method further comprises the following steps: if compensated, the initial pre-processing logic row P _ C still cannot be made 1 If the number f of the middle fault-free processor units is larger than or equal to k, repeating the step 1.2 for the initial preprocessing logic column P _ C 1 The medium fault handler unit compensates.
In step 2.3, if the i +1 th preprocessed logic row P _ C i+1 And if the physical column indexes of the middle fault processor units are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the current boundary interval range.
As a modification, the method further comprises the following steps after the step 2.3 and before the step 2.4: if compensated, the i +1 st pre-processing logic column P _ C still cannot be ordered i+1 If the number f of the middle fault-free processor units is larger than or equal to k, repeating the step 2.3 to the (i + 1) th preprocessing logic column P _ C i+1 The medium fault handler unit compensates.
In the above steps, when compensating the processor unit e with the current failure, the processor unit e with the current failure is replaced by the non-failure processor unit closest to the processor unit e with the current failure on the same physical row on the right side of the processor unit e with the current failure within the predetermined range.
In the above steps, the set priority rule is: for any two processor units x and y, comparing the column index col (x) of the processor unit x with the column index col (y) of the processor unit y, and if col (x) < col (y), giving priority to the processor unit x over the processor unit y; on the basis, if col (x) = col (y), the row index row (x) of the processor unit x and the row index row (y) of the processor unit y are further compared, and if row (x) < row (y), the processor unit x has priority over the processor unit y.
Compared with the prior art, the method divides the processor array into small intervals through the idea of dynamic programming, and sequentially constructs the local optimal logic columns in the intervals according to the sequence from left to right, so that the maximum logic array is generated in the polynomial time, the operation can be faster without losing results, and the logic array is larger in scale. In addition, the method does not limit the compensation distance in row and column rerouting, which can maximally improve the utilization rate of the fault-free processor unit in the processor, thereby greatly improving the stability of the system.
Detailed Description
For the understanding of the present invention, the following description is given for the purpose of analyzing and explaining the related contents of the present invention:
s1, partial order relation of logic columns
The non-faulty subarray resulting from the reconstruction of an array (physical array) containing faulty processor elements is called the logical array (target array), and the resulting columns are called logical columns. All logic columns in the logic array satisfy the following partial order relationship. In a logic array S comprising m logic columns, for any two logic columns C α And C β α ≠ β: if C α The ith processor unit in the ith row is located at C β I is more than or equal to 1 and less than or equal to m, then called C α ＜C β . If C α The ith processor unit in the ith row is located at C β The left side or position of the ith processor unit in the ith row of (1) is the same, then it is called C α ≤C β . If C α ＜C β Or C α ＞C β Then call C α And C β Are independent of each other. Therefore, the logic columns in the logic array S satisfy the partial order relationshipC 1 ＜C 2 ＜…＜C m 。
S2, definition of intervals
Hypothesis C l And C r For two mutually independent logic columns in the logic array S, use is made of ^ C l ,C r ]To represent by C l And C r An interval of boundary (including C) l And C r ). Using ^ C l ,C r ) To indicate the same interval as above, including C l But does not contain C r . Using ^ (C) l ,C r ]To indicate the same interval as above, including C r But does not contain C l 。C l And C r Is divided into intervals ^ (C) l ,C r ]Left and right boundaries.
S3, constructing an initial logic column
(1) A pre-processing logic column is constructed.
The algorithm attempts to construct a logical column of k number of non-failing processors. Firstly, the first physical column is taken as the first preprocessing logic column P _ C 1 . If P _ C 1 If the number f of the middle fault-free processor units satisfies f = k, then P _ C 1 I.e. the initial logic column C 1 (ii) a If P _ C 1 If the number f of the middle fault-free processor units satisfies f > k, then the number of the processor units is P _ C 1 The k non-failure processor units (the non-failure processor unit on the right side is the most) are selected as the initial logic column C 1 (ii) a If P _ C 1 The number f of the middle fault-free processor units satisfies f < k, namely the preprocessing logic column P _ C 1 If the number k of the non-fault processor units in (1) does not satisfy the number k required by the system, compensation operation is required to meet the requirement.
(2) And (6) compensation.
Pre-processing logic column P _ C 1 The number f of fault-free processor units in (2) is less than the required number k, then at P _ C 1 The k-f failing processor units need to be compensated. Comparison P _ C 1 Selecting k-f fault processor units with the smallest column index for preferential compensation; if the index of the failing processor unit row is the same, choose its right noneThe most faulty processor element is compensated for by the faulty processor element to the right of which the selected faulty processor element is compensated for by the neighbouring processor element. If compensated, the initial pre-processing logic row P _ C still cannot be enabled 1 If the number f of the medium and non-fault processor units is larger than or equal to k, repeating the steps until k-f fault processor units are all compensated by the non-fault processor units, and the compensated non-fault processor units and the P _ C 1 The non-faulty processor unit in (1) is connected as an initial logical column C 1 。
When the processor unit e with the current fault is compensated, the processor unit e with the current fault is replaced by the processor unit without the fault which is closest to the same physical row on the right side of the processor unit e with the current fault (with the smallest physical row difference) within a preset range (within the range of the current physical array or within the range of the current boundary interval).
Because the invention adopts the compensation mode to lead the fault-free processor unit P _ C of the preprocessing logic column i Up to k, so that the logic column C is actually formed i Is substantially equal to the physical column index i of the corresponding physical array.
S4, definition of unavailable processor unit
Since the algorithm does not limit the compensation distance, some processor units that are not faulty become unusable after a logical column is constructed. Assume that α and β are logic columns C i For any non-failing processor unit u, it will become unusable if the following two conditions are met.
The first condition is as follows: col (α) < col (β), row (u) = row (α) and col (α) < col (u) < col (β);
case two: col (α) < col (β), row (u) = row (β) and col (α) < col (u) < col (β).
Where col (·) represents the physical column index and row (·) represents the physical row index.
S5, constructing a subsequent logic column
When the first logic column C 1 After obtaining, selecting C 1 All places on the right sideThe processor units (except the unavailable processor unit in S4) are connected as the next pre-processing column P _ C 2 ，
If P _ C 2 If the number f of the fault-free processor units in the system satisfies f ≧ k, the first step of S3 is used to construct the logic column C 2 ；
If P _ C 2 The number f of the fault-free processor units satisfies f < k, and the algorithm will P _ C 2 As a left boundary C l Then look for P _ C 2 The first non-faulty processor unit to the right of all faulty processor units in the cluster, and compares the column indices of the non-faulty processor units, and takes the physical column in which the non-faulty processor unit with the largest column index is located as the right boundary C r It is recorded as ^ C l ,C r ]. Second logic column C 2 Will be in the interval ^ C l ,C r ]And internally compensating in the same way as the second step of S3. Subsequent logical columns are obtained in this manner until there are no available processor units in the array.
S6, correcting unconnected processor units
When constructing any two logic columns C i And C i+1 Then, since the compensation distance is not limited, logic column C i And C i+1 The upper processor units may not be connected to each other due to the occupation of the links and switches. Let p, u and q be logic columns C i Three in-sequence non-fault processor units, v and w being logical columns C i+1 In the two sequenced continuous fault-free processor units respectively corresponding to the same positions of p and u, p and v are connected with each other to be used as a logic row, and in general, for any w, row (w) > row (v) is satisfied, and in four cases, w cannot be connected with u to be used as a logic row.
The first condition is as follows: row (u) > row (p), row (u) < row (v) and col (p) = col (u);
case two: row (w) ≦ row (p) -1, col (w) = col (v) and row (w) < row (p);
case three: col (u) < col (q), row (v) = row (u) and row (u) ≦ row (q) -1;
case four: col (u) = col (w).
Where col (·) represents the physical column index and row (·) represents the physical row index. The algorithm then checks that if the processor elements adjacent to the two logical columns satisfy the above condition, w is marked as an unavailable element and selects other non-failing processor elements that can be connected to u to replace it until logical column C i And C i+1 All of the corresponding processor units may be connected to each other. This step is performed in a loop until all the processor units corresponding to the logical columns can be connected to each other, and the logical columns with the size of m '× n' are finally constructed.
S7, constructing the largest logic array
In an m n primary array, r and c represent the minimum dimensional requirement of the rows and columns of the target sub-array, respectively. The first algorithm is constructed by taking the row dimension as m, a corresponding logic array m '× n' is obtained through S4, S5 and S6, and if m 'is more than or equal to r and n' is more than or equal to c, a logic sub-array meeting the requirements is obtained; otherwise, the resulting logic array does not meet the required minimum dimension and the algorithm terminates. Then m-1,m-2, …,1, and constructing a logic array of the corresponding row dimension, and selecting the logic array meeting the requirement. In order to obtain the largest-sized logic sub-array, m iterations are performed, and the largest-sized logic array is selected as the final output from among the logic sub-arrays that satisfy the requirements.
Based on the above analysis, the method for rapidly reconstructing a two-dimensional processor array designed by the present invention specifically includes the following steps:
before the algorithm runs, initialization is carried out: the number k of non-failing processor units in the set logical column and the priority rule.
In this embodiment, the set priority rule is: for any two processor units x and y, comparing the column index col (x) of the processor unit x with the column index col (y) of the processor unit y, and if col (x) < col (y), giving priority to the processor unit x over the processor unit y; at this time, if col (x) = col (y), the row index row (x) of the processor unit x and the row index row (y) of the processor unit y are compared, and if row (x) < row (y), the processor unit x has priority over the processor unit y.
Step 1: constructing an initial logic column C 1 Namely:
step 1.1, forming the first physical column of the current physics into an initial preprocessing logic column P _ C 1 ：
If the initial pre-processing logic row P _ C 1 If the number f of the middle fault-free processor units is larger than or equal to k, the logic column P _ C is preprocessed from the beginning 1 Selecting k fault-free processor units to form an initial logic column C 1 ；
If the initial pre-processing logic row P _ C 1 If the number f of the processor units without faults is less than k, turning to the step 1.2;
step 1.2, compare initial pre-processing logic column P _ C 1 Selecting the fault processor unit with the smallest k-f physical column indexes to compensate in the current physical array range; on this basis, if the initial pre-processing logic row P _ C 1 If the physical column indexes of the middle fault processor units are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the range of the current physical array;
step 1.3, if the compensation is performed, the initial pre-processing logic row P _ C still cannot be enabled 1 If the number f of the medium and non-fault processor units is more than or equal to k, repeating the step 1.2;
step 1.4, from the compensated initial preprocessed logic sequence P _ C 1 Selecting k non-fault processor units to form an initial logic column C 1 ；
Step 1.5, start logic column C 1 Arranging the k fault-free processor units according to a set priority rule; and will participate in constructing the initial logical column C 1 The k non-faulty processor elements are removed from the current physical array;
step 1.6 at the beginning of logic column C 1 After the construction is completed, the processor unit u without fault in the current physical array which satisfies one of the following two conditions needs to be eliminated:
the first condition is as follows: col (α) < col (β), row (u) = row (α) and col (α) < col (u) < col (β);
and a second condition: col (α) < col (β), row (u) = row (β) and col (α) < col (u) < col (β)
Wherein: alpha and beta represent the starting logical column C 1 Two of the failure-free processor units are continuous in sequence; col (. Cndot.) represents a physical column index, and row (. Cndot.) represents a physical row index.
Step 2, based on the ith logic column C i Constructing the i +1 th logic column C i+1 Wherein i =1,2, …; namely:
step 2.1, all processor units on the right side of the ith physical column are selected from the current physical array to form an i +1 th preprocessing logic column P _ C i+1 ：
If the i +1 th preprocessed logic row P _ C i+1 If the number f of the non-fault processor units is more than or equal to k, the logic column P _ C is preprocessed from the i +1 th i+1 Selecting k fault-free processor units to form an i +1 logic column C i+1 ；
If the i +1 th preprocessed logic row P _ C i+1 If the number f of the fault-free processor units is less than k, then the step 2.2 is carried out;
step 2.2, the i +1 th preprocessing logic column P _ C i+1 Corresponding physical column as left boundary C l Then find the i +1 th preprocessed logic column P _ C i+1 The first non-faulty processor element to the right of all faulty processor elements in the cluster, and compares the physical column indices of these non-faulty processor elements, and takes the physical column in which the non-faulty processor element with the largest column index is located as the right boundary C r Obtaining a current boundary interval;
step 2.3, compare the i +1 th preprocessing logic column P _ C i+1 Selecting the fault processor unit with the smallest k-f physical column indexes to compensate in the current boundary interval range; on this basis, if the i +1 th preprocessed logic row P _ C i+1 If the physical column indexes of the middle fault processor units are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the current boundary interval range;
step 2.4, if the compensation is carried out, the compensation is carried outStill, the i +1 st preprocessed logic column P _ C cannot be ordered i+1 If the number f of the medium and non-fault processor units is more than or equal to k, repeating the step 2.3;
step 2.5, from the compensated i +1 th preprocessed logic column P _ C i+1 Selecting k fault-free processor units to form an i +1 logic column C i+1 ；
Step 2.6, the (i + 1) th logic column C i+1 Arranging the k fault-free processor units according to a set priority rule; and will participate in the construction of the (i + 1) th logical column C i+1 The k fault-free processor units are removed from the current physical array;
step 2.7, in the i +1 th logic column C i+1 After the construction is completed, the processor unit u without fault in the current physical array which satisfies one of the following two conditions needs to be eliminated:
the first condition is as follows: col (α) < col (β), row (u) = row (α) and col (α) < col (u) < col (β);
case two: col (α) < col (β), row (u) = row (β) and col (α) < col (u) < col (β)
Wherein: alpha and beta represent the logic column C in the i +1 th column i+1 Two of the failure-free processor units are continuous in sequence; col (·) denotes a physical column index, row (·) denotes a physical row index;
step 2.8, in the i +1 th logic column C i+1 After the construction is completed, the processor unit u without fault in the current physical array, which satisfies one of the following four conditions, needs to be further rejected:
the first condition is as follows: row (u) > row (p), row (u) < row (v) and col (p) = col (u);
and a second condition: row (w) ≦ row (p) -1, col (w) = col (v) and row (w) < row (p);
and a third situation: col (u) < col (q), row (v) = row (u) and row (u) ≦ row (q) -1;
case four: col (u) = col (w);
wherein: p, u and q are the ith logical column C i Three in the sequence of the non-fault processor units, v and w are the (i + 1) th logic column C i+1 Respectively corresponding to a non-faulty processor unit p andu two sequentially consecutive non-failing processor units of the same location, row (·) represents the physical row index.
Step 3, judging whether the number of the residual fault-free processor units on the current physical array is more than or equal to the number k of the fault-free processor units in the set logic array: if yes, returning to the step 2; otherwise, go to step 4;
and 4, forming all the constructed logic columns into final logic array output.
The reconfigurable processor system is composed of a general processor and a reconfigurable array, and supports dynamic change of the link mode of the processor by changing the state of an internal link. The difference between the method and the common microprocessor is that not only the control flow can be changed, but also the structure of a Data Path (Data Path) can be changed, and the method has the advantages of low hardware overhead and power consumption, good flexibility and good expansibility. In a large-scale coarse-grained reconfigurable array, the characteristic of hardware parallelization execution can be fully utilized, and the acceleration of computation-intensive application is obvious.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.
Claims (9)
1. A fast reconstruction method of a two-dimensional processor array is characterized by comprising the following steps:
step 1: constructing an initial logic column C 1 Namely:
step 1.1, forming the first physical column of the current physics into an initial preprocessing logic column P _ C 1 ：
If the initial pre-processing logic row P _ C 1 If the number f of the middle fault-free processor units is larger than or equal to k, the logic column P _ C is preprocessed from the beginning 1 Selecting k non-fault processor units to form an initial logic column C 1 ；
If it is initially pre-determinedProcessing logic column P _ C 1 If the number f of the processor units without faults is less than k, turning to the step 1.2;
step 1.2, compare initial pre-processing logic column P _ C 1 Selecting the fault processor unit with the smallest k-f physical column indexes to compensate in the current physical array range;
step 1.3, from the compensated initial preprocessed logic sequence P _ C 1 Selecting k non-fault processor units to form an initial logic column C 1 ；
Step 1.4, start logic column C 1 Arranging the k fault-free processor units according to a set priority rule; and will participate in constructing the initial logical column C 1 The k non-faulty processor elements are removed from the current physical array;
step 2, based on the ith logic column C i Constructing the i +1 th logic column C i+1 Namely:
step 2.1, all processor units on the right side of the ith physical column are selected from the current physical array to form an i +1 th preprocessing logic column P _ C i+1 ：
If the i +1 th preprocessed logic row P _ C i+1 If the number f of the non-fault processor units is more than or equal to k, the logic column P _ C is preprocessed from the i +1 th i+1 Selecting k fault-free processor units to form an i +1 logic column C i+1 ；
If the i +1 st preprocessed logic row P _ C i+1 If the number f of the fault-free processor units is less than k, then the step 2.2 is carried out;
step 2.2, the i +1 th preprocessing logic column P _ C i+1 Corresponding physical column as left boundary C l Then find the i +1 th preprocessed logic column P _ C i+1 The first non-faulty processor element to the right of all faulty processor elements in the cluster, and by comparing the physical column indices of these non-faulty processor elements, the physical column in which the non-faulty processor element with the largest physical column index is located is taken as the right boundary C r Obtaining the range of the current boundary interval;
step 2.3, comparing the i +1 th preprocessing logic columnP_C i+1 Selecting the fault processor unit with the smallest k-f physical column indexes to compensate in the current boundary interval range;
step 2.4, from the compensated i +1 th preprocessed logic column P _ C i+1 Selecting k non-fault processor units to form the (i + 1) th logic column C i+1 ；
Step 2.5, the (i + 1) th logic column C i+1 Arranging the k fault-free processor units according to a set priority rule; and will participate in the construction of the (i + 1) th logical column C i+1 The k non-faulty processor elements are removed from the current physical array;
step 3, judging whether the number of the residual fault-free processor units on the current physical array is more than or equal to the number k of the fault-free processor units in the set logic array: if yes, returning to the step 2; otherwise, go to step 4;
step 4, forming all the constructed logic columns into final logic array output;
k is the number of fault-free processor units in the set logic column; i =1,2, ….
2. A method for fast reconstruction of a two-dimensional processor array according to claim 1, characterized in that in each logical column C i After the construction is completed, the processor units u without faults in the current physical array that satisfy one of the following two conditions need to be rejected:
the first condition is as follows: col (α) < col (β), row (u) = row (α) and col (α) < col (u) < col (β);
case two: col (α) < col (β), row (u) = row (β) and col (α) < col (u) < col (β)
Wherein: alpha and beta represent logic columns C i Two of the failure-free processor units are continuous in sequence; col (·) denotes a physical column index, row (·) denotes a physical row index; i =1,2, ….
3. A method for fast reconstruction of a two-dimensional processor array according to claim 1 or 2, characterized in thatStarting from the second logic column, at the i +1 th logic column C i+1 After the construction is completed, the processor unit u without fault in the current physical array, which satisfies one of the following four conditions, needs to be further rejected:
the first condition is as follows: row (u) > row (p), row (u) < row (v) and col (p) = col (u);
case two: row (w) ≦ row (p) -1, col (w) = col (v) and row (w) < row (p);
case three: col (u) < col (q), row (v) = row (u) and row (u) ≦ row (q) -1;
case four: col (u) = col (w);
wherein: p, u and q are the ith logical column C i Three in the sequence of the non-fault processor units, v and w are the (i + 1) th logic column C i+1 Two consecutive non-faulty processor units in the sequence that correspond to the same location of non-faulty processor units p and u, respectively, row (-) represents the physical row index; i =1,2, ….
4. The method of claim 1, wherein in step 1.2, if the initial preprocessed logical row P _ C is used, the method further comprises 1 And if the physical column indexes of the middle fault processor units are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the current physical array range.
5. A method for fast reconstruction of a two-dimensional processor array according to claim 1 or 4, characterized in that after step 1.2 and before step 1.3 further comprising the steps of: if compensated, the initial pre-processing logic row P _ C still cannot be made 1 If the number f of the middle fault-free processor units is larger than or equal to k, repeating the step 1.2 for the initial preprocessing logic column P _ C 1 The medium fault handler unit compensates.
6. The method as claimed in claim 1, wherein in step 2.3, if the i +1 th preprocessed logic column P _ C i+1 Of medium-fault processor unitsAnd if the physical column indexes are the same, selecting the fault processor unit with the most fault processor units on the right side to compensate in the current boundary interval range.
7. A method for fast reconstruction of a two-dimensional processor array according to claim 1 or 6, further comprising the following steps after step 2.3 and before step 2.4: if compensated, the i +1 st pre-processing logic column P _ C still cannot be ordered i+1 If the number f of the middle fault-free processor units is larger than or equal to k, repeating the step 2.3 to the (i + 1) th preprocessing logic column P _ C i+1 The medium fault handler unit compensates.
8. The method of claim 1, wherein when compensating for a currently failing processor unit e, the currently failing processor unit e is replaced by a non-failing processor unit closest to the currently failing processor unit e on the same physical row to the right of the currently failing processor unit e within a predetermined range.
9. The method of claim 1, wherein the priority rule is set as: for any two processor units x and y, comparing the column index col (x) of the processor unit x with the column index col (y) of the processor unit y, and if col (x) < col (y), prioritizing the processor unit x over the processor unit y; on the basis, if col (x) = col (y), the row index row (x) of the processor unit x and the row index row (y) of the processor unit y are further compared, and if row (x) < row (y), the processor unit x has priority over the processor unit y.
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