CN111492348A

CN111492348A - Techniques for achieving guaranteed network quality with hardware acceleration

Info

Publication number: CN111492348A
Application number: CN201980006775.0A
Authority: CN
Inventors: M.甘谷利; F.G.伯纳特; T.维罗尔
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2018-02-21
Filing date: 2019-02-21
Publication date: 2020-08-04
Also published as: DE112019000910T5; WO2019165110A1

Abstract

A technique for managing service guarantees in a network includes an orchestrator server receiving a request to launch a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification, the orchestrator server mapping the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating a required network bandwidth and computing capacity specified in a service level agreement (S L A). The orchestrator server launching the VM. orchestrator server on a computing device identified according to the mapped S L O units generates one or more scores associated with performance of the VM, and determines whether the performance of the VM on the computing device satisfies each of the one or more S L O units according to the generated one or more scores.

Description

Techniques for achieving guaranteed network quality with hardware acceleration

Cross Reference to Related Applications

This disclosure claims priority to U.S. provisional patent application serial No. 62/633,397, filed on 21/2/2018, which is incorporated herein by reference.

Background

Service guarantees are important for Network Function Virtualization (NFV) and Software Defined Networking (SDN) technologies. Generally, service guarantees involve the application of policies and procedures to ensure that services provided over the network meet specified quality of service levels. For example, determining quality of service (QoS) at one endpoint and another provides a measure of service guarantees. Doing so involves monitoring the following: service infrastructure performance under a Virtualized Network Function (VNF), compliance to performance targets, alerts for threshold violations, and appropriate actions. Furthermore, NFV workloads are typically associated with network QoS requirements, violations of which may result in the provider compensating the customer. Currently, solutions are available to guarantee QoS for aspects such as computing resources and performance, but comprehensive service guarantees for VNFs typically require fine-tuning of processor, memory, and network control for each virtual central processing unit (vCPU) and each thread. Service guarantees may also require a constant feedback loop to maintain QoS.

Drawings

The concepts described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a data center for utilizing decomposed (disaggregate) resources to execute workloads;

FIG. 2 is a simplified diagram of at least one embodiment of a pod (pod) that may be included in the data center of FIG. 1;

FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod of FIG. 2;

FIG. 4 is a side view of the frame of FIG. 3;

FIG. 5 is a perspective view of the frame of FIG. 3 having a sled (sled) mounted thereon;

FIG. 6 is a simplified block diagram of at least one embodiment of a top side of the sled of FIG. 5;

FIG. 7 is a simplified block diagram of at least one embodiment of the underside of the sled of FIG. 6;

FIG. 8 is a simplified block diagram of at least one embodiment of a computing sled that may be used in the data center of FIG. 1;

FIG. 9 is a top perspective view of at least one embodiment of the computing sled of FIG. 8;

FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled that may be used in the data center of FIG. 1;

FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled of FIG. 10;

FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled that may be used in the data center of FIG. 1;

FIG. 13 is a top perspective view of at least one embodiment of the storage device sled of FIG. 12;

FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled that may be used in the data center of FIG. 1; and

FIG. 15 is a simplified block diagram of a system that may be set up within the data center of FIG. 1 to perform workloads with managed nodes (managed nodes) comprised of decomposed resources;

fig. 16 is a simplified block diagram of a system that provides a quality of experience (QoE) software stack that represents a network services framework for deploying, orchestrating, and managing services provided by a Virtualized Network Function (VNF);

FIG. 17 is a simplified block diagram of at least one embodiment of an orchestrator server in the system described with respect to FIG. 16;

FIG. 18 is a simplified block diagram of at least one embodiment of an environment that may be established by the orchestrator server of FIGS. 16 and 17; and

FIG. 19 is a simplified flow diagram of at least one embodiment of a method for managing service guarantees in a network environment, such as the system described with respect to FIG. 16.

Detailed Description

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intention to limit the concepts of the disclosure to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the disclosure and the appended claims.

References in the specification to "one embodiment," "an illustrative embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in the list in the form of "at least one A, B and C" may mean (a); (B) (ii) a (C) (ii) a (A and B); (A and C); (B and C); or (A, B and C). Similarly, an item listed in the form of "at least one of A, B or C" can mean (a); (B) (ii) a (C) (ii) a (A and B); (A and C); (B and C); or (A, B and C).

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disk, or other media device).

In the drawings, some structural or methodical features may be shown in a particular arrangement and/or ordering. However, it should be appreciated that such a specific arrangement and/or ordering may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or methodical feature in a particular figure is not meant to imply that such feature is required in all embodiments, and may not be included or combined with other features in some embodiments.

Referring now to fig. 1, a data center 100 in which decomposed resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includes a plurality of

pods

110, 120, 130, 140, each pod including one or more rows of racks. Of course, although data center 100 is shown with multiple pods, in some embodiments, data center 100 may be embodied as a single pod. As described in more detail herein, each chassis houses a plurality of sleds, each sled may be primarily equipped with a particular type of resource (e.g., memory device, data storage device, accelerator device, general purpose processor), i.e., a resource that may be logically coupled to form a component node that may act as, for example, a server. In the illustrative embodiment, the sleds in each

pod

110, 120, 130, 140 are connected to multiple pod switches (e.g., switches that route data communications to or from the sleds within the pod). The pod switches, in turn, are connected to spine (spine) switches 150, which spine switches 150 switch communications among the pods (e.g.,

pods

110, 120, 130, 140) in the data center 100. In some embodiments, the intel Omni-Path technology may be used to attach the sled to a structure. In other embodiments, the sleds may be connected to other structures, such as InfiniBand (ethernet). As described in more detail herein, resources within sleds in data center 100 can be assigned to a group (referred to herein as a "managed node") containing resources from one or more sleds that will be commonly utilized in the execution of a workload. The workload may be executed as if the resources belonging to the managed node were on the same sled. The resources in the managed node may belong to the following sleds: these sleds belong to different racks and even to

different pods

110, 120, 130, 140. Thus, some resources of a single skid may be allocated to one managed node while other resources of the same skid are allocated to a different managed node (e.g., one processor is assigned to one managed node while another processor of the same skid is assigned to a different managed node).

A data center, such as data center 100, that includes the decomposed resources may be used in a wide variety of contexts, such as businesses, governments, cloud service providers, and communication service providers (e.g., of a telecommunications company), and may be used in a wide variety of scales, from large data centers that occupy over 100,000 square feet of cloud service providers to single or multi-rack installations for use in base stations.

Resource decomposition of sleds that include primarily a single type of resource (e.g., compute sleds that include primarily compute resources, memory sleds that include primarily memory resources), and selective allocation and reallocation of the decomposed resources to form managed nodes, which are assigned to execute workloads, improves the operation and resource usage of the data center 100 relative to a typical data center consisting of a super-converged server that includes compute, memory, storage, and possibly additional resources in a single chassis (chasis). For example, since the sleds contain primarily resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, since different resource types (processors, storage, accelerators, etc.) typically have different refresh rates, higher resource utilization and reduced overall cost of ownership may be achieved. For example, a data center operator may upgrade processors throughout its facility by merely swapping out (swap out) computing sleds. In this case, the accelerator and storage resources may not be upgraded at the same time, but may be allowed to continue operating until they are scheduled for their own refresh. Resource utilization may also increase. For example, if a managed node is composed based on the requirements of the workload to be run on, then resources within the node are more likely to be fully utilized. Such utilization may allow more managed nodes to run in a data center with a given set of resources, or allow fewer resources to be used to construct a data center that is expected to run a given set of workloads.

Referring now to fig. 2, in an illustrative embodiment, the pod 110 includes a set of

rows

200, 210, 220, 230 of racks 240. Each chassis 240 may house a plurality of sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in each

row

200, 210, 220, 230 are connected to a plurality of pod switches 250, 260. Pod switch 250 includes: a set of ports 252 to which the sleds in the frame of pod 110 are connected; and another set of ports 254 that connect the pod 110 to the spine switch 150 to provide connectivity to other pods in the data center 100. Similarly, pod switch 260 includes: a set of ports 262 to which the sleds in the frame of pod 110 are connected; and a set of ports 264, the ports 264 connecting the pod 110 to the spine switch 150. Thus, the use of the pair of switches 250, 260 provides a certain amount of redundancy to the pod 110. For example, if either of the switches 250, 260 fails, the sleds in a pod 110 may still maintain data communication with the rest of the data center 100 (e.g., sleds of other pods) through the other switch 250, 260. Further, in the illustrative embodiment, the

switches

150, 250, 260 may be embodied as dual-mode optical switches capable of routing both Internet Protocol (IP) packet-bearing ethernet protocol communications and communications in accordance with a second high-performance link-layer protocol (e.g., intel's Omni-Path architecture, infiniband, PCI Express) via the optical signaling medium of the optical fabric.

It should be appreciated that each of the

other pod compartments

120, 130, 140 (as well as any additional pod compartments of the data center 100) may be similarly configured as the pod compartment 110 shown and described with respect to fig. 2, and have similar components as the pod compartment 110 (e.g., each pod compartment may have a row of racks housing a plurality of sleds, as described above). Additionally, while two pod switches 250, 260 are shown, it should be understood that in other embodiments, each

pod

110, 120, 130, 140 may be connected to a different number of pod switches, thereby providing even more failover capabilities. Of course, in other embodiments, the pods may be arranged differently than in the row-of-racks configuration shown in FIGS. 1-2. For example, the pod may be embodied as multiple sets of racks, with each set of racks being arranged radially, i.e., the racks being equidistant from the central switch.

Referring now to fig. 3-5, each illustrative rack 240 of the data center 100 includes two elongated support posts 302, 304 arranged vertically. For example, the elongated support posts 302, 304 may extend upward from the floor of the data center 100 when deployed. The frame 240 also includes one or more horizontal pairs 310 (identified in FIG. 3 via dashed ellipses) of elongated support arms 312, the elongated support arms 312 configured to support a sled of the data center 100, as discussed below. One elongated support arm 312 of the pair of elongated support arms 312 extends outwardly from the elongated support column 302, while the other elongated support arm 312 extends outwardly from the elongated support column 304.

In the illustrative embodiment, each sled of data center 100 is embodied as an inorganic box-less sled. That is, each sled has an inorganic box-type circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage devices, etc.) are mounted, as discussed in more detail below. Thus, the chassis 240 is configured to receive a mineral box sled. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the frame 240, the sled slot 320 configured to receive a corresponding inorganic box sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330, the circuit board guide 330 configured to receive the inorganic box circuit board substrate of the sled. Each circuit board guide 330 is secured to or otherwise mounted to the top side 332 of the corresponding elongate support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding

elongated support post

302, 304. For clarity of the figures, each circuit board guide 330 may not be referenced in each figure.

Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380, the circuit board slot 380 being configured to: the inorganic box circuit board substrate of the sled 400 is received when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, the user (or robot) aligns the inorganic box circuit board substrate of the exemplary inorganic box sled 400 to the sled slot 320, as shown in fig. 4. The user or robot may then slide the inorganic case circuit board substrate forward into the sled slots 320 such that each side edge 414 of the inorganic case circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of elongated support arms 312 defining the corresponding sled slot 320, as shown in fig. 4. By having a robot-accessible and robot-manipulatable sled that includes decomposed resources, each type of resource can be upgraded independently of the other and at its own optimized refresh rate. In addition, the sleds are configured to blind mate (blindly mate) with the power and data communication cables in each rack 240, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Thus, in some embodiments, the data center 100 may operate (e.g., perform a workload, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center 100.

It should be appreciated that each circuit board guide 330 is double sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this manner, each circuit board guide 330 may support the inorganic case circuit board substrate on either side. Thus, a single additional elongated support post may be added to the rack 240 to convert the rack 240 into a two-rack solution that may hold twice as many sled slots 320 as shown in fig. 3. The illustrative chassis 240 includes seven pairs 310 of elongated support arms 312, the seven pairs 310 of elongated support arms 312 defining corresponding seven sled slots 320, each sled slot 320 configured to receive and support a corresponding sled 400 as discussed above. Of course, in other embodiments, the frame 240 may include additional or fewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because sled 400 is inorganic boxed, sled 400 may have an overall height that is different from a typical server. Thus, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single row unit "1U"). That is, the vertical distance between each pair 310 of elongated support arms 312 may be less than the standard rack unit "1U". Additionally, due to the relative reduction in the height of sled slots 320, in some embodiments, the overall height of holster 240 may be shorter than the height of conventional holster shells. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Also, in other embodiments, the chassis 240 may have different dimensions. For example, in some embodiments, the vertical distance between each pair 310 of elongated support arms 312 may be greater than the standard rack unit "1U". In such embodiments, the increased vertical distance between the sleds allows for a larger heat sink to be attached to the physical resources and allows for the use of larger fans (e.g., in fan array 370 described below) for cooling each sled, which in turn may allow the physical resources to operate at increased power levels. Further, it should be appreciated that the chassis 240 does not include any walls, housings, etc. Rather, the chassis 240 is a case-less chassis that is open to the local environment. Of course, in some cases, an end plate (endplate) may be attached to one of the elongated support posts 302, 304 in those instances where the rack 240 forms an end-of-row rack in the data center 100.

In some embodiments, various interconnects may be routed up or down through the elongated support posts 302, 304. To facilitate such routing, each

elongated support post

302, 304 includes an inner wall that defines an interior chamber in which the interconnect can be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnect, including but not limited to: a data or communication interconnect to provide a communication connection to each sled slot 320; a power interconnect to provide power to each sled slot 320; and/or other types of interconnects.

In the illustrative embodiment, the chassis 240 includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to: when the sled 400 is received in the corresponding sled slot 320, it mates with the optical data connector of the corresponding sled 400. In some embodiments, the optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made using blind mate (blidmate) optical connections. For example, a door on each cable may prevent dust from contaminating the optical fibers inside the cable. In a process for connecting to a blind mate optical connector mechanism, the door is pushed open as the end of the cable approaches or enters the connector mechanism. The optical fibers within the cables may then enter the gel within the connector mechanism, and the optical fibers of one cable contact the optical fibers of another cable within the gel within the connector mechanism.

The illustrative chassis 240 also includes a fan array 370 coupled to the cross-support arms of the chassis 240. The fan array 370 includes one or more rows of cooling fans 372, the cooling fans 372 being aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, in the illustrative embodiment, each sled 400 does not include any on-board cooling system, and as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. In the illustrative embodiment, each rack 240 also includes a power supply associated with each sled slot 320. Each power source is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define a corresponding sled slot 320. For example, the frame 240 may include a power source coupled or secured to each of the elongated support arms 312 extending from the elongated support column 302. Each power supply includes a power connector configured to: when the sled 400 is received in the corresponding sled slot 320, it mates with the power connector of the sled 400. In the illustrative embodiment, the sleds 400 do not include any on-board power supply, and thus, the power supply provided in the chassis 240 supplies power to the corresponding sleds 400 when mounted to the chassis 240. Each power source is configured to meet the power requirements of its associated sled, which may vary from sled to sled. Additionally, the power supplies provided in the racks 240 may operate independently of each other. That is, within a single gantry, a first power source that provides power to the computation sled may provide a different power level than a second power source that provides power to the accelerator sled. The power supply may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled, or remotely, such as by other sleds or organizers.

Referring now to fig. 6, in an illustrative embodiment, sled 400 is configured to be mounted in corresponding racks 240 of data center 100, as discussed above. In some embodiments, each sled 400 may be optimized or otherwise configured for performing specific tasks, such as computing tasks, acceleration tasks, data storage tasks, and the like. For example, sled 400 may be embodied as a computation sled 800 as discussed below with respect to fig. 8-9, an accelerator sled 1000 as discussed below with respect to fig. 10-11, a storage device sled 1200 as discussed below with respect to fig. 12-13, or as a sled optimized or otherwise configured to perform other specialized tasks as discussed below with respect to fig. 14, such as memory sled 1400.

As discussed above, the illustrative sled 400 includes an inorganic box-type circuit board substrate 602, the circuit board substrate 602 supporting various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is "inorganic box-type" because the sled 400 does not include a housing or casing. Rather, the inorganic box substrate 602 is open to the local environment. The inorganic case circuit board substrate 602 may be formed of any material capable of supporting the various electrical components mounted thereon. For example, in the illustrative embodiment, the inorganic box circuit board substrate 602 is formed from an FR-4 glass reinforced epoxy laminate. Of course, in other embodiments, other materials may be used to form the inorganic box circuit board substrate 602.

As discussed in more detail below, the inorganic case circuit board substrate 602 includes a number of features that improve the thermal cooling characteristics of the various electrical components mounted on the inorganic case circuit board substrate 602. As discussed, the inorganic box circuit board substrate 602 does not include a housing or casing, which may improve airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the inorganic box circuit board substrate 602 is not positioned in a separate housing or casing, there is no vertically disposed backplane (e.g., a backplane of a chassis) attached to the inorganic box circuit board substrate 602 that may inhibit air flow across the electrical components. Additionally, the inorganic box circuit board substrate 602 has the following geometry: the geometry is configured to reduce the length of the airflow path across the electrical components mounted to the inorganic box circuit board substrate 602. For example, the illustrative inorganic box circuit board substrate 602 has a width 604 that is greater than a depth 606 of the inorganic box circuit board substrate 602. In one particular embodiment, for example, the inorganic box circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, as compared to a typical server having a width of about 17 inches and a depth of about 39 inches. Thus, the airflow path 608 extending from the front edge 610 toward the back edge 612 of the inorganic box circuit board substrate 602 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Further, although not illustrated in fig. 6, the various physical resources mounted to the inorganic box circuit board substrate 602 are mounted in corresponding locations such that any two substantially heat generating electrical components are not shielded from each other, as discussed in more detail below. That is, any two electrical components that generate appreciable heat during operation (i.e., greater than nominal heat, which is sufficient to adversely affect cooling of another electrical component) are not linearly mounted to the inorganic box circuit board substrate 602 in line with one another in the direction of the airflow path 608 (i.e., in a direction extending from the front edge 610 toward the rear edge 612 of the inorganic box circuit board substrate 602).

As discussed above, the illustrative sled 400 includes one or more physical resources 620, the physical resources 620 being mounted to the top side 650 of the inorganic box circuit board substrate 602. Although two physical resources 620 are shown in fig. 6, it should be appreciated that in other embodiments sled 400 may comprise one, two, or more physical resources 620. Physical resources 620 may be embodied as any type of processor, controller, or other computing circuitry capable of performing various tasks, such as computing functions and/or controlling the functions of sled 400, depending on, for example, the type or intended function of sled 400. For example, as discussed in more detail below, physical resources 620 may be embodied as high performance processors in embodiments in which sled 400 is embodied as a computation sled; embodied as an accelerator co-processor or circuitry in embodiments in which sled 400 is embodied as an accelerator sled; in embodiments in which sled 400 is embodied as a storage device sled, as a storage device controller; or as a set of memory devices in embodiments in which sled 400 is embodied as a memory sled.

Sled 400 also includes one or more additional physical resources 630, which additional physical resources 630 are mounted to a top side 650 of inorganic box circuit board substrate 602. In an illustrative embodiment, the additional physical resources include a Network Interface Controller (NIC), as discussed in more detail below. Of course, depending on the type and function of sled 400, in other embodiments physical resources 630 may include additional or other electrical components, circuits, and/or devices.

Physical resources 620 are communicatively coupled to physical resources 630 via input/output (I/O) subsystem 622. I/O subsystem 622 may embody circuitry and/or components to facilitate input/output operations with physical resources 620, physical resources 630, and/or other components of sled 400. For example, I/O subsystem 622 may embody or otherwise include a memory controller hub, an input/output control hub, an integrated sensor hub, a firmware device, a communication link (i.e., a point-to-point link, a bus link, a wire, a cable, a waveguide, a light guide, a printed circuit board trace, etc.), and/or other components and subsystems that facilitate input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as or otherwise includes a double data rate 4 (DDR 4) data bus or a DDR5 data bus.

In some embodiments, sled 400 may also include resource-to-resource interconnects 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communication. In an illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath interconnect (QPI), an UltraPath interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.

Sled 400 also includes a power connector 640, power connector 640 configured to: when the sled 400 is mounted in the corresponding bay 240, it mates with the corresponding power connector of the bay 240. Sled 400 receives power from a power source of rack 240 via power connectors 640 to supply power to the various electrical components of sled 400. That is, sled 400 does not include any local power source (i.e., an on-board power source) to provide power to the electrical components of sled 400. The elimination of a local or on-board power source facilitates reducing the overall footprint of the inorganic box circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the inorganic box circuit board substrate 602, as discussed above. In some embodiments, a voltage regulator is placed on a bottom side 750 (see fig. 7) of the inorganic box-type circuit board substrate 602 directly opposite the processor 820 (see fig. 8), and power is routed from the voltage regulator to the processor 820 through vias extending through the circuit board substrate 602. This configuration provides increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards where processor power is delivered from the voltage regulator, in part, through printed circuit traces.

In some embodiments, sled 400 may further comprise mounting features 642, which mounting features 642 are configured to mate with mounting arms or other structures of a robot to facilitate placement of sled 600 in frame 240 by the robot. The mounting features 642 may be embodied as any type of physical structure that allows the robot to grasp the sled 400 without damaging the inorganic box circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads (pads) attached to the inorganic case circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, posts, or other similar structures attached to the inorganic case circuit board substrate 602. The particular number, shape, size, and/or composition of mounting features 642 may depend on the design of the robot configured to manage sled 400.

Referring now to fig. 7, in addition to physical resources 630 mounted on a top side 650 of inorganic box circuit board substrate 602, sled 400 also includes one or more memory devices 720 mounted to a bottom side 750 of inorganic box circuit board substrate 602. That is, the inorganic case type circuit board substrate 602 is embodied as a double-sided circuit board. Physical resources 620 are communicatively coupled to memory device 720 via I/O subsystem 622. For example, the physical resources 620 and the memory device 720 may be communicatively coupled by one or more vias extending through the inorganic chassis substrate 602. In some embodiments, each physical resource 620 may be communicatively coupled to a different set of one or more memory devices 720. Alternatively, in other embodiments, each physical resource 620 may be communicatively coupled to each memory device 720.

Memory device 720 may be embodied as any type of memory device capable of storing data for physical resource 620 during operation of sled 400, such as any type of volatile (e.g., Dynamic Random Access Memory (DRAM), etc.) or non-volatile memory, volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium non-limiting examples of volatile memory may include various types of Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), one particular type of DRAM that may be used in a memory module is Synchronous Dynamic Random Access Memory (SDRAM), in particular embodiments, the DRAM of the memory assembly may conform to standards promulgated by JEDEC, such as JESD 7379 for SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for SDRAM 3, JESD79-4A for DDR4 SDRAM, pd 79-pdp pd 24 for low power SDRAM, dr 6324, dr-2 for DDR3, and dr-6853, which may be based on such standards as dr 209, dr-6853, dr-dr 3, and dr3, dr.

In one embodiment, the memory devices are block addressable memory devices, such as memory devices based on NAND or NOR technology. The memory devices may also include next generation non-volatile devices, such as Intel 3D Xpoint^TMMemory or other byte-addressable write-in-place (write-in-place) non-volatile memory devices. In one embodiment, the memory device may be or include a memory device using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, Magnetoresistive Random Access Memory (MRAM) memory incorporating memristor technology, resistive memory including metal oxide radicals, oxygen vacancy radicals, and conductive bridge random access memory (CB-RAM), or Spin Transfer Torque (STT) -MRAM, a spintronic magnetic junction memory-based device, a Magnetic Tunneling Junction (MTJ) -based device, a DW (domain wall) and SOT (spin-orbit transfer) based device, a thyristor-based memory device, or a combination of any of the above, Or other memory. A memory device may refer to the die itself and/or a packaged memory product. In some embodiments, the memory device may include a transistor-less stackable cross-point architecture, where the memory cells are located at the intersections of word lines and bit lines and are individually addressable, and where the bit storage is based on a change in the bulk resistance.

Referring now to fig. 8, in some embodiments, sled 400 may be embodied as a computing sled 800. The computing sled 800 is optimized or otherwise configured to perform computing tasks. Of course, as discussed above, the computing sled 800 may rely on other sleds (such as acceleration sleds and/or storage sleds) to perform such computing tasks. Computing sled 800 includes various physical resources (e.g., electrical components) similar to those of sled 400, which have been identified in FIG. 8 using the same reference numerals. The description of such components provided above with respect to fig. 6 and 7 applies to the corresponding components of the computing sled 800 and is not repeated herein for clarity of the description of the computing sled 800.

In the illustrative computing sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in fig. 8, it should be appreciated that in other embodiments, the computing sled 800 may include additional processors 820. Illustratively, the processor 820 is embodied as a high performance processor 820 and may be configured to operate at a relatively high power rating. Although the processor 820 generates additional heat when operating at greater than the rated power of a typical processor (which operates at approximately 155-230W), the enhanced thermal cooling characteristics of the inorganic box circuit board substrate 602 discussed above facilitate this higher power operation. For example, in the illustrative embodiment, the processor 820 is configured to operate at a power rating of at least 250W. In some embodiments, the processor 820 may be configured to operate at a power rating of at least 350W.

In some embodiments, the computing sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communication. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath interconnect (QPI), UltraPath interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

The computing sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a Network Interface Controller (NIC) 832, which Network Interface Controller (NIC) 832 may also be referred to as a Host Fabric Interface (HFI). NIC 832 may be embodied as or otherwise include any type of integrated circuit, discrete circuit, controller chip, chipset, add-in-board (add-in-board), daughter card, network interface card, or other device that may be used by computing sled 800 to connect with another computing device (e.g., with other sled 400). In some embodiments, NIC 832 may be embodied as part of a system on a chip (SoC) that includes one or more processors, or included in a multi-chip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown), both of which are local to the NIC 832. In such an embodiment, the local processor of NIC 832 may be capable of performing one or more functions of processor 820. Additionally or alternatively, in such embodiments, the local memory of NIC 832 may be integrated into one or more components of the computing sled at a board level, a socket level, a chip level, and/or other levels.

The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to: when the computing sled 800 is mounted in the rack 240, it mates with a corresponding optical data connector of the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers that lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to: the method also includes converting incoming optical signals from the rack-side optical data connectors to electrical signals and converting electrical signals to outgoing optical signals to the rack-side optical data connectors. Although shown in the illustrative embodiment as forming part of the optical data connector 834, in other embodiments the optical transceiver 836 may form part of the communication circuit 830.

In some embodiments, the computing sled 800 may further include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to: mate with corresponding connectors of an extended inorganic chassis-less (expansion chassis-less) circuit board substrate to provide additional physical resources to the computing sled 800. This additional physical resource may be used, for example, by processor 820 during operation of computing sled 800. The extended inorganic box circuit board substrate may be substantially similar to the inorganic box circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the extended inorganic box circuit board substrate may depend on the intended function of the extended inorganic box circuit board substrate. For example, the extended inorganic box circuit board substrate may provide additional computing resources, memory resources, and/or storage resources. Thus, additional physical resources of the extended inorganic box circuit board substrate may include, but are not limited to: processors, memory devices, storage devices, and/or accelerator circuits, including, for example, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), security coprocessors, Graphics Processing Units (GPUs), machine learning circuits, or other special purpose processors, controllers, devices, and/or circuits.

Referring now to FIG. 9, an illustrative embodiment of a computation sled 800 is shown. As shown, processor 820, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the inorganic box circuit board substrate 602. The physical resources of the computing sled 800 may be mounted to the inorganic box circuit board substrate 602 using any suitable attachment or mounting technique. For example, various physical resources may be installed in corresponding slots (e.g., processor slots), holders, or racks. In some cases, some of the electrical components may be mounted directly to the inorganic box circuit board substrate 602 via soldering or similar techniques.

As discussed above, separate processor 820 and communication circuit 830 are mounted to the top side 650 of the inorganic box circuit board substrate 602 so that any two heat generating electrical components are not shielded from each other. In the illustrative embodiment, the processor 820 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the inorganic box circuit board substrate 602 such that none of the two of these physical resources are linearly in line with each other along the direction of the airflow path 608. It should be appreciated that although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 does not generate heat or generates nominal heat during operation.

As discussed above with respect to sled 400, memory devices 720 of computing sled 800 are mounted to bottom side 750 of inorganic box circuit board substrate 602. While mounted to bottom side 750, memory device 720 is communicatively coupled to processor 820 on top side 650 via I/O subsystem 622. Because the inorganic case circuit board substrate 602 is embodied as a double-sided circuit board, the memory device 720 and the processor 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the inorganic case circuit board substrate 602. Of course, in some embodiments, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines (mezzanines) on the bottom side of the inorganic box circuit board substrate 602 and may be interconnected with the corresponding processor 820 by a ball grid array.

Each of the processors 820 includes a heat sink 850 affixed thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the inorganic box circuit board substrate 602 (and corresponding vertical spacing of the sleds 400 in the chassis 240), the top side 650 of the inorganic box circuit board substrate 602 includes additional "free" area or space, which facilitates the use of a heat sink 850 having a larger size relative to conventional heat sinks used in typical servers. Additionally, none of the processor heat sinks 850 include a cooling fan attached thereto due to the improved thermal cooling characteristics of the inorganic box circuit board substrate 602. That is, each of the heat sinks 850 is embodied as a fanless heat sink. In some embodiments, the heat sink 850 mounted on top of the processor 820 may overlap with the heat sink attached to the communication circuitry 830 in the direction of the airflow path 608 due to its increased size, as illustratively represented by fig. 9.

Referring now to fig. 10, in some embodiments, sled 400 may be embodied as an accelerator sled 1000. Accelerator sled 1000 is configured to perform specialized computing tasks such as machine learning, encryption, hashing, or other computationally intensive tasks. In some embodiments, for example, the computation sled 800 may offload tasks to the accelerator sled 1000 during operation. Accelerator sled 1000 includes various components similar to those of sled 400 and/or computing sled 800, which have been identified in fig. 10 using the same reference numerals. The description of such components provided above with respect to fig. 6, 7, and 8 applies to the corresponding components of the accelerator sled 1000 and is not repeated herein for clarity of the description of the accelerator sled 1000.

In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuitry 1020. Although only two accelerator circuits 1020 are shown in fig. 10, it should be appreciated that in other embodiments, the accelerator sled 1000 may include additional accelerator circuits 1020. For example, as shown in fig. 11, in some embodiments, the accelerator sled 1000 may include four accelerator circuits 1020. Accelerator circuitry 1020 may be embodied as any type of processor, co-processor, computing circuitry, or other device capable of performing computing or processing operations. For example, accelerator circuitry 1020 may be embodied as, for example, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a security co-processor, a Graphics Processing Unit (GPU), a neuromorphic processor unit, a quantum computer, machine learning circuitry, or other special-purpose processor, controller, device, and/or circuitry.

In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 can be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath interconnect (QPI), UltraPath interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, accelerator circuits 1020 may be daisy-chained (daisy-chained) with a primary accelerator circuit 1020 connected to NIC 832 and memory 720 through I/O subsystem 622 and with a secondary accelerator circuit 1020 connected to NIC 832 and memory 720 through primary accelerator circuit 1020.

Referring now to FIG. 11, an illustrative embodiment of an accelerator sled 1000 is shown. As discussed above, accelerator circuit 1020, communication circuit 830, and optical data connector 834 are mounted to top side 650 of inorganic box circuit board substrate 602. Again, separate accelerator circuitry 1020 and communication circuitry 830 are mounted to the top side 650 of the inorganic box circuit board substrate 602 so that any two heat generating electrical components are not shielded from each other, as discussed above. The memory devices 720 of the accelerator sled 1000 are mounted to the bottom side 750 of the inorganic box circuit board substrate 602, as discussed above with respect to the sled 600. Although mounted to the bottom side 750, the memory device 720 is communicatively coupled to the accelerator circuitry 1020 located on the top side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of the accelerator circuits 1020 may include a heat sink 1070 that is larger than conventional heat sinks used in servers. As discussed above with reference to heat spreader 870, heat spreader 1070 may be larger than conventional heat spreaders because of the "free" area provided by memory resources 720 located on bottom side 750, but not on top side 650, of inorganic box circuit board substrate 602.

Referring now to fig. 12, in some embodiments, sled 400 may be embodied as a storage device sled 1200. Storage sled 1200 is configured to store data in data storage device 1250 that is local to storage sled 1200. For example, during operation, the computing sled 800 or accelerator sled 1000 may store and retrieve data from the data storage 1250 of the storage sled 1200. Storage device sled 1200 includes various components similar to components of sled 400 and/or computing sled 800, which have been identified in fig. 12 using the same reference numerals. The description of such components provided above with respect to fig. 6, 7, and 8 applies to the corresponding components of storage device sled 1200 and is not repeated herein for clarity of the description of storage device sled 1200.

In the illustrative storage sled 1200, the physical resources 620 are embodied as a storage controller 1220. Although only two storage device controllers 1220 are shown in FIG. 12, it should be appreciated that in other embodiments, storage device sled 1200 may include additional storage device controllers 1220. Storage controller 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into data storage 1250 based on requests received via communication circuits 830. In the illustrative embodiment, the storage device controller 1220 is embodied as a relatively low power processor or controller. For example, in some embodiments, storage device controller 1220 may be configured to operate at a power rating of approximately 75 watts.

In some embodiments, storage device sled 1200 may also include controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communication. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, controller-to-controller interconnect 1242 may be embodied as a QuickPath interconnect (QPI), UltraPath interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

Referring now to FIG. 13, an illustrative embodiment of a storage device sled 1200 is shown. In the illustrative embodiment, the data storage 1250 is embodied as or otherwise includes a storage bin 1252 configured to house one or more Solid State Drives (SSDs) 1254. To do so, the storage bin 1252 includes a plurality of mounting slots 1256, each configured to receive a corresponding solid state drive 1254. Each of the mounting slots 1256 includes a plurality of drive guides 1258 that cooperate to define an access opening 1260 of the corresponding mounting slot 1256. The storage bin 1252 is secured to the inorganic box circuit board substrate 602 such that the access opening faces away from the inorganic box circuit board substrate 602 (i.e., toward the front of the inorganic box circuit board substrate 602). Thus, the solid state drives 1254 are accessible when the storage sled 1200 is mounted in the corresponding rack 204. For example, the solid state drives 1254 may be swapped out of the bay 240 (e.g., via a robot) while the storage sled 1200 is still mounted in the corresponding bay 240.

The storage bin 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, in other embodiments, the storage bins 1252 may be configured to store additional or fewer solid state drives 1254. Additionally, in the illustrative embodiment, the solid state drives are mounted vertically in the storage bins 1252, but in other embodiments, the solid state drives may be mounted in different orientations in the storage bins 1252. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long-term data. To do so, the solid state drive 1254 may include the volatile and non-volatile memory devices discussed above.

As shown in fig. 13, a storage device controller 1220, communication circuitry 830, and optical data connector 834 are illustratively mounted to the top side 650 of the inorganic box circuit board substrate 602. Again, as discussed above, the electrical components of the storage device sled 1200 may be mounted to the inorganic case circuit board substrate 602 using any suitable attachment or mounting technique, including, for example, slots (e.g., processor slots), retainers, brackets, solder connections, and/or other mounting or securing techniques.

As discussed above, a separate storage device controller 1220 and communication circuit 830 are mounted to the top side 650 of the inorganic case-type circuit board substrate 602 so that any two heat generating electrical components are not shielded from each other. For example, the storage device controller 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the inorganic box circuit board substrate 602 such that none of the two of these electrical components are linearly in line with each other along the direction of the airflow path 608.

As discussed above with respect to sled 400, memory devices 720 of storage sled 1200 are mounted to bottom side 750 of inorganic case circuit board substrate 602. While mounted to bottom side 750, memory device 720 is communicatively coupled to storage controller 1220 located on top side 650 via I/O subsystem 622. Again, because the inorganic case circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage device controller 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the inorganic case circuit board substrate 602. Each of storage device controllers 1220 includes a heat sink 1270 affixed thereto. As discussed above, none of heat sinks 1270 include a cooling fan attached thereto due to the improved thermal cooling characteristics of inorganic case circuit board substrate 602 of storage device sled 1200. That is, each of the heat sinks 1270 is embodied as a fanless heat sink.

Referring now to fig. 14, in some embodiments, sled 400 may be embodied as a memory sled 1400. The storage sled 1400 is optimized or otherwise configured to provide other sleds 400 (e.g., the compute sled 800, the accelerator sled 1000, etc.) access to a pool of memory local to the memory sled 1200 (e.g., present in two or

more sets

1430, 1432 of memory devices 720). For example, during operation, the compute sled 800 or the accelerator sled 1000 may use a logical address space mapped to physical addresses in the

memory banks

1430, 1432 to remotely write to one or more of the

memory banks

1430, 1432 of the memory sled 1200 and/or to remotely read from one or more of the

memory banks

1430, 1432. Memory sled 1400 includes various components similar to components of sled 400 and/or computing sled 800, which have been identified in fig. 14 using the same reference numerals. The description of such components provided above with respect to fig. 6, 7, and 8 applies to the corresponding components of the memory sled 1400, and is not repeated herein for clarity of the description of the memory sled 1400.

In the illustrative memory sled 1400, the physical resources 620 are embodied as a memory controller 1420. Although only two memory controllers 1420 are shown in FIG. 14, it should be appreciated that in other embodiments, memory sled 1400 may include additional memory controllers 1420. Memory controller 1420 may be embodied as any type of processor, controller, or control circuitry capable of controlling the writing and reading of data into

memory banks

1430, 1432 based on requests received via communications circuitry 830. In the illustrative embodiment, each memory controller 1420 is connected to a

corresponding memory bank

1430, 1432 to write to and read from a memory device 720 within the corresponding

memory bank

1430, 1432 and to implement any permissions (e.g., read, write, etc.) associated with the sled 400 as follows: the sled 400 has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).

In some embodiments, memory sled 1400 may also include controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communication. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath interconnect (QPI), UltraPath interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. Thus, in some embodiments, the memory controller 1420 may access memory within a memory bank 1432 associated with another memory controller 1420 through a controller-to-controller interconnect 1442. In some embodiments, the expandable memory controller is made up of multiple smaller memory controllers (referred to herein as "chiplets") on a memory sled (e.g., memory sled 1400). The chiplets can be interconnected (e.g., using EMIB (embedded multi-die interconnect bridge)). The combined chiplet memory controller can be extended (scale up) to a relatively large number of memory controllers and I/O ports (e.g., up to 16 memory channels). In some embodiments, memory controller 1420 may implement memory interleaving (e.g., one memory address is mapped to memory bank 1430, the next memory address is mapped to memory bank 1432, and the third address is mapped to memory bank 1430, etc.). The interleaving may be managed within memory controller 1420 or across network links to

memory banks

1430, 1432 from CPU sockets (e.g., of compute sled 800) and may improve latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.

Further, in some embodiments, a waveguide connector 1480 may be used to connect the memory sled 1400 to one or more other sleds 400 (e.g., in the same chassis 240 or an adjacent chassis 240) through a waveguide. In the illustrative embodiment, the waveguide is a 64 millimeter waveguide that provides 16 Rx (i.e., receive) channels and 16 Tx (i.e., transmit) channels. In the illustrative embodiment, each channel is 16 GHz or 32 GHz. In other embodiments, the frequency may be different. The use of waveguides may provide high throughput access to memory pools (e.g., memory groups 1430, 1432) to another sled (e.g., sled 400 in the same bay 240 as the memory sled 1400 or an adjacent bay 240) without increasing the load on the optical data connector 834.

Referring now to fig. 15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center 100. In an illustrative embodiment, the system 1510 includes an orchestrator server 1520, the orchestrator server 1520 may be embodied as a managed node comprising a computing device (e.g., a processor 820 on the computing sled 800) that executes management software (e.g., a cloud operating environment such as OpenStack) that is communicatively coupled to a plurality of sleds 400, the plurality of sleds 400 comprising a number of computing sleds 1530 (e.g., each similar to the computing sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sleds 1200). One or more of the

sleds

1530, 1540, 1550, 1560 can be grouped into a managed node 1570, such as by the orchestrator server 1520, to collectively execute a workload (e.g., an application 1532 executing in a virtual machine or container). Managed node 1570 may be embodied as an assembly of physical resources 620 from the same or different sleds 400, such physical resources 620 as processors 820, memory resources 720, accelerator circuitry 1020, or data storage 1250. Further, a managed node may be established, defined, or "spun-up" by orchestrator server 1520 at the time when the workload is to be assigned to the managed node, or at any other time, and may exist regardless of whether any workload is currently assigned to the managed node. In an illustrative embodiment, orchestrator server 1520 may selectively allocate and/or deallocate (deallocate) physical resources 620 from sleds 400, and/or add or remove one or more sleds 400 from managed node 1570, according to quality of service (QoS) goals associated with a service level agreement for a workload (e.g., application 1532) (e.g., performance goals associated with throughput, latency, instructions per second, etc.). In doing so, orchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of managed node 1570 and compare the telemetry data to a quality of service target to determine whether the quality of service target is met. Orchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from managed node 1570 while still meeting the QoS goals, thereby freeing those physical resources for use in another managed node (e.g., to perform a different workload). Alternatively, if the QoS target is not currently being met, the orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing. Similarly, if the orchestrator server 1520 determines that deallocating physical resources will result in the QoS target still being met, the orchestrator server 1520 may determine to dynamically deallocate physical resources from the managed node.

Additionally, in some embodiments, the orchestrator server 1520 may identify trends in resource utilization of the workload (e.g., the application 1532), such as by: the method may further include identifying an execution phase of the workload (e.g., the time period in which different operations are executed, each operation having different resource utilization characteristics), and preemptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predetermined time period from the beginning of the associated phase). In some embodiments, the orchestrator server 1520 may model performance based on various latency and allocation schemes to place workloads among the computation sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize the following model: the model accounts for the performance of the resource on sled 400 (e.g., FPGA performance, memory access latency, etc.) and the performance of the path through the network to the resource (e.g., FPGA) (e.g., congestion, latency, bandwidth). Thus, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., in addition to the latency associated with the path through the network between the computing sled executing the workload and the sled 400 in which the resource is located, the latency associated with the performance of the resource itself).

In some embodiments, the orchestrator server 1520 may generate a heat generation map in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400, and allocate resources to managed nodes according to the heat generation map and predicted heat generation associated with different workloads to maintain target temperature and heat distributions in the data center 100. Additionally or alternatively, in some embodiments, orchestrator server 1520 may organize received telemetry data into a hierarchical model that indicates relationships between managed nodes (e.g., spatial relationships (such as physical locations of resources of managed nodes within data center 100), and/or functional relationships (such as groupings of managed nodes by customers that the managed nodes serve, types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). based on differences in physical locations and resources in managed nodes, a given workload may exhibit different resource utilization across resources of different managed nodes (e.g., resulting in different internal temperatures, using different percentages of processor or memory capacity.). if a workload is reassigned from one managed node to another managed node, the orchestrator server 1520 may determine the difference based on the telemetry data stored in the hierarchical model and account the difference in the prediction of future resource utilization for the workload to accurately balance resource utilization in the data center 100.

To reduce the computational load on the orchestrator server 1520 and the data transmission load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to determine locally (e.g., on the sleds 400) whether the telemetry data generated by the sleds 400 meets one or more conditions (e.g., meets a predetermined threshold of available capacity, meets a predetermined threshold of temperature, etc.). Each sled 400 may then report the simplified results (e.g., "yes" or "no") back to the orchestrator server 1520, which may utilize the simplified results to determine resource allocation to the managed nodes.

Referring now to fig. 16, a block diagram of a system 1600 for a quality of experience (QoE) software stack representing a network services framework for deploying, orchestrating and managing services provided by Virtualized Network Functions (VNFs) that may be executed in a system 1510 is provided. As further described herein, the web services framework uses computation, network and memory based performance scores, and resource allocation remediation (reparation) based thereon to provide service guarantees in the system 1510. System 1600 is mapped to a QoE-based industry framework. The system 1600 provides quality of service (QoS) per Virtualized Network Function (VNF) as a combination of QoS per CPU thread and QoS per Polling Mode Driver (PMD) thread based on a data plane development library (e.g., Data Plane Development Kit (DPDK)). In addition, the network service framework provides per second recalibration using monitoring and resource assessment agents on QoS to QoE shares. The resource assessment agent may adjust resources to maintain QoE in the VNF (or other Virtual Machine (VM)) within a given range.

The network services framework provided by system 1600 includes QoE monitors, service level target (S L O) monitors, predictive QoS monitors, S L O agents, predictive QoS agents, CPU Service Computing Unit (SCU) management agents, network Service Network Unit (SNU) management agents, platform telemetry collector agents, remediation agents, and Virtual Machine Managers (VMMs) over the underlying Hardware (HW) system 1600 provides network and computing power, performance QoS, reliability (e.g., in terms of network bandwidth and CPU cycles) and availability (e.g., recalculated by periodic management agents for SCU and SNU) using one or more of such components, system 1600 provides an autonomic environment that, in some embodiments, includes a QoE model for the end user, and a functional mapping of QoE parameters to workload S L O parameters.

In some embodiments, the sled device described with respect to fig. 1-15 may implement the web services framework of system 1600. Illustratively, the system 1600 provides an orchestrator server 1520, a computing sled 1610, a memory sled 1620, and an accelerator sled 1640, all interconnected with a network 1640 (e.g., the Internet). Orchestrator server 1520 includes service management logic 1602, which may be embodied as any device or circuitry that performs the functions described herein, such as receiving CPU and network metrics from

agents

1614, 1624, and 1644 executing in computation sled 1610, memory sled 1620, and accelerator sled 1640, respectively.

The illustrative computation sled 1610 includes an application 1612 (e.g., a workload executing on behalf of a user) and an agent 1614 configured to collect computation and network metrics. The broker 1614 may then determine from the computation and network metrics a Service Compute Unit (SCU) and a Service Network Unit (SNU) that indicate the available computation and network resources available for servicing the workload (e.g., application).

The illustrative memory sled 1620 comprises one or more memory devices 1622 (e.g., volatile and non-volatile memory devices) and a proxy 1624. Similar to agent 1614, agent 1624 may collect computations and network metrics and compute SCU and SNU. The illustrative accelerator sled 1630 includes one or more accelerator devices 1632 (e.g., field programmable gate arrays (FGPAs), Application Specific Integrated Circuits (ASICs), Graphics Processing Units (GPUs), etc.) and a proxy 1634 that collects computations and network metrics to compute the SCU and SNU. It is noted that system 1600 may include a plurality of computation sleds 1610, memory sleds 1620, and accelerator sleds 1630.

Further, the components of system 1600 (e.g., agents, monitors, and telemetry collectors) may be implemented as acceleration entities that are executed, for example, on one or more accelerator sleds 1630, or accelerators executing on other components in system 1600. To avoid computing platform cycles being consumed by those components, an accelerator device (e.g., a Field Programmable Gate Array (FPGA) derivative or acceleration in a package) may allow a given tenant of system 1600 to register an accelerated kernel bitstream for monitoring, prediction, and processing telemetry. The acceleration may include proprietary system QoE acceleration logic configured to route tenant telemetry from the converged telemetry architecture to each of the registered bitstreams. Doing so allows callbacks (callbacks) to be seamlessly routed (seamless route) from the accelerated kernel bitstream to the CPU and other components. The acceleration logic includes an acceleration kernel bitstream monitor, a proxy, and a telemetry processor for each tenant. The acceleration logic also exposes (expose) acceleration functions (e.g., for functions such as Fast Fourier Transforms (FFTs)) that may be used by the agent. In addition, the acceleration logic manages and routes flows between the acceleration component and the non-acceleration component.

Referring now to fig. 17, the orchestrator server 1520 may be embodied as any type of computing device capable of performing the functions described herein. As shown, the illustrative orchestrator server 1520 includes a compute engine 1702, an input/output (I/O) subsystem 1708, communication circuitry 1710, and one or more data storage devices 1714. Of course, in other embodiments, the orchestrator server 1520 may include other or additional components, such as those commonly found in a computer (e.g., a display, peripheral devices 1716, etc.). Additionally, in some embodiments, one or more of the illustrative components may be incorporated into or otherwise form a part of another component.

The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing the various computing functions described below. In some embodiments, the compute engine 1702 may be embodied as a single device, such as an integrated circuit, an embedded system, a Field Programmable Gate Array (FPGA), a system on a chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1702 includes or is embodied as a processor 1704 and a memory 1706. The processor 1704 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1704 may be embodied as a single or multi-core processor(s), microcontroller, or other processor or processing/control circuit. In some embodiments, the processor 1704 may be embodied as, include or be coupled to an FPGA, an Application Specific Integrated Circuit (ASIC), reconfigurable hardware or hardware circuits, or other dedicated hardware for facilitating the performance of the functions described herein. As shown, the processor 1704 may also include the aforementioned service management logic 1602.

Memory 1706 may be embodied as any type of volatile (e.g., Dynamic Random Access Memory (DRAM), etc.) or non-volatile memory or data storage device capable of performing the functions described herein.a volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium.a non-limiting example of a volatile memory may include various types of Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). one particular type of DRAM that may be used in a memory module is Synchronous Dynamic Random Access Memory (SDRAM). in particular embodiments, the DRAM of the memory assembly may conform to standards promulgated by JESD standards such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3, JESD79-4A for DDR4 SDRAM, JESD 209-5393 for low power DDR L PDDR 209, JESD2, JESD 209-L for DDR 6853, and a communication interface based on these standards may be referred to as PDDR 209-dr L, dr 73, and may be implemented at this DDR interface 209, dr 84, which may be based on these standards.

In one embodiment, the memory devices are block addressable memory devices, such as memory devices based on NAND or NOR technology. The memory device may also include a non-volatile device, such as a three-dimensional cross-point memory device (e.g., Intel 3D XPoint)^TMMemory) or other byte-addressable write-in-place non-volatile memory devices. In one embodiment, the memory device may be or may include a memory device using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, Magnetoresistive Random Access Memory (MRAM) memory incorporating memristor technology, including metal oxide based, oxygen vacancy based resistive memory, and conductive bridge random access memory (CB-RAM), or Spin Transfer Torque (STT) -MRAM, spintronics magnetic junction based memory devices, Magnetic Tunneling Junction (MTJ) based devices, DW (domain wall) and SOT (spin orbit transfer) based devices, thyristor based memory devices, or a combination of any of the above, or other memory. A memory device may refer to the die itself and/or a packaged memory product.

In some embodiments, a 3D crosspoint memory (e.g., Intel 3D XPoint)^TMMemory) may include a transistor-less stackable cross-point architecture in which memory cells are located at the intersections of word lines and bit lines and are individually addressable, and in which bit storage is based on changes in the body resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the processor 1704. In operation, the memory 1706 may store various software and data used during operation, such as task request data, kernel mapping data, telemetry data, applications, programs, libraries, and drivers.

The compute engine 1702 is communicatively coupled to other components of the orchestrator server 1520 via an I/O subsystem 1708, which I/O subsystem 1708 may embody the following circuits and/or components: the circuitry and/or components facilitate input/output operations with the compute engine 1702 (e.g., with the processor 1704 and/or memory 1706) and other components of the orchestrator server 1520. For example, I/O subsystem 1708 may embody or otherwise include a memory controller hub, an input/output control hub, an integrated sensor hub, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate input/output operations. In some embodiments, the I/O subsystem 1708 may form part of a system on a chip (SoC) and be incorporated into the compute engine 1702 along with one or more of the processor 1704, memory 1706, and other components of the orchestrator server 1520.

The communication circuitry 1710 may be embodied as any communication circuitry, device, or collection thereof capable of enabling communication over a network 1640 between the orchestrator server 1520 and another computing device (e.g., the computing sled 1610, the memory sled 1620, the accelerator sled 1640, etc.). The communication circuitry 1710 may be configured to enable such communication using any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet, Bluetooth, Wi-Fi, WiMAX, etc.).

The illustrative communication circuit 1710 includes a Network Interface Controller (NIC) 1712, which Network Interface Controller (NIC) 1712 may also be referred to as a Host Fabric Interface (HFI). The NIC 1712 may be embodied as one or more add-in boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the orchestrator server 1520 to connect with another computing device (e.g., the computing sled 1610, the memory sled 1620, the accelerator sled 1640, etc.). In some embodiments, NIC 1712 may be embodied as part of a system on a chip (SoC) that includes one or more processors, or included in a multi-chip package that also contains one or more processors. In some embodiments, the NIC 1712 may include a local processor (not shown) and/or a local memory (not shown), both of which are local to the NIC 1712. In such embodiments, the local processor of NIC 1712 may be capable of performing one or more functions of processing engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1712 may be integrated into one or more components of the orchestrator server 1520 at a board level, a socket level, a chip level, and/or other levels.

The illustrative data storage device(s) 1714 may be embodied as any type of device configured for short-term or long-term storage of data (such as, for example, memory devices and circuits, memory cards, hard drives, solid-state drives, or other data storage devices). Each data storage device 1714 may include a system partition that stores data and firmware code for data storage device 1714. Each data storage device 1714 may also include an operating system partition that stores data files and executable files for the operating system.

Additionally or alternatively, the orchestrator server 1520 may include one or more peripheral devices 1716. Such peripheral devices 1716 can include any type of peripheral device commonly found in computing devices such as displays, speakers, mice, keyboards and/or other input/output devices, interface devices, and/or other peripheral devices. Further, each of

sleds

1610, 1620 and 1630 may include components comparable to those of orchestrator server 1520, with the possible exceptions:

sleds

1610, 1620 and 1630 omit service management logic 1602.

Referring now to fig. 18, the orchestrator server 1520 may establish an environment 1800 during operation. The illustrative environment 1800 includes a network communicator 1820 and a service manager 1830. Each component of environment 1800 may be embodied as hardware, firmware, software, or a combination thereof. Thus, in some embodiments, one or more components of the environment 1800 may be embodied as a collection of circuits or electrical devices (e.g., the network communicator circuit 1820, the service manager circuit 1830, etc.). It should be appreciated that in such embodiments, one or more of the network communicator circuit 1820 or the service manager circuit 1830 may form part of one or more of the compute engine 1702, the communications circuit 1710, the I/O subsystem 1708, and/or other components of the orchestrator server 1520.

In the illustrative environment 1800, the network communicator 1820, which may be embodied in hardware, firmware, software, virtualized hardware, emulated architecture, and/or combinations thereof, as discussed above, is configured to: facilitating inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from, respectively, the orchestrator server 1520. To do so, network communicator 1820 is configured to receive and process data packets from one system or computing device (e.g., computing sled 1610), and to prepare and send data packets to another computing device or system (e.g., memory sled 1620, accelerator sled 1630). Thus, at least a portion of the functionality of the network communicator 1820 may be performed by the communication circuitry 1710 in some embodiments, and by the NIC 1712 in an illustrative embodiment.

The service manager 1830, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to: the management of computing and network resources is coordinated according to the techniques described herein. To do so, in the illustrative embodiment, service manager 1830 includes a monitor component 1832, a forecast component 1834, and a remediation component 1836.

In an illustrative embodiment, monitoring component 1832 is configured to receive CPU and network metrics from sleds in system 1600, in addition, monitoring component 1832 is used to receive indications of the amount of available Service Compute Units (SCUs) and Service Network Units (SNUs), each of the SCUs and SNUs is a logical representation of the available compute units and network units on a computing device (e.g., compute sled 1610) in system 1600 in service manager 1830 to receive these metrics, monitoring component 1832 may communicate with agents executing on devices in system 1600, such as

agents

1614, 1624, and 1634 to receive these metrics, monitoring component 1832 is also used to determine whether a given resource meets S L O (service level target) requirements, such as specified within a service level (S L A).

In an illustrative embodiment, the predictive component 1834 is configured to receive available SNU data and SCU data and determine computing devices in the system 1600 that are capable of providing resources, such as when a Virtual Machine (VM) instance is launched the predictive component 1834 may evaluate, for example, S L A and quality of service (QoS) requirements associated with a given user to determine suitable ones of the computing devices associated with available SCU and SNU units that satisfy S L O that may also represent S L O units in the service manager 1830.

In an illustrative embodiment, the remediation component 1836 is configured to determine and generate one or more remedial actions upon determining that one of the computing or network resources does not satisfy (or is predicted to not satisfy) a given S L O example remedial actions include assigning computing and network resources to a given computing sled, relocating a VM to another computing sled, assigning resources to an accelerator sled, and so forth.

Referring now to FIG. 19, orchestrator server 1520 (e.g., one or more of the sleds in system 1600) that incorporates the components of system 1600 in execution may execute method 1900 to manage service guarantees in system 1600, for example, method 1900 may be executed upon starting a given Virtual Machine (VM) on a computing sled in block 1902. in block 1902, available SCUs and SNUs are determined, for example, to do so, in block 1904 orchestrator server 1520 determines available SCUs and SNUs from CPU and network metrics collected from agents executing on the computing device.

In block 1906, a service class (C L oS) of QoE is selected (e.g., by a scheduler in system 1600) for a given VM to be booted in block 1908 the orchestrator server 1520 matches the host on which the VM can be booted to the service level for the VM in block 1910, the selected C L oS is mapped to an S L O unit in block 1912 the available SNUs, SCUs, and predicted QoS are evaluated for each host computing device (e.g., compute sled 1610) based thereon in block 1914 the orchestrator server 1520 places the VM in the appropriate host computing device in block 1916 the orchestrator server 1520 launches the prediction result VM. at the host computing device made by the QoS proxy is sent to the remediation proxy in block 1918 the orchestrator server 1520 generates one or more scores associated with the performance of the VM that is booted in the host computing device.

In block 1920, the S L O agent may determine whether the performance of the VM satisfies the requested S L O. to do so, the S L O agent calculates the metrics received from the performance monitor S L O agent may send the results to the remediation agent.

A Quality Solutions Stack (QSS) monitor at the orchestrator server 1520 may include modules to define QoEs and process templates.

The QoS is calculated at each control plane aggregation based on infrastructure VM aggregation and application computation and data VM aggregation.

In terms of hardware, embodiments may be adapted based on software and hardware co-design management and orchestration methods. Doing so allows for reduced Total Cost of Ownership (TCO) due to a smaller amount of software management overhead, improved response time by being able to process data in an accelerated manner, and multi-tenant support.

In some embodiments, QoS may be defined as a function of delay, jitter, latency, and bandwidth, and QoE may be defined as a function of QoS. QoE parameters may include Round Trip Time (RTT) and Mean Opinion Score (MOS) at the user level. For example, RTT for 10,000 UDP packets sent over the network, where PING is defined as the average of all RTTs, and JITTER, which is the 99.9% quantile of all RTTs minus the minimum RTT, can be expressed as: . MOS at user level translates to decode time at application level and decomposes into CPU and RAM consumption at workload level, as well as delay, hop (hop) and packet loss at network level, retransmission to link level and delay. Given a

The control mechanism at each layer may be implemented in the following manner. By PING and based on RFC 6928 or

To calculate an expected S L o at that layer for RTT after making two RTT measurements, the first measurement SRTT is initialized to the first measurement value, i.e. to the first measurement value

. Typical RTT values for speech as recommended by ITU-T g.114 have a maximum value of 150 ms one-way delay. If the window size is 64 KB =0.5 MBits, the throughput is 0.5/0.15=3.3.33 MBits/s-minimum.

To handle this scenario and ensure a minimum bandwidth to the VNF, the bandwidth share received by each VNF in the host may be controlled on the tenant interface.

The following provides example S L O definitions:

'slo'：{

'slo_definition'：{

'slos'：[

{

'SCU：'GIPS',

..... //

}

{

'value'：['100：200：400：500'],

'type'：'SNU',

'id'：29,

'Description'：'service network unit'

}

]

}

}。

the following provides an example QoE template definition:

QOE_CLOS：{

'HICritical'：{

'RTT'：{

'value'：[10,20]

'units'：'ms'

}

'MedCritical'：{

'RTT'：{

'value'：[21,30]

'units'：'ms'

}

'MinCritical'：{

'RTT'：{

'value'：[40,50]

'units'：'ms'

}

}。

in the above, the "value" tag of the SNU has the following format: 'value': [ minimum guaranteed downlink SNU: maximum downlink SNU: minimum guaranteed uplink SNU: maximum upstream SNU ].

The following is an example algorithm for mapping QoE classes to S L P parameters:

if QOE _ C L OS is "HiCrical";

allocating 2 to 4 SCUs;

400-500 SNUs were allocated;

sending an alert to the S L O agent if RTT > max at the QOE monitor;

at the host, IPC and cache metrics from the performance monitor agent are examined to classify the VNF as computationally heavy;

if true, S L O is notified that the agent increased the SCU, resulting in more CPUs

. Allocating a cache in the BDX system if the cache miss is high;

if not computationally burdensome, the IO _ trans counter is checked and 90% of the RX-TX > SNU is classified as network burdensome;

if true, the S L O agent increments the SNU;

adding a port to the VM using libvirt;

monitoring RTT and jitter at QOE monitors and establishing a ratio;

if a threshold value such as VM1 is crossed:

calculating the required time delay throughput;

applying proportional throttling by a DPDK virtual host (vhost) egress traffic supervisor (policer) and ingress traffic supervisor;

weighted throttling of VMs based on a ratio of achieved QOE to S L O (TBD);

if more than 10% of the VMs are affected, then performing a migration (migrate);

allocating a dynamic pNIC PF in an RSD environment;

load balancing is done by adding pmd threads for the socket hosting the most affected VMs.

Advantageously, VNFs launched in the same or different hosts will get the same bandwidth limitation according to the defined SNU. In a particular host, the sum of the minimum bandwidth sets for all VNFs in a particular tenant interface should not exceed the actual throughput achieved by that interface. However, the sum of the maximum bandwidth sets may be greater than the actual throughput of the tenant interface. The minimum and maximum sets of throughputs may not exceed the actual throughputs of the tenant interfaces. A particular VNF with an SNU will have a guaranteed minimum bandwidth and can use up to a maximum throughput if other VNFs in the same host on the tenant interface do not use the SNU.

In some embodiments, each host or computing sled periodically advertises the available SNUs for each tenant interface to the service assurance manager. System 1600 may centralize control of all hosts and help schedule VNFs. The network metrics for each VM in the host are also displayed as a graph for monitoring. By using the DPDK library, VNF network throughput performance can be increased and latency can be minimized. In addition, network drivers and forwarding threads are moved to user space, which results in increased performance. The physical port (eth 0) attached to the tenant bridge is occupied by the poll mode driver, causing the kernel to lose control of the port. The VNF interface (vnet) attached to the integrated bridge is of the type dpdkhostresser. The performance of the VNF is further improved by increasing the number of forwarding threads and allocating 1G of large pages to the VM. Performance may also be improved by assigning the forwarding thread to a CPU core that is isolated from operating system scheduling. Performance can also be improved in a NUMA (non-uniform memory access) aware system by allocating a forwarding thread servicing a physical port to a CPU core on the socket in which the physical port is located. Performance may also be improved by assigning the transmitting and receiving threads to the same socket in which the forwarding thread is scheduled.

In some embodiments, the ports are managed by a DPDK. In this case, QoS and rate limiting control cannot generally be applied. However, open source solutions may provide a method for ingress and egress throughput control. Further, ingress and egress network throughput may be controlled by applying ingress and egress traffic policing (policing) rates on virtual host ports connected to the integrated bridge via setting ingress _ policing _ rate and aggregation _ policing _ rate parameters of the ports at the integrated bridge. However, using this approach, the maximum bandwidth of the VNF may be set. In this case, the SNU minimum and maximum values will be the same, and over subscription (oversubscription) will not be achieved. On such systems, applications that do not require any change in QoS (e.g., mission critical video applications) are scheduled.

Furthermore, as previously described, embodiments may be adapted for software and hardware co-design. For example, the hardware offload architecture may include interface and management logic, a platform telemetry distributor, a callback manager, and Intellectual Property (IP) prediction and telemetry acceleration functions. The interface and management logic exposes to the software stack (e.g., of system 1600) an interface that allows a particular tenant executing a QoE instance to instantiate bit streams for the two agents and the two predictor components discussed above, as well as for the agent responsible for handling the telemetry sent by the telemetry distributor.

The platform telemetry distributor is to collect corresponding performance counters exposed by a platform convergence telemetry architecture associated with each tenant and automatically deliver the counters to a bitstream for processing the telemetry. The bitstream may share the processed data to different bitstream predictors (e.g., simultaneously). When registering a particular QoE accelerated bitstream via the interface and management logic, the tenant may specify what telemetry data the predictor and telemetry processor use.

The callback manager exposes an interface for the bitstream to send callbacks to corresponding software entities (e.g., various QoE managers, CPUs, networks, etc.). The IP prediction and telemetry acceleration functions IP library exposes a set of functions that can be used by the bitstream. The library also provides access acceleration functionality exposed by the dedicated bitstream logic. Furthermore, prior to registering the user bit stream, the software stack may check what functionality is exposed by a given IP via the CPUID mechanism.

Examples of the invention

Illustrative examples of the techniques disclosed herein are provided below. Embodiments of these techniques may include any one or more of the examples described below, as well as any combination thereof.

Example 1 includes an orchestrator server for managing service guarantees for a platform, the orchestrator server comprising one or more processors and memory storing a plurality of instructions that, when executed on the one or more processors, cause the orchestrator server to receive a request to launch a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification, map the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating a required network bandwidth and computing capacity specified in a service level agreement (S L A), launch the VM on a computing device of a plurality of computing devices identified according to the mapped S L O units, generate one or more performance scores associated with the VM, and determine whether performance of the VM on the computing device satisfies each of the one or more S L units according to the generated one or more scores.

Example 2 includes the subject matter of example 1, and wherein the plurality of instructions further cause the orchestrator server to determine a plurality of available service computing units and a plurality of available service network units in the platform.

Example 3 includes the subject matter of any of examples 1 and 2, and wherein determining the plurality of available service computing units and the plurality of available service network units comprises: determining the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from a broker application executing on a computing device in the platform.

Example 4 includes the subject matter of any of examples 1-3, and wherein identifying computing devices from the mapped S L O units comprises evaluating the plurality of available service computing units, the plurality of available service network units, and the predicted quality of service (QoS) for each of the plurality of computing devices.

Example 5 includes the subject matter of any of examples 1-4, and wherein the plurality of instructions further cause the orchestrator server to place the VM in the identified computing device.

Example 6 includes the subject matter of any of examples 1-5, and wherein the plurality of instructions further cause the orchestrator server to generate a remedial action to perform when it is determined that at least one of the S L O cells is not satisfied.

Example 7 includes the subject matter of any of examples 1-6, and wherein the plurality of instructions further cause the orchestrator server to cause the identified computing device to perform a remedial action.

Example 8 includes a method for managing service guarantees for a platform, the method comprising receiving, by an orchestrator server, a request to launch a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification, mapping, by the orchestrator server, the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating a required network bandwidth and computing capacity specified in a service level agreement (S L a), launching, by the orchestrator server, the VM on a computing device of a plurality of computing devices identified according to the mapped S L O units, generating, by the orchestrator server, one or more scores associated with performance of the VM, and determining, by the orchestrator server, according to the generated one or more scores, whether the performance of the VM on the computing device satisfies each of the one or more S L O units.

Example 9 includes the subject matter of example 8, and further comprising: a plurality of available service computing units and a plurality of available service network units are determined in the platform and by an orchestrator server.

Example 10 includes the subject matter of any one of examples 8 and 9, and wherein determining the plurality of available service computing units and the plurality of available service network units comprises: determining, by an orchestrator server, the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from agent applications executing on computing devices in the platform.

Example 11 includes the subject matter of any of examples 8-10, and wherein identifying computing devices according to the mapped S L O units comprises evaluating, by the orchestrator server, the plurality of available service computing units, the plurality of available service network units, and the predicted quality of service (QoS) for each of the plurality of computing devices.

Example 12 includes the subject matter of any one of examples 8-11, and further comprising: placing, by the orchestrator server, the VM in the identified computing device.

Example 13 includes the subject matter of any of examples 8-12, and further comprising generating a remedial action to perform upon a determination by the orchestrator server that at least one of the S L O cells is not satisfied.

Example 14 includes the subject matter of any one of examples 8-13, and further comprising causing, by the orchestrator server, the identified computing device to perform the remedial action.

Example 15 includes an orchestrator server to manage service guarantees for a platform, comprising circuitry to receive a request to launch a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification, means to map the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating a required network bandwidth and computing capacity specified in a service level agreement (S L a), circuitry to launch the VM on a computing device of a plurality of computing devices identified according to the mapped S L O units, means to generate one or more scores associated with performance of the VM, and means to determine whether the performance of the VM on the computing device satisfies each of the one or more S L O units according to the generated one or more scores.

Example 16 includes the subject matter of example 15, and further comprising: means for determining, in the platform, a plurality of available service computing units and a plurality of available service network units.

Example 17 includes the subject matter of any of examples 15 and 16, and wherein the means for determining the plurality of available service computing units and the plurality of available service network units comprises: means for determining the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from a broker application executing on a computing device in the platform.

Example 18 includes the subject matter of any of examples 15-17, and further comprising means for evaluating the plurality of available serving computing units, the plurality of available serving network units, and the predicted quality of service (QoS) for each of the plurality of computing devices to identify the computing device according to the mapped S L O unit.

Example 19 includes the subject matter of any one of examples 15-18, and further comprising: circuitry for placing the VM in the identified computing device.

Example 20 includes the subject matter of any of examples 15-19, and further includes means for generating a remedial action to perform upon determining that at least one of the S L O cells is not satisfied, and means for causing the identified computing device to perform the remedial action.

Example 21 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that in response to being executed result in an orchestrator server performing the method of any of examples 8-14.

Example 22 includes an orchestrator server comprising circuitry to perform the method of any of examples 8-14.

Claims

1. An orchestrator server for managing service guarantees of a platform, the orchestrator server comprising:

one or more processors; and

a memory storing a plurality of instructions that, when executed on one or more processors, cause the orchestrator server to perform the following;

receiving a request to start a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification;

mapping the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating required network bandwidth and computing capacity specified in a service level agreement (S L A);

booting the VM on a computing device of the plurality of computing devices identified according to the mapped S L O cell;

generating one or more scores associated with performance of the VM; and

determining whether performance of the VM on a computing device satisfies each of the one or more S L O cells according to the generated one or more scores.

2. The orchestrator server of claim 1, wherein the plurality of instructions further cause the orchestrator server to determine a plurality of available service computing units and a plurality of available service network units in the platform.

3. The orchestrator server of claim 2, wherein determining the plurality of available service computing units and the plurality of available service network units comprises: determining the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from a broker application executing on a computing device in the platform.

4. The orchestrator server of claim 3, wherein identifying a computing device according to the mapped S L O units comprises:

evaluating the plurality of available service computing units, the plurality of available service network units, and the predicted quality of service (QoS) for each of the plurality of computing devices.

5. The orchestrator server of claim 4, wherein the plurality of instructions further cause the orchestrator server to place the VM in the identified computing device.

6. The orchestrator server of claim 1, wherein the plurality of instructions further cause the orchestrator server to generate a remedial action to perform when it is determined that at least one of the S L O cells is not satisfied.

7. The orchestrator server of claim 6, wherein the plurality of instructions further cause the orchestrator server to cause the identified computing device to perform a remedial action.

8. A method for managing service guarantees of a platform, comprising:

receiving, by an orchestrator server, a request to start a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification;

mapping, by the orchestrator server, the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating a required network bandwidth and computing capacity specified in a service level agreement (S L a);

booting, by the orchestrator server, the VM on a computing device of the plurality of computing devices identified according to the mapped S L O unit;

generating, by an orchestrator server, one or more scores associated with performance of the VM; and

determining, by the orchestrator server, whether performance of the VM on the computing device satisfies each of the one or more S L O units according to the generated one or more scores.

9. The method of claim 8, further comprising: a plurality of available service computing units and a plurality of available service network units are determined in the platform and by an orchestrator server.

10. The method of claim 9, wherein determining the plurality of available service computing units and the plurality of available service network units comprises: determining, by an orchestrator server, the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from agent applications executing on computing devices in the platform.

11. The method of claim 10, wherein identifying computing devices from the mapped S L O units comprises evaluating, by the orchestrator server, the plurality of available service computing units, the plurality of available service network units, and the predicted quality of service (QoS) for each of the plurality of computing devices.

12. The method of claim 11, further comprising: placing, by the orchestrator server, the VM in the identified computing device.

13. The method of claim 8, further comprising generating a remedial action to be performed upon determining by the orchestrator server that at least one of the S L O cells is not satisfied.

14. The method of claim 13, further comprising: causing, by the orchestrator server, the identified computing device to perform the remedial action.

15. An orchestrator server for managing service guarantees for a platform, comprising:

circuitry for receiving a request to start a Virtual Machine (VM) instance, the request specifying a selection of a service class (C L oS) of a quality of experience (QoS) specification;

means for mapping the selected C L oS to one or more service level target (S L O) units, the one or more S L O units indicating required network bandwidth and computing capacity specified in a service level agreement (S L A);

circuitry for booting the VM on a computing device of a plurality of computing devices identified according to the mapped S L O cell;

means for generating one or more scores associated with performance of the VM; and

means for determining whether performance of the VM on a computing device satisfies each of the one or more S L O cells based on the generated one or more scores.

16. The orchestrator server of claim 15, further comprising: means for determining, in the platform, a plurality of available service computing units and a plurality of available service network units.

17. The orchestrator server of claim 16, wherein means for determining the plurality of available service computing units and the plurality of available service network units comprises: means for determining the plurality of available service computing units and the plurality of available service network units based on computing and network metrics collected from a broker application executing on a computing device in the platform.

18. The orchestrator server of claim 17, further comprising means for evaluating the plurality of available serving computing units, the plurality of available serving network units, and the predicted quality of service (QoS) for each of the plurality of computing devices to identify computing devices according to the mapped S L O units.

19. The orchestrator server of claim 18, further comprising: circuitry for placing the VM in the identified computing device.

20. The orchestrator server of claim 15, further comprising:

means for generating a remedial action to perform upon determining that at least one of the S L O cells is not satisfied, and

means for causing the identified computing device to perform a remedial action.