CN111490779B - Clock recovery circuit and electronic communication device - Google Patents
Clock recovery circuit and electronic communication device Download PDFInfo
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- CN111490779B CN111490779B CN202010307959.5A CN202010307959A CN111490779B CN 111490779 B CN111490779 B CN 111490779B CN 202010307959 A CN202010307959 A CN 202010307959A CN 111490779 B CN111490779 B CN 111490779B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
A clock recovery circuit and an electronic communication device comprising N BBPD circuits, an adder, clock recovery logic, and a phase selector, wherein: each BBPD circuit comprises a data input end and an edge input end, and edge input ends of N-1 BBPD circuits input edge signals with unequal time delays; n is more than or equal to 2; the input end of the adder is coupled with the output ends of the N BBPD circuits, and the output end of the adder is coupled with the input end of the clock recovery logic circuit; the output end of the clock recovery logic circuit is coupled with the input end of the phase selector; the output ends of the phase selectors are respectively coupled with the phase input ends of the N BBPD circuits. The scheme can effectively improve the bandwidth of the clock recovery circuit.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a clock recovery circuit and an electronic communications device.
Background
In serial data communication transmission, a transceiver circuit is responsible for converting internal parallel data with external serial data. At the transmitting end, bit data in the parallel data are sent to a transmission medium one by utilizing the principle of high-speed clock sampling, so that parallel-to-serial conversion is realized. At the receiving end, since the sending end and the receiving end do not share clock signals to synchronize data, the receiving end needs to recover the clock signals from the received serial data stream to realize synchronous operation, and the clock recovery circuit (Clock and Data Recovery, CDR) is responsible for extracting the recovered clock and the recovered data in the serial data. The serial-to-parallel circuit at the later stage converts the recovered data into parallel data and outputs the parallel data, and meanwhile, the characteristic code pattern of the input serial data can be judged, so that byte synchronization is realized.
Referring to fig. 2, a schematic diagram of a clock recovery circuit in the prior art is shown. In fig. 2, the clock recovery circuit is composed of a bang-bang phase detector (BBPD) circuit, a clock recovery logic circuit, a phase selector, and the like.
However, in the prior art, the gain of the BBPD circuit is affected by the clock quality, the input signal quality, and the like, resulting in a narrower bandwidth of the clock recovery circuit.
Disclosure of Invention
The embodiment of the invention solves the problem of how to improve the bandwidth of a clock recovery circuit.
To solve the above technical problem, an embodiment of the present invention provides a clock recovery circuit, including: n BBPD circuits, an adder, clock recovery logic, and a phase selector, wherein: each BBPD circuit comprises a data input end and an edge input end, and edge input ends of N-1 BBPD circuits input edge signals with unequal time delays; n is more than or equal to 2; the input end of the adder is coupled with the output ends of the N BBPD circuits, and the output end of the adder is coupled with the input end of the clock recovery logic circuit; the output end of the clock recovery logic circuit is coupled with the input end of the phase selector; the output ends of the phase selectors are respectively coupled with the phase input ends of the N BBPD circuits.
Optionally, the time delays corresponding to the edge signals of the N-1 BBPD circuits are determined by the duration of the edge signals.
Optionally, the N BBPD circuits have weighting values corresponding to each other; the adder is suitable for adding products of the sampling data output by the N BBPD circuits and the corresponding weighted values.
Optionally, among the weighted values corresponding to the N BBPD circuits, the weighted value corresponding to the BBPD circuit having no delay in the edge signal is the largest, and the delay corresponding to the edge signal of the N-1 BBPD circuits is inversely related to the weighted value.
Optionally, the adder stores weighting values corresponding to the N BBPD circuits.
Optionally, the adder is further coupled to a preset controller, and is adapted to receive weighting values output by the controller and corresponding to the N BBPD circuits one by one.
Optionally, the N BBPD circuits are selected from M PPBD circuits by a preset controller; m is more than or equal to N.
The embodiment of the invention also provides electronic communication equipment, which comprises any one of the clock recovery circuits.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
by setting N BBPD circuits, the gain of the BBPD circuits can be linearized, so that the influence degree of the gain of the BBPD circuits on the quality of input signals and the quality of clocks is reduced, and the bandwidth of the clock recovery circuit is further improved.
Drawings
FIG. 1 is a schematic diagram of a clock recovery circuit in an embodiment of the invention;
fig. 2 is a schematic diagram of a prior art clock recovery circuit.
Detailed Description
From the foregoing, it is known that the gain of the BBPD circuit in the prior art is affected by clock quality, signal jitter, and the like, resulting in a narrower bandwidth of the clock recovery circuit.
In the embodiment of the invention, the gains of the BBPD circuits can be linearized by setting N BBPD circuits, so that the influence degree of the gains of the BBPD circuits on the quality of input signals and the quality of clocks is reduced, and the bandwidth of the clock recovery circuit is further improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a clock recovery circuit including: n BBPD circuits 11, an adder 12, a clock recovery logic circuit 13, and a phase selector 14, wherein:
each BBPD circuit 11 comprises a Data input end Data and an Edge input end Edge, the Data signals input by the Data input ends of the N BBPD circuits 11 are the same, and the Edge input ends of the N-1 BBPD circuits 11 input Edge signals with unequal time delays; the N BBPD circuits 11 are adapted to output corresponding sample data to the adder 12;
adder 12, the input end couples to output end of N BBPD circuit 11, the output end couples to input end of the clock recovery logic circuit 13; the clock offset between the data signal and the edge signal is obtained by corresponding addition of the sampling data output by the N BBPD circuits 11;
a clock recovery logic circuit 13 having an output coupled to an input of the phase selector 14;
the phase selector 14 has output terminals coupled to the phase input terminals of the N BBPD circuits 11, respectively, and is adapted to input the detected phase differences to the N BBPD circuits 11, respectively.
In a specific implementation, for N BBPD circuits 11, an edge input terminal of one BBPD circuit 11 may input an edge signal without delay, and edge input terminals of other N-1 BBPD circuits 11 all input edge signals with delay. For the N-1 BBPD circuits 11, the delays of the edge signals corresponding to different BBPD circuits 11 are different.
For example, n=3, where the edge input of the first BBPD circuit 11 inputs an edge signal without delay, the edge input of the second BBPD circuit 11 inputs an edge signal with delay of a first duration, and the edge input of the third BBPD circuit 11 inputs an edge signal with delay of a second duration, where the first duration is different from the second duration and neither is 0.
In a specific implementation, a one-to-one corresponding delay circuit can be set for the N-1 BBPD circuits 11, and the delays corresponding to the N-1 delay circuits are all unequal, and the delay circuit can be set in front of the Edge signal input end corresponding to the BBPD circuits 11. The Edge signals are input to different time delay circuits, so that the Edge signals with different time delays can be obtained, and the signals input by Edge signal input ends corresponding to different BBPD circuits 11 are Edge signals with different time delays.
In a specific implementation, a one-to-one corresponding delay circuit may be set for N BBPD circuits 11, where the delay of the delay circuit corresponding to one BBPD circuit 11 is 0.
In the embodiment of the present invention, the time delays corresponding to the N-1 BBPD circuits 11 with time delays other than 0 may be set according to the duration of the edge signal.
Taking 3 BBPD circuits 11 as an example, the duration of the edge signal is set to be t, the first BBPD circuit 11 is set to input an edge signal without delay, the delay corresponding to the edge signal input by the second BBPD circuit 11 is set to be t/16, and the delay corresponding to the edge signal input by the third BBPD circuit 11 is set to be t/8.
It will be appreciated that other methods may be used to set the corresponding delays of the BBPD circuits 11, and are not limited to the above example, as long as the delays corresponding to the N-1 BBPD circuits 11 are set differently.
In a specific implementation, weighting values corresponding to each of the N BBPD circuits 11 may be set. In the embodiment of the present invention, the weighting value may be used to perform an operation with the sampling data output from the BBPD circuit 11. The adder 12 may add products of the sampling data output from the N BBPD circuits 11 and the corresponding weighting values, and the obtained result is a clock offset of the edge signal with respect to the data signal.
That is, the product of the sampling data output from each BBPD circuit 11 and the corresponding weighting value may be calculated first, and the sum of the N products may be calculated by the adder 12.
For example, n=3, the sampling data output by the first BBPD circuit 11 is s1, and the corresponding weighting value is a1; the sampling data output by the second BBPD circuit 11 is s2, and the corresponding weighting value is a2; the sample data output from the third BBPD circuit 11 is s3, and the corresponding weighting value is a3. The adder 12 calculates the value as: s1+s2+a2+s3 a3.
In a specific implementation, the weighting values corresponding to the different BBPD circuits 11 may be preset. The weighting values corresponding to the different BBPD circuits 11 may be equal or may be completely unequal. In the embodiment of the invention, the weighted value corresponding to the BBPD circuit 11 with no time delay of the edge signal is set to be the largest, the weighted values corresponding to the BBPD circuits 11 with time delay of other N-1 edge signals are smaller than the weighted values corresponding to the BBPD circuits 11 without time delay, and the weighted values are inversely related to the time delay of the edge signal.
For example, the edge input end of the first BBPD circuit 11 inputs an edge signal without delay, the edge input end of the second BBPD circuit 11 inputs an edge signal with delay of a first duration, the edge input end of the third BBPD circuit 11 inputs an edge signal with delay of a second duration, the first duration is smaller than the second duration, the weighting value corresponding to the first BBPD circuit 11 is set to be the largest, the weighting value corresponding to the second BBPD circuit 11 is the second, and the weighting value corresponding to the third BBPD circuit 11 is the smallest.
In a specific implementation, the delays corresponding to the edge signals of the N-1 BBPD circuits 11 may also be set to be positively correlated with the weighting values. It will be appreciated that the delay and the weighting value corresponding to the edge signals of the N-1 BBPD circuits 11 may also be set to be uncorrelated.
For example, the weighting values corresponding to the three BBPD circuits 11 are equal. For another example, the weighting value corresponding to the first BBPD circuit 11 is set to be the smallest, the weighting value corresponding to the second BBPD circuit 11 is set to be the largest, the weighting value corresponding to the third BBPD circuit 11 is set to be between the two weighting values, and so on.
In a specific implementation, the adder 12 may store weighting values corresponding to the N BBPD circuits 11. The N BBPD circuits 11 output the corresponding sample data to the adders 12, respectively. After receiving the sampling data corresponding to the N BBPD circuits 11, the adder 12 calculates products corresponding to each BBPD circuit 11 according to the weighted values corresponding to one, and then adds the N products to obtain corresponding sum values.
In a specific implementation, the adder 12 may not store the weighting values corresponding to the N BBPD circuits 11. In the embodiment of the present invention, the adder 12 may be coupled to a preset controller, and the weighted values corresponding to the N BBPD circuits 11 may be output to the adder 12 through the preset controller.
In a specific implementation, multipliers corresponding to BBPDs one by one may be provided between the N BBPD circuits 11 and the adder 12, and after the sampling data output by the N BBPD circuits 11 passes through the corresponding multipliers, corresponding products are obtained and input to the adder 12, and the adder 12 performs addition operation on the N products.
For example, a first multiplier is provided between the first BBPD circuit 11 and the adder 12, a second multiplier is provided between the second BBPD circuit 11 and the adder 12, a third multiplier is provided between the third BBPD circuit 11 and the adder 12, the first multiplier multiplies the sample data output from the first BBPD circuit 11 by a weight value corresponding to the first BBPD circuit 11, the second multiplier multiplies the sample data output from the second BBPD circuit 11 by a weight value corresponding to the second BBPD circuit 11, and the third multiplier multiplies the sample data output from the third BBPD circuit 11 by a weight value corresponding to the third BBPD circuit 11.
It can be understood that in practical application, other implementation manners may also exist to implement multiplication operation of the sampled data output by the BBPD circuit and the corresponding weighting value, which is not described in detail in the embodiment of the present invention.
It should be noted that in fig. 1, only the phase selector 14 is shown coupled to the phase input of one of the BBPD circuits 11 for simplicity. In particular implementations, the phase selector 14 may be coupled to the phase inputs of the N BBPD circuits 11.
In a specific implementation, the core of the clock logic recovery circuit 13 may be a multi-bit second-order integrator, and the clock logic recovery circuit 13 may perform weighted integration on the output signal of the adder 12, thereby obtaining a stable error average value, and output the obtained error average value to the phase selector 14. The phase selector 14 may convert the received error mean value into a phase difference and output to the N BBPD circuits.
The specific working principle and structure of the clock logic recovery circuit and the working principle and structure of the phase selector can refer to the prior art, and the embodiments of the present invention are not described in detail.
Referring to fig. 2, a schematic diagram of a prior art clock recovery circuit is shown. Compared with the prior art, the clock recovery circuit provided by the embodiment of the invention increases the number of BBPD circuits and correspondingly increases the adders. The specific structure and working principle of the clock recovery logic circuit and the phase selector in the embodiment of the invention can be the same as those in the prior art.
In the embodiment of the invention, the number of BBPD circuits in the clock recovery circuit is adjustable, and the clock recovery circuit can comprise M BBPD circuits, wherein M is larger than or equal to N. The N BBPD circuits described in the embodiment of the present invention may be N selected from the M BBPD circuits by a preset controller.
When the number of BBPD circuits in the clock recovery circuit is 1 and the BBPD circuits input edge signals without delay, the clock recovery circuit in the embodiment of the present invention is substantially the same as the classical clock recovery circuit provided in the prior art. Therefore, the clock recovery circuit provided by the embodiment of the invention can be correspondingly improved on the basis of the existing classical clock recovery circuit, and is convenient for engineering realization.
In the embodiment of the invention, N is more than or equal to 2. The larger the value of N is, the more accurate the clock offset of the edge signal obtained finally relative to the data signal is, and correspondingly, more BBPD circuits are required to be arranged and the corresponding calculated amount is increased; on the contrary, when the value of N is smaller, the accuracy of the clock offset of the edge signal obtained finally relative to the clock signal is poorer, but fewer BBPD circuits need to be arranged, and the calculated amount is smaller.
Therefore, in practical application, the value of N can be determined by comprehensively considering the accuracy of the clock offset and the balance between the occupied area and the calculated amount of the BBPD circuit. In one embodiment of the present invention, n=3.
In summary, in the embodiment of the invention, by setting N BBPD circuits, the gain of the BBPD circuits can be linearized, so that the influence degree of the gain of the BBPD circuits on the quality of input signals and the quality of clocks is reduced, and the bandwidth of the clock recovery circuit is further improved.
The embodiment of the invention also provides electronic communication equipment which can comprise the clock recovery circuit provided by any embodiment.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (8)
1. A clock recovery circuit, comprising: n BBPD circuits, an adder, clock recovery logic, and a phase selector, wherein:
each BBPD circuit comprises a data input end and an edge input end, and edge input ends of N-1 BBPD circuits input edge signals with unequal time delays; n is more than or equal to 2; the input end of the adder is coupled with the output ends of the N BBPD circuits, and the output end of the adder is coupled with the input end of the clock recovery logic circuit;
the output end of the clock recovery logic circuit is coupled with the input end of the phase selector;
the output ends of the phase selectors are respectively coupled with the phase input ends of the N BBPD circuits.
2. The clock recovery circuit of claim 1, wherein the time delays corresponding to the edge signals of the N-1 BBPD circuits are determined by the duration of the edge signals.
3. The clock recovery circuit of claim 1, wherein the N BBPD circuits have one-to-one weighting values; the adder is suitable for adding products of the sampling data output by the N BBPD circuits and the corresponding weighted values.
4. The clock recovery circuit of claim 3, wherein the weighted value corresponding to the N BBPD circuits has a largest weighted value corresponding to a BBPD circuit having no delay in the edge signal, and the delay corresponding to the edge signal of the N-1 BBPD circuits is inversely related to the weighted value.
5. The clock recovery circuit of claim 3, wherein the adder has stored therein weighting values for the N BBPD circuits.
6. The clock recovery circuit of claim 3, wherein the adder is further coupled to a predetermined controller and adapted to receive the weighted values output by the controller in one-to-one correspondence with the N BBPD circuits.
7. The clock recovery circuit of claim 1, wherein the N BBPD circuits are selected from M PPBD circuits by a preset controller; m is more than or equal to N.
8. An electronic communication device comprising a clock recovery circuit as claimed in any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010307959.5A CN111490779B (en) | 2020-04-17 | 2020-04-17 | Clock recovery circuit and electronic communication device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010307959.5A CN111490779B (en) | 2020-04-17 | 2020-04-17 | Clock recovery circuit and electronic communication device |
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| CN111490779A CN111490779A (en) | 2020-08-04 |
| CN111490779B true CN111490779B (en) | 2023-06-23 |
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| JP4196657B2 (en) * | 2002-11-29 | 2008-12-17 | 株式会社日立製作所 | Data recovery method and digitally controlled clock data recovery circuit |
| US8634510B2 (en) * | 2011-01-12 | 2014-01-21 | Qualcomm Incorporated | Full digital bang bang frequency detector with no data pattern dependency |
| US8860467B2 (en) * | 2013-03-15 | 2014-10-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Biased bang-bang phase detector for clock and data recovery |
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