CN111490690B - Dual output active rectifier structure and wireless charging circuit - Google Patents

Dual output active rectifier structure and wireless charging circuit Download PDF

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CN111490690B
CN111490690B CN202010387461.4A CN202010387461A CN111490690B CN 111490690 B CN111490690 B CN 111490690B CN 202010387461 A CN202010387461 A CN 202010387461A CN 111490690 B CN111490690 B CN 111490690B
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output
mos tube
input end
active rectifier
rectifier structure
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CN111490690A (en
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林杰
詹陈长
路延
马许愿
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University of Macau
Southwest University of Science and Technology
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University of Macau
Southwest University of Science and Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses a double-output active rectifier structure and a wireless charging circuit. The double-output active rectifier structure comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a power tube control driving circuit; the double-output active rectifier structure further comprises an alternating current input end, a first output end and a second output end; the first MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the first output end, and the second MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the ground; the third MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the second output end, and the fourth MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the ground; the first MOS tube and the third MOS tube are P-type tubes, and the second MOS tube and the fourth MOS tube are N-type tubes. The two-way output active rectifier structure of the embodiment has the function of two-way output.

Description

Dual output active rectifier structure and wireless charging circuit
Technical Field
The embodiment of the invention relates to the technical field of electronics, in particular to a two-way output active rectifier structure with two-way output and a wireless charging circuit.
Background
The dual-output active rectifier structure has wide application in modern electronic technology, and particularly with the popularization of wireless charging technology in recent years, the function of the dual-output active rectifier structure is more and more important.
The two-way output active rectifier structure is responsible for converting AC power to DC power, which is then converted to one or two different voltage outputs by a DC-DC power converter. However, the existing two-way output active rectifier structure needs to be connected with a DC-DC power converter to convert one-way signals into two-way outputs, and more energy loss can be generated in the conversion process, so that the application range of the two-way output active rectifier structure is narrower.
Disclosure of Invention
The invention provides a double-output active rectifier structure and a wireless charging circuit, so as to realize two-way output of the double-output active rectifier structure.
In a first aspect, an embodiment of the present invention provides a dual-output active rectifier structure with two outputs, including a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a power transistor control driving circuit; the double-output active rectifier structure further comprises an alternating current input end, a first output end and a second output end; the first MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the first output end, and the second MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the ground; the third MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the second output end, and the fourth MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the ground; the first MOS tube and the third MOS tube are P-type tubes, and the second MOS tube and the fourth MOS tube are N-type tubes; the power tube control driving circuit is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube and is used for controlling the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube to be conducted or cut off.
Optionally, the source electrode and the substrate of the first MOS tube are connected to the first output end of the dual-output active rectifier structure, and the drain electrode of the first MOS tube is connected to the first end of the ac input end; the source electrode and the substrate of the second MOS tube are grounded, and the drain electrode of the second MOS tube is connected with the first end of the alternating current input end; the source electrode and the substrate of the third MOS tube are connected with the second output end of the double-output active rectifier structure, and the drain electrode of the third MOS tube is connected with the second end of the alternating current input end; the source electrode and the substrate of the fourth MOS tube are grounded, and the drain electrode of the fourth MOS tube is connected with the second end of the alternating current input end.
Optionally, the device further comprises a fifth MOS tube and a sixth MOS tube; the fifth MOS tube is connected with the second MOS tube in parallel, and the sixth MOS tube is connected with the fourth MOS tube in parallel.
Optionally, the power tube control drive circuit includes a clock generator, a first mode controller, a second mode controller, and drive logic and a power stage size adjuster; the input end of the clock generator is connected with the alternating current input end of the two-way output active rectifier structure, and the first mode controller is connected with the first output end of the clock generator and the first output end of the two-way output active rectifier structure; the second mode controller is connected with a second output end of the clock generator and a second output end of the two-way output active rectifier structure; the driving logic and the power level size regulator are connected with the first mode controller and the second mode controller, and the output ends of the driving logic and the power level size regulator are respectively connected with the grid electrodes of the MOS tubes; the driving logic and the power level size regulator are used for controlling the on/off of each MOS tube according to different modulation mode signals output by the first mode controller and the second mode controller.
Optionally, the first mode controller includes a first voltage divider circuit, at least two first comparators, at least two first D flip-flops, two second D flip-flops, at least two first nand gates, and a second nand gate; the input end of the first voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the first voltage dividing circuit divides the voltage of the input end and outputs the divided voltage from at least two output ends, the first input ends of at least two first comparators are correspondingly connected with at least two output ends of the first voltage dividing circuit, and the second input end of the first comparator inputs reference voltage; the data input end of each first D trigger is connected with the output end of each first comparator in a one-to-one correspondence manner, and the clock signal input end of each first D trigger is connected with the first output end of the clock generator; the two second D flip-flops are cascaded, the clock signal input end of the first second D flip-flop is connected with the first output end of the clock generator, the signal phases output by the two second D flip-flops are output to the first input end of one first NAND gate after being processed, and the signals output by the two second D flip-flops are respectively output to the first input ends of the other two first NAND gates; the second input ends of the first NAND gates are respectively connected with the output ends of the first D flip-flops in a one-to-one correspondence manner; the input end of the second NAND gate is respectively connected with the output end of each first NAND gate, wherein the output end of one first D trigger and the output end of the second NAND gate output modulation mode signals.
Optionally, the second mode controller includes a second voltage divider circuit, at least two second comparators, at least two third D flip-flops, two fourth D flip-flops, at least two third nand gates, and a fourth nand gate; the input end of the second voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the second voltage dividing circuit divides the voltage of the input end and outputs the divided voltage from at least two output ends, the first input ends of at least two second comparators are correspondingly connected with at least two output ends of the second voltage dividing circuit, and the second input end of the second comparator inputs reference voltage; the data input end of each third D trigger is connected with the output end of each second comparator in a one-to-one correspondence manner, and the clock signal input end of each third D trigger is connected with the second output end of the clock generator; the clock signal input end of the first D trigger is connected with the second output end of the clock generator, the signal phases output by the two fourth D triggers are output to the first input end of one third NAND gate after being processed, and the signals output by the two fourth D triggers are respectively output to the first input ends of the other two third NAND gates; the second input ends of the third NAND gates are respectively connected with the output ends of the third D flip-flops in a one-to-one correspondence manner; the input end of the fourth NAND gate is respectively connected with the output end of each third NAND gate, wherein the output end of one third D trigger and the output end of the fourth NAND gate output modulation mode signals.
Optionally, the clock generator includes a third comparator, a fourth comparator, a first falling edge detector, a second falling edge detector, an SR latch, and a first inverter; the first input ends of the third comparator and the fourth comparator are respectively connected with two ends of the alternating current input end of the two-way output active rectifier structure; the input end of the first falling edge detector is connected with the output end of the third comparator, the output end of the first falling edge detector is connected with the first input end of the SR latch, the input end of the second falling edge detector is connected with the output end of the fourth comparator, and the output end of the second falling edge detector is connected with the second input end of the SR latch; the time input end of the first inverter is connected with the output end of the SR latch, and the output end of the SR latch and the output end of the first inverter output clock signals.
Optionally, the drive logic and power stage sizer includes a third voltage divider circuit, a fifth comparator, and a first dead time control circuit; the input end of the third voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the output end of the third voltage dividing circuit is connected with the first input end of the fifth comparator, and the second input end of the fifth comparator inputs a reference voltage; the first dead time control circuit receives a signal output by the output end of the fifth comparator and a modulation mode signal of a first mode controller, and is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the drive logic and power stage sizer further includes a fourth voltage divider circuit, a sixth comparator, and a second dead time control circuit; the input end of the fourth voltage dividing circuit is connected with the second output end of the two-way output active rectifier structure, the output end of the fourth voltage dividing circuit is connected with the first input end of the sixth comparator, and the second input end of the sixth comparator inputs a reference voltage; the second dead time control circuit receives the signal output by the output end of the sixth comparator and the modulation mode signal of the second mode controller, and the second dead time control circuit is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
Optionally, the device further comprises a voltage boosting circuit, wherein the voltage boosting circuit is connected between the grid electrode of the first MOS tube and the driving logic and power level size regulator, and is used for boosting the voltage input into the first MOS tube.
In a second aspect, an embodiment of the present invention further provides a wireless charging circuit, including a charging receiving coil and the dual-output active rectifier structure in the first aspect; and the input end of the two-way output active rectifier structure is connected with the charging receiving coil.
According to the technical scheme of the embodiment, the adopted double-output active rectifier structure comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a power tube control driving circuit; the double-output active rectifier structure further comprises an alternating current input end, a first output end and a second output end; the first MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the first output end, and the second MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the ground; the third MOS tube is connected with the second end of the alternating current input end of the double-output active rectifier structure and the second output end V OUT2 The fourth MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the ground; the first MOS tube and the third MOS tube are P-type tubes, and the second MOS tube and the fourth MOS tube are N-type tubes; the power tube control driving circuit is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube and used for controlling the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube to be turned on or turned off. The power tube controls the driving circuit to output the current input by the alternating current input end through the two output ends in turn, thereby completing the two-way output function of the two-way output active rectifier structure and expanding the application range of the two-way output active rectifier structure.
Drawings
Fig. 1 is a schematic circuit diagram of a dual-output active rectifier structure according to an embodiment of the present invention;
fig. 2 is a timing diagram of a dual-output active rectifier structure according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of another two-way output active rectifier structure according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a first mode controller according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a first mode controller according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a second mode controller according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a clock generator according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a clock generator according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a circuit configuration of a driving logic and power stage size regulator according to an embodiment of the present invention;
fig. 10 is a schematic circuit diagram of a wireless charging circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic circuit structure diagram of a dual-output active rectifier structure according to an embodiment of the present invention, and referring to fig. 1, the dual-output active rectifier structure includes: first MOS tube M P1 Second MOS tube M N1 Third MOS tube M P2 Fourth MOS tube M N2 And a power tube control drive circuit 101; the double-output active rectifier structure also comprises an alternating current input end and a first output endTerminal V OUT1 And a second output terminal V OUT2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the first MOS tube M P1 A first end V connected to the AC input end of the dual-output active rectifier structure ac1 And a first output terminal V OUT1 Between the second MOS tube M N1 A first end V connected to the AC input end of the dual-output active rectifier structure ac1 And ground; third MOS tube M P2 A second terminal V connected to the AC input terminal of the dual output active rectifier structure ac2 And a second output terminal V OUT2 Between, the fourth MOS tube M N2 A second terminal V connected to the AC input terminal of the dual output active rectifier structure ac2 And ground; first MOS tube M P1 And a third MOS tube M P2 Is a P-type tube, a second MOS tube M N1 And a fourth MOS tube M N2 Is an N-type pipe; the power tube control driving circuit 101 is respectively connected with the first MOS tube M P1 Gate electrode of (2), second MOS transistor M N1 Gate electrode of (d), third MOS transistor M P2 Gate electrode of (d) and fourth MOS transistor M N2 Gate connection for controlling the first MOS transistor M P1 Second MOS tube M N1 Third MOS tube M P2 And a fourth MOS tube M N2 On or off.
Specifically, fig. 2 is a timing chart of a dual-output active rectifier structure according to an embodiment of the present invention, which may correspond to the dual-output active rectifier structure in fig. 1, and with reference to fig. 1 and 2, an ac input terminal inputs an ac current I in a sinusoidal form ac First voltage signal V 1 For loading on the first MOS tube M P1 And a second MOS tube M N1 Voltage signal on, first output current I RX1 Representing the current flowing through the first load resistor R1, the second voltage signal V 2 For loading on the third MOS tube M P2 And a fourth MOS tube M N2 Voltage signal on, second output current I RX2 Representing the current flowing through the second load resistor R2; in the first half-wave period t1, the power tube control driving circuit 101 controls the first voltage signal V1 to be low level, the second voltage signal V2 to be high level, the first MOS tube MP1 is turned on, and the fourth MOS tube M N2 Conduction, second MOS tube M N1 And a third MOS tube M P2 Turn off, first end V of AC input end ac1 The input current passes through the first MOS tube M P1 A first load resistor R1 and a fourth MOS tube M N2 Second end V flowing back to the AC input end ac2 Thereby forming a current loop, i.e. a first output V during a first half-wave period t1 OUT1 Current I at RX1 Input current I with AC input terminal ac Keeping consistency; in the second half-wave period t2, the power tube control driving circuit controls the first voltage signal V1 to be high level and the second voltage signal V2 to be low level, and the first MOS tube M is used for driving the first MOS tube M P1 Turn-off, fourth MOS transistor M N2 Turn off, the second MOS tube M N1 And a third MOS tube M P2 Conducting, at this time, the current flows to the second end V of the AC input end ac2 Fourth MOS tube M N2 Through a second load resistor R2 and a first MOS tube M P1 Back to the first end V of the AC input ac1 Thereby forming a current loop, and thus, the second output terminal V OUT2 Current to ground I RX2 And at the moment the alternating current input end inputs current I ac Inverting; in the third half-wave period t3, the states of all MOS tubes are kept consistent with the states of all MOS tubes in the first half-wave period t 1; in the fourth half-wave period t4, the states of the MOS transistors are kept consistent with the states of the MOS transistors in the second half-wave period t 2; i.e. to obtain the waveforms of FIG. 2, i.e. to form two outputs, by applying a voltage to the first output terminal V OUT1 A second output terminal V OUT2 The output current signal is converted into a voltage signal through a load, and the voltage signal in a half sine form can be converted into a stable direct current signal through a chopping mode and the like, so that the two-way output active rectifier structure achieves the functions of two-way output and voltage stabilization. It should be noted that, in the present embodiment, the first load resistor R1 and the second load resistor R2 may be replaced by capacitors. First MOS tube M P1 And a second MOS tube M N1 Can be a high-voltage MOS tube, a third MOS tube M P2 And a fourth MOS tube M N2 The active rectifier structure can be a low-voltage MOS tube, so that the two-way output active rectifier structure can support two output voltages, namely high voltage and low voltage.
According to the technical scheme of the embodiment, the adopted double-output active rectifier structure comprises a first MOS tube, a second MOS tube and a third MOS tubeThe MOS tube, the fourth MOS tube and the power tube control driving circuit; the double-output active rectifier structure further comprises an alternating current input end, a first output end and a second output end; the first MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the first output end, and the second MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the ground; the third MOS tube is connected with the second end of the alternating current input end of the double-output active rectifier structure and the second output end V OUT2 The fourth MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the ground; the first MOS tube and the third MOS tube are P-type tubes, and the second MOS tube and the fourth MOS tube are N-type tubes; the power tube control driving circuit is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube and used for controlling the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube to be turned on or turned off. The power tube controls the driving circuit to output the current input by the alternating current input end through the two output ends in turn, thereby completing the two-way output function of the two-way output active rectifier structure and expanding the application range of the two-way output active rectifier structure.
Optionally, with continued reference to fig. 1, a first MOS transistor M P1 Is connected with the source electrode and the substrate of the double-output active rectifier structure OUT1 First MOS tube M P1 A drain electrode connected to the first end V of the AC input terminal ac1 The method comprises the steps of carrying out a first treatment on the surface of the Second MOS tube M N1 The source electrode and the substrate of the MOS transistor are grounded, the second MOS transistor M N1 A drain electrode connected to the first end V of the AC input terminal ac1 The method comprises the steps of carrying out a first treatment on the surface of the Third MOS tube M P2 Is connected with the second output end V of the double-output active rectifier structure through the source electrode and the substrate OUT2 Third MOS tube M P2 A second terminal V connected to the AC input terminal ac2 The method comprises the steps of carrying out a first treatment on the surface of the Fourth MOS tube M N2 The source electrode and the substrate of the transistor are grounded, and a fourth MOS transistor M N2 A second terminal V connected to the AC input terminal ac2 。
By means of the arrangement, the corresponding MOS tube can be guaranteed to be opened or closed under the control of the power tube control driving circuit 101, and then the current input by the alternating current input end is guaranteed to be output through the two output ends in turn, so that the two-way output function of the two-way output active rectifier structure is achieved.
Optionally, fig. 3 is a schematic circuit structure diagram of another dual-output active rectifier structure according to an embodiment of the present invention, and referring to fig. 3, the circuit structure diagram further includes a fifth MOS transistor and a sixth MOS transistor, where the fifth MOS transistor and the second MOS transistor M N1 Parallel connection, a sixth MOS tube and a fourth MOS tube M N2 And are connected in parallel.
Specifically, as shown in fig. 3, the second MOS transistor M N1 And the fifth MOS tube can be connected in parallel to form a first power structure 102, and the second MOS tube M N2 And the sixth MOS tube can be connected in parallel to form a second power structure 103, and the fifth MOS tube and the second MOS tube M N1 The gates of the (a) and (b) may be connected to the power tube control driving circuit 101 via a bus, for example, the power tube control driving circuit 101 may output a 2-bit control signal V to the first power structure 102 GN1 [1:2]Outputs a 2-bit control signal V to the second power structure 103 GN2 [1:2]The control signal can respectively control the on/off of each MOS tube in the two power structures, for example, when the load of the corresponding output end of the two-way output active rectifier structure is smaller, the two MOS tubes in the corresponding power structure can be conducted, so that the power conversion efficiency of the two-way output active rectifier structure system is optimized, and the performance of the two-way output active rectifier structure is improved. It should be noted that in other embodiments, more MOS transistors may be connected in parallel in the two power structures, and the number of MOS transistors in the two power structures may be different.
Optionally, with continued reference to fig. 3, the power tube control drive circuit includes a clock generator 201, a first mode controller 202, a second mode controller 203, and drive logic and power stage sizer 204; the input end of the clock generator 201 is connected with the alternating current input end of the double-output active rectifier structure, and the first mode controller 202 is connected with the first output end CLK of the clock generator 201 and the first output end V of the double-output active rectifier structure OUT1 A second mode controller 203 connected to the second output terminal of the clock generator
Figure BDA0002484323140000111
And a second output terminal V of the dual-output active rectifier structure OUT2 Connecting; the driving logic and power level size regulator 204 is connected with the first mode controller 202 and the second mode controller 203, and each output end of the driving logic and power level size regulator is connected with the grid electrode of each MOS tube respectively; the driving logic and power level size adjuster 204 is configured to output different modulation mode signals according to the first mode controller 202 and the second mode controller 203, and control the on/off of each MOS transistor.
In particular, when the load changes, e.g. the first load capacitance C O1 Or a second load capacitance C O2 When one or two capacitors of the two-way output active rectifier structure change, the output voltages of the two output ends change, and the two output voltages are fed back to the first mode controller 202 or the second mode controller 203, the mode controllers generate mode modulation signals according to the feedback signals, and the driving logic and the power stage size regulator generate corresponding power grid control signals (such as V GN1 ，V GN2 、V GP1 And V GP2 ) And transferred to each MOS tube. The drive logic and power stage sizing agent 204 may adjust the size of the first power structure 102 and the second power structure 103 according to the sizing modulation signals ms_l and ms_h generated by the mode controller to optimize the power conversion efficiency of the two-way output active rectifier structure at low loads. It should be noted that the first mode controller 202 and the second mode controller 203 may access the first reference signal V respectively REF_H And a second reference signal V REF_L 。
Optionally, fig. 4 is a schematic circuit diagram of a first mode controller according to an embodiment of the present invention, and referring to fig. 4, the first mode controller includes: a first voltage divider circuit 2021, at least two first comparators 2022, at least two first D flip-flops 2023, two second D flip-flops 2024, at least two first nand gates 2025, and a second nand gate 2026; the input end of the first voltage dividing circuit 2021 is connected to the first output end V of the two-way output active rectifier structure OUT1 The first voltage dividing circuit 2021 divides the voltage at the input end and outputs the divided voltage from at least two output ends, the first input ends of the at least two first comparators 2022 are correspondingly connected with the at least two output ends of the first voltage dividing circuit 2021, and the second input end of the first comparators 2022 inputs the reference voltage V REF_H The method comprises the steps of carrying out a first treatment on the surface of the The data input end of each first D flip-flop is connected with the output end of each first comparator 2022 in a one-to-one correspondence manner, and the clock signal input end of the first D flip-flop 2023 is connected with the first output end CLK of the clock generator; the two second D flip-flops are cascaded, the clock signal input end of the first second D flip-flop 2024 is connected with the first output end CLK of the clock generator, the signal phase and the signal phase output by the two second D flip-flops 2024 are output to the first input end of a first nand gate 2025, and the signals output by the two second D flip-flops 2024 are respectively output to the first input ends of the other two first nand gates 2025; the second input end of each first NAND gate 2025 is respectively connected with the output end of each first D flip-flop 2023 in a one-to-one correspondence manner; the input end of the second nand gate 2026 is connected to the output end of each first nand gate 2025, respectively, wherein the output end of a first D flip-flop 2023 and the output end of the second nand gate 2026 output the modulation mode signal.
Specifically, fig. 5 is a timing diagram of a first mode controller according to an embodiment of the present invention, which may correspond to the mode controller shown in fig. 4, and in conjunction with fig. 4 and fig. 5, in fig. 4, three first nand gates 2025 and one nor gate may be included and connected to form the structure shown in fig. 4; the first voltage divider circuit 2021 may be a plurality of resistors connected in series for outputting the first output V of the two-way output active rectifier structure OUT1 The output voltage is divided, the first input terminal of the first comparator 2022 may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal; the second D trigger is in a frequency divider connection mode, and when the first output end V of the double-output active rectifier structure OUT1 When the output voltage is high, the output voltage of each divided output end of the first voltage dividing circuit 2021 is high, and at this time, the output end of each first comparator 2022 outputs a high level; when the first output end V OUT1 When the output voltage gradually decreases, the output voltage of the first voltage dividing circuit decreases, however, the graphThe uppermost first comparator 2022 in 4 has its output still high due to the larger divided voltage, while the bottommost first comparator has its output changed to low due to the smaller divided voltage; thus, when the first mode controller comprises four first comparators 2022, five modes can be generated altogether, i.e. during one period T, according to the two-way output of the first output V of the active rectifier structure OUT1 The first mode controller generates five different modulation mode signals ms_h according to different output voltages, so that the driving logic and the power stage size regulator output different control signals, such as adjusting the duty ratio of the control signals of the MOS transistor, and further controlling the output power of the output end of the two-way output active rectifier structure.
Optionally, fig. 6 is a schematic circuit diagram of a second mode controller according to an embodiment of the present invention, and referring to fig. 6, the first mode controller includes: a second voltage divider circuit 2031, at least two second comparators 2032, at least two third D flip-flops 2033, two fourth D flip-flops 2034, at least two third nand gates 2035, and a fourth nand gate 2036; an input end of the second voltage dividing circuit 2031 is connected with a second output end V of the dual-output active rectifier structure OUT2 The second voltage dividing circuit 2031 divides the voltage of the input terminal and outputs the divided voltage from at least two output terminals, the first input terminal of the at least two second comparators 2032 is correspondingly connected to the at least two output terminals of the second voltage dividing circuit 2031, and the second input terminal of the second comparators 2032 inputs the reference voltage V REF_L The method comprises the steps of carrying out a first treatment on the surface of the The data input end of each third D trigger is connected with the output end of each second comparator 2032 in a one-to-one correspondence manner, and the clock signal input end of the third D trigger 2033 is connected with the second output end of the clock generator
Figure BDA0002484323140000131
Two fourth D flip-flops 2034 are cascaded, the clock signal input of the first second D flip-flop 2034 being connected to the second output of the clock generator
Figure BDA0002484323140000132
The signal phase output by the two fourth D flip-flops 2034 is then output to a first output of a third NAND gate 2035The input end, the signals output by the two fourth D flip-flops 2034 are respectively output to the first input ends of the other two third nand gates 2035; the second input ends of the third nand gates 2035 are respectively connected with the output ends of the third D flip-flops 2033 in a one-to-one correspondence; the input end of the fourth nand gate 2036 is connected to the output end of each third nand gate 2035, respectively, and the output end of one third D flip-flop 2033 and the output end of the fourth nand gate 2036 output the modulation mode signal.
Specifically, the timing diagram of fig. 5 may also correspond to the second mode controller shown in fig. 6, and in fig. 6, may include three third nand gates 2035 and one nor gate connected in the structure shown in fig. 6; referring to fig. 5 and 6, the second voltage dividing circuit 2031 may be a plurality of resistors connected in series for outputting the second output V of the two-way output active rectifier structure OUT2 The output voltage is divided, the first input terminal of the second comparator 2032 may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal; the fourth D trigger is a frequency divider connection mode, and when the second output end V of the double-output active rectifier structure OUT2 When the output voltage is higher, the output voltage of each divided output terminal of the voltage dividing circuit 2031 is higher, and at this time, the output terminal of each second comparator 2032 outputs a high level; when the second output end V OUT2 When the output voltage gradually decreases, the output voltage of the output terminal of the voltage dividing circuit decreases, however, the output of the uppermost second comparator 2032 in fig. 6 is still at a high level due to the larger voltage division, and the output of the bottommost second comparator becomes at a low level due to the smaller voltage division; thus, when the second mode controller comprises four second comparators 2032, five modes can be generated altogether, i.e. during one period T, according to the two-way output of the first output V of the active rectifier structure OUT2 The second mode controller generates five different modulation mode signals (ms_l) according to the output voltages, so that the driving logic and the power stage size regulator output different control signals, such as adjusting the duty ratio of the MOS transistor control signals, and further controlling the output power of the output end of the two-way output active rectifier structure.
Optionally, fig. 7 is a circuit structure of a clock generator according to an embodiment of the present inventionSchematic diagram, referring to FIG. 7, the clock generator includes a third comparator CMP 1 Fourth comparator CM P2 A first falling edge detector 301, a second falling edge detector 302, an SR latch 303, and a first inverter 304; third comparator CMP 1 And fourth comparator CM P2 A first input terminal of the third comparator CMP connected to the reference voltage 1 And a fourth comparator CM P2 The second input ends of the two-way output active rectifier structure are respectively connected with two ends of the alternating current input end of the two-way output active rectifier structure; the input of the first falling edge detector 301 and the third comparator CMP 1 Output terminal C of (2) N1 An output of the first falling edge detector 301 is connected to a first input of the SR latch 303; the input of the second falling edge detector 302 is connected to a fourth comparator CM P2 Output terminal C of (2) N2 The output end of the second falling edge detector 302 is electrically connected with the second input end of the SR latch; the input of the first inverter 304 is connected to the output of the SR latch, and the output of the SR latch 301 and the output of the first inverter 304 output a clock signal.
Specifically, fig. 8 is a timing chart of a clock generator according to an embodiment of the present invention, which may correspond to the clock generator of fig. 7, and with reference to fig. 7 and 8, the third comparator CMP 1 The first input of (a) may be a normal phase input and the second input may be an inverted phase input; fourth comparator CM P2 The first input of (a) may be a normal phase input and the second input may be an inverted phase input; the reference signal is regarded as a ground signal, and the third comparator CMP 1 And fourth comparator CM P2 Respectively comparing the first AC input terminals V ac1 A second AC input terminal V for receiving signals of the signal and ground signals ac2 The magnitude of the signal and the ground signal of (a) is as the first AC input terminal V ac1 And a second ac input V ac2 When the signals of the (a) are respectively smaller than the grounding signal, the third comparator and the fourth comparator respectively output high level, the falling edge detector detects the falling edge of the corresponding comparator output signal and transmits the falling edge to the SR latch and the inverter, so that the first clock signal output end CLK and the second clock signal output end CLK of the clock signal generator are enabled to outputEnd of the device
Figure BDA0002484323140000151
And respectively outputting corresponding clock signals. It should be noted that, as shown IN fig. 7, the input terminal IN of the falling edge detector is connected to the output terminal of the corresponding comparator, the output terminal OUT is connected to the input terminal of the SR latch, and the falling edge detector may include three inverters and a nor gate, which are connected to form the structure shown IN fig. 7.
Optionally, fig. 9 is a schematic circuit diagram of a driving logic and a power stage size adjuster according to an embodiment of the present invention, and referring to fig. 9, the driving logic and the power stage size adjuster include a third voltage dividing circuit 401, a fifth comparator 402, and a first dead time control circuit 403; the input end of the third voltage dividing circuit 401 is connected with the first output end of the two-way output active rectifier structure, the output end of the third voltage dividing circuit 401 is connected with the first input end of the fifth comparator 402, and the second input end of the fifth comparator 402 inputs the reference voltage; the first dead time control circuit 403 receives the signal output by the output end of the fifth comparator 402 and the modulation mode signal of the first mode controller, and the first dead time control circuit 403 is connected with the gate of the first MOS transistor and the gate of the second MOS transistor;
The drive logic and power stage sizer also includes a fourth voltage divider circuit 501, a sixth comparator 502, and a second dead time control circuit 503; the input end of the fourth voltage dividing circuit 501 is connected with the second output end of the two-way output active rectifier structure, the output end of the fourth voltage dividing circuit 501 is connected with the first input end of the sixth comparator 502, and the second input end of the sixth comparator 502 inputs the reference voltage; the second dead time control circuit 503 receives the signal output by the output end of the sixth comparator 502 and the modulation mode signal of the second mode controller, and the second dead time control circuit 503 connects the gate of the third MOS transistor and the gate of the fourth MOS transistor.
Specifically, the third voltage dividing circuit 401 and the fifth comparator 402 form a start-up circuit, when the output signal EN of the start-up circuit is at a low level, the driving logic will keep the MOS transistor gate control signal VGP1 at a high level, VG N1 The level of the voltage is kept low and,the MOS transistor is conducted by using a body diode. When EN is in high level, the grid control signal of the power tube is modulated by the first mode controller, and the double-output active rectifier structure works normally. The first dead time control circuit 403 is used for preventing the P-type power tube and the N-type power tube from being conducted simultaneously to cause loss; and may also drive logic and power stage sizing devices to perform sizing of the first power structure based on the sizing signal MS _ H.
The fourth voltage divider 501 and the sixth comparator 502 form a start-up circuit, when the output signal EN of the start-up circuit is low, the driving logic will make the MOS transistor gate control signal VG P2 Hold high level, VG N2 And keeping a low level, and conducting the MOS tube by using the body diode. When EN is in high level, the grid control signal of the power tube is modulated by the second mode controller, and the double-output active rectifier structure works normally. The second dead time control circuit 503 is used for preventing the P-type and N-type power transistors from being conducted simultaneously to cause loss; and may also drive logic and power stage sizing devices to perform sizing of the first power structure based on the sizing signal ms_l.
Optionally, with continued reference to fig. 3, the dual-output active rectifier structure further includes a boost circuit 601, where the boost circuit 601 is connected between the gate of the first MOS transistor and the driving logic and the power stage size regulator, to boost the voltage input to the first MOS transistor.
Specifically, the voltage of the first MOS tube can be boosted by the voltage boosting circuit, so that the grid voltage of the first MOS tube meets the voltage required by normal operation, the first MOS tube is enabled to work normally, the first MOS tube is prevented from being damaged, and the stability of the double-output active rectifier structure is improved.
In fig. 3, the first inductance L1 and the second inductance L2 are inductances of a resonant wireless charging transmitting coil and a resonant wireless charging receiving coil, the first capacitance C1 and the second capacitance C2 are resonance capacitances, and K is a coupling coefficient of the transmitting coil and the receiving coil, respectively. First ac input V of two-way output active rectifier structure ac1 And a second AC input terminal V ac2 Resonant circuit comprising second inductor L2 and second capacitorThe principle of body operation is well known to those skilled in the art and will not be described in detail herein.
The embodiment of the invention also provides a wireless charging circuit, as shown in fig. 10, fig. 10 is a schematic circuit diagram of the wireless charging circuit provided by the embodiment of the invention, and the wireless charging circuit comprises a charging receiving coil 12 and a two-way output active rectifier structure 11 provided by any embodiment of the invention; the input of the two-way output active rectifier structure 11 is electrically connected to a charge receiving coil 12. The two-way output active rectifier structure provided by any embodiment of the present invention has the same advantages, and is not described herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. The double-output active rectifier structure is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a power tube control driving circuit; the double-output active rectifier structure further comprises an alternating current input end, a first output end and a second output end;
the first MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the first output end, and the second MOS tube is connected between the first end of the alternating current input end of the double-output active rectifier structure and the ground; the third MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the second output end, and the fourth MOS tube is connected between the second end of the alternating current input end of the double-output active rectifier structure and the ground; the first MOS tube and the third MOS tube are P-type tubes, and the second MOS tube and the fourth MOS tube are N-type tubes;
the power tube control driving circuit is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube and is used for controlling the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube to be conducted or cut off.
2. The dual output active rectifier structure of claim 1, wherein a source and a substrate of the first MOS transistor are connected to a first output of the dual output active rectifier structure, and a drain of the first MOS transistor is connected to a first end of the ac input; the source electrode and the substrate of the second MOS tube are grounded, and the drain electrode of the second MOS tube is connected with the first end of the alternating current input end; the source electrode and the substrate of the third MOS tube are connected with the second output end of the double-output active rectifier structure, the drain electrode of the third MOS tube is connected with the second end of the alternating current input end, the source electrode and the substrate of the fourth MOS tube are grounded, and the drain electrode of the fourth MOS tube is connected with the second end of the alternating current input end.
3. The dual output active rectifier structure of claim 2, further comprising a fifth MOS transistor and a sixth MOS transistor;
the fifth MOS tube is connected with the second MOS tube in parallel, and the sixth MOS tube is connected with the fourth MOS tube in parallel.
4. The dual output active rectifier architecture of claim 1, wherein the power transistor control drive circuit includes a clock generator, a first mode controller, a second mode controller, and drive logic and a power stage size regulator;
The input end of the clock generator is connected with the alternating current input end of the two-way output active rectifier structure, and the first mode controller is connected with the first output end of the clock generator and the first output end of the two-way output active rectifier structure; the second mode controller is connected with a second output end of the clock generator and a second output end of the two-way output active rectifier structure; the driving logic and the power level size regulator are connected with the first mode controller and the second mode controller, and the output ends of the driving logic and the power level size regulator are respectively connected with the grid electrodes of the MOS tubes; the driving logic and the power level size regulator are used for controlling the on/off of each MOS tube according to different modulation mode signals output by the first mode controller and the second mode controller.
5. The dual output active rectifier structure of claim 4, wherein the first mode controller comprises a first voltage divider circuit, at least two first comparators, at least two first D flip-flops, two second D flip-flops, at least two first nand gates, and a second nand gate;
The input end of the first voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the first voltage dividing circuit divides the voltage of the input end and outputs the divided voltage from at least two output ends, the first input ends of at least two first comparators are correspondingly connected with at least two output ends of the first voltage dividing circuit, and the second input end of the first comparator inputs reference voltage; the data input end of each first D trigger is connected with the output end of each first comparator in a one-to-one correspondence manner, and the clock signal input end of each first D trigger is connected with the first output end of the clock generator;
the two second D flip-flops are cascaded, the clock signal input end of the first second D flip-flop is connected with the first output end of the clock generator, the signal phases output by the two second D flip-flops are output to the first input end of one first NAND gate after being processed, and the signals output by the two second D flip-flops are respectively output to the first input ends of the other two first NAND gates; the second input ends of the first NAND gates are respectively connected with the output ends of the first D flip-flops in a one-to-one correspondence manner; the input end of the second NAND gate is respectively connected with the output end of each first NAND gate, wherein the output end of one first D trigger and the output end of the second NAND gate output modulation mode signals.
6. The dual output active rectifier structure of claim 4, wherein the second mode controller includes a second voltage divider circuit, at least two second comparators, at least two third D flip-flops, two fourth D flip-flops, at least two third nand gates, and a fourth nand gate;
the input end of the second voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the second voltage dividing circuit divides the voltage of the input end and outputs the divided voltage from at least two output ends, the first input ends of at least two second comparators are correspondingly connected with at least two output ends of the second voltage dividing circuit, and the second input end of the second comparator inputs reference voltage; the data input end of each third D trigger is connected with the output end of each second comparator in a one-to-one correspondence manner, and the clock signal input end of each third D trigger is connected with the second output end of the clock generator;
the clock signal input end of the first D trigger is connected with the second output end of the clock generator, the signal phases output by the two fourth D triggers are output to the first input end of one third NAND gate after being processed, and the signals output by the two fourth D triggers are respectively output to the first input ends of the other two third NAND gates; the second input ends of the third NAND gates are respectively connected with the output ends of the third D flip-flops in a one-to-one correspondence manner; the input end of the fourth NAND gate is respectively connected with the output end of each third NAND gate, wherein the output end of one third D trigger and the output end of the fourth NAND gate output modulation mode signals.
7. The dual output active rectifier structure of claim 4, wherein the clock generator includes a third comparator, a fourth comparator, a first falling edge detector, a second falling edge detector, an SR latch, and a first inverter;
the first input ends of the third comparator and the fourth comparator are respectively connected with two ends of the alternating current input end of the two-way output active rectifier structure; the input end of the first falling edge detector is connected with the output end of the third comparator, the output end of the first falling edge detector is connected with the first input end of the SR latch, the input end of the second falling edge detector is connected with the output end of the fourth comparator, and the output end of the second falling edge detector is connected with the second input end of the SR latch; the time input end of the first inverter is connected with the output end of the SR latch, and the output end of the SR latch and the output end of the first inverter output clock signals.
8. The dual output active rectifier architecture of claim 4 wherein said drive logic and power stage sizing agent includes a third voltage divider circuit, a fifth comparator, and a first dead time control circuit;
The input end of the third voltage dividing circuit is connected with the first output end of the two-way output active rectifier structure, the output end of the third voltage dividing circuit is connected with the first input end of the fifth comparator, and the second input end of the fifth comparator inputs a reference voltage; the first dead time control circuit receives a signal output by the output end of the fifth comparator and a modulation mode signal of a first mode controller, and is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube;
the drive logic and power stage sizer further includes a fourth voltage divider circuit, a sixth comparator, and a second dead time control circuit;
the input end of the fourth voltage dividing circuit is connected with the second output end of the two-way output active rectifier structure, the output end of the fourth voltage dividing circuit is connected with the first input end of the sixth comparator, and the second input end of the sixth comparator inputs a reference voltage; the second dead time control circuit receives the signal output by the output end of the sixth comparator and the modulation mode signal of the second mode controller, and the second dead time control circuit is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
9. The dual output active rectifier structure of claim 4 further comprising a boost circuit connected between the gate of the first MOS transistor and the drive logic and power stage size regulator to boost a voltage input to the first MOS transistor.
10. A wireless charging circuit comprising a charging receiver coil and a dual output active rectifier structure as defined in any one of claims 1-9; and the input end of the two-way output active rectifier structure is connected with the charging receiving coil.
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CN202721604U (en) * 2012-06-14 2013-02-06 石家庄通合电子科技股份有限公司 Three-phase active power factor correcting circuit
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