CN111488575B - System and method for actively defending hardware Trojan on storage path - Google Patents

Abstract

The application provides a system and a method for actively defending a hardware Trojan horse on a storage path, wherein the system comprises the following steps: the key unit is connected with the CPU and used for generating keys required by transcoding operation and decoding operation according to instructions of the CPU; the code changing unit is connected with the memory and the key unit and is used for obtaining the original data, carrying out code changing operation on the original data by utilizing the key and transmitting the original data to the memory for storage; and the decoding unit is connected with the memory and the key unit and is used for acquiring the data output by the memory and decoding the data output by the memory by using the key. The application can effectively defend the initial and high-order Trojan, not only can fully realize the hardware Trojan resistance, but also can meet the speed requirement of the memory and ensure the normal operation of the chip.

Description

System and method for actively defending hardware Trojan on storage path

Technical Field

The application relates to the technical field of information security, in particular to a system and a method for actively defending hardware Trojan on a storage path.

Background

The hardware Trojan horse structure generally comprises a trigger module and an execution module. The trigger part generally realizes the trigger of Trojan horse by reading the data field with special meaning in the transmission path or when certain signals or signal combinations meet certain conditions through some built-in trigger mechanisms. Such a trigger mechanism is difficult to find, and there is no very reliable and low cost way in the prior art to achieve a scan detection of hidden Trojan, and the severity of the impact caused once a device containing a hardware Trojan is used is self evident.

Since the chip production in China at the present stage also depends on external enterprises seriously, including EDA (Electronics Design Automation) software of chip design, layout generation and production parts, the links have the possibility of introducing Trojan horse, and the chip application (especially military industry and government affairs) is greatly restricted.

Disclosure of Invention

In order to solve the problems, the application provides a system and a method for actively defending a hardware Trojan on a storage path, which are used for actively defending the hardware Trojan on the storage path inside a chip by converting storage data in a memory into coded data.

The technical scheme of the application is realized as follows:

in a first aspect, the present application provides a system for actively defending against a hardware Trojan on a storage path, comprising:

the key unit is connected with the CPU and used for generating keys required by transcoding operation and decoding operation according to instructions of the CPU;

the code changing unit is connected with the memory and the key unit and is used for obtaining the original data, carrying out code changing operation on the original data by utilizing the key and transmitting the original data to the memory for storage;

and the decoding unit is connected with the memory and the key unit and is used for acquiring the data output by the memory and decoding the data output by the memory by using the key.

Still further, the system is implemented on an FPGA.

Still further, the key unit includes:

the controller is connected with the CPU and is used for receiving the instruction of the CPU and generating an instruction for controlling the random number module according to the instruction of the CPU;

the random number module is connected with the controller and used for generating a master key and a first label according to the instruction of the controller;

and the key generation module is connected with the random number module and is used for generating a plurality of sub-keys according to the main key.

Still further, the key generation module includes:

the key expansion module is used for generating a plurality of sub-keys according to the main key;

the updating control module is used for controlling the time of generating the subkeys by the key expansion module, controlling the sequence of writing the subkeys into the key pool and generating a second label;

and at least two groups of key pools are used for storing sub-keys, wherein at least one group of key pools is used for storing sub-keys of the current period, and at least one group of key pools is used for storing sub-keys updated in the next period.

Still further, the key expansion module iterates the master key using a round function to generate a number of sub-keys.

Still further, the system further comprises:

the first verification unit is connected with the memory and used for verifying the original data and calculating a first verification code, and the first verification code and the data after the code transformation operation are transmitted to the memory for storage;

and the second check unit is connected with the memory and used for checking the data after the decoding operation, calculating a second check code and comparing the first check code with the second check code.

Furthermore, the code changing unit adopts a multi-round PUFFIN algorithm round function iteration structure to change codes of the original data; and the decoding unit adopts a multi-round PUFFIN algorithm round function iteration structure to decode the data output by the memory.

In a second aspect, the present application provides a method for actively defending a hardware Trojan on a storage path, including:

generating a key required by transcoding operation and decoding operation according to the instruction of the CPU;

acquiring original data, performing transcoding operation on the original data by using the secret key, and transmitting the original data to a memory for storage;

and acquiring the data output by the memory, and decoding the data output by the memory by using the secret key.

Still further, the step of generating keys required for the transcoding operation and the decoding operation according to the instructions of the CPU includes:

receiving an instruction of a CPU, and generating an instruction for controlling a random number module according to the instruction of the CPU;

generating a master key and a first tag according to an instruction of a controller;

generating a plurality of sub-keys according to the main key;

the step of generating the master key and the first tag according to the instruction of the controller includes:

each clock signal generates a random number of a first preset bit; in the random number, a part is used as a first tag, and the other part is used as an accumulation signal, and the accumulation signal is accumulated continuously along with the generation of a clock signal;

the accumulated signal accumulated up to the second preset bit is the master key.

Still further, the method further comprises:

checking the original data, calculating a first check code, and transmitting the first check code and the data subjected to the code changing operation to a memory for storage;

checking the data after the decoding operation, calculating a second check code, and comparing the first check code with the second check code;

and if the first check code is not matched with the second check code, discarding the data after the decoding operation.

The application carries out hardware Trojan defense aiming at the memory part in the chip, external data enter the memory, the stored data in the memory is converted into the data after transcoding and is stored in the memory, and the transcoded data has good randomness and no correlation among the data, so that a hardware Trojan triggering mechanism is cut off, initial and high-order Trojan can be effectively defended through Trojan triggering verification test, the hardware Trojan resistance can be fully realized, the speed requirement of the memory can be met, and the normal work of the chip is ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a system for actively defending against hardware Trojan on a storage path according to a first embodiment of the present application;

FIG. 2 is a block diagram of a key unit provided in a second embodiment of the present application;

FIG. 3 is a block diagram of a key generation module according to a second embodiment of the present application;

FIG. 4 is a system diagram of a key generation module according to a second embodiment of the present application;

FIG. 5 is a block diagram of a system for actively defending against hardware Trojan on a storage path provided by a third embodiment of the present application;

fig. 6 is a data path of a transcoding algorithm according to a fourth embodiment of the present application;

FIG. 7 is a logical structure of a round function datapath provided in accordance with a fourth embodiment of the present application;

FIG. 8 is a block diagram illustrating the operation structure of round functions of a transcoding unit according to a fourth embodiment of the present application;

FIG. 9 is a block diagram showing the operation structure of round functions of a decoding unit according to a fourth embodiment of the present application;

fig. 10 is a system architecture diagram of a system application for actively defending against a hardware Trojan on a storage path according to a fourth embodiment of the present application.

Detailed Description

The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present application, and realizing the corresponding technical effects can be fully understood and implemented accordingly. The embodiment of the application and the characteristics in the embodiment can be mutually combined on the premise of no conflict, and the formed technical scheme is within the protection scope of the application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

In the related technology, the hardware Trojan can generate trigger when certain conditions are met by reading data in and out of the memory, so that the starting of the hazardous function is realized, and the normal function of the chip is destroyed or the leakage of the data is realized. Therefore, it is necessary to provide a system and method for actively defending against hardware Trojan on a storage path.

Example 1

Fig. 1 shows a block diagram of a system for actively defending a hardware Trojan on a storage path, and as shown in fig. 1, the system for actively defending a hardware Trojan on a storage path provided in this embodiment includes:

the key unit 100 is connected to the CPU and is used for generating keys required for transcoding and decoding operations according to instructions of the CPU.

The transcoding unit 200 is connected to the memory 400 and the key unit 100, and is used for obtaining the original data, performing transcoding operation on the original data by using the key, and transmitting the original data to the memory for storage. The memory may be, for example, RAM (random access memory ) in a chip.

The decoding unit 300 is connected to the memory and the key unit, and is configured to obtain data output from the memory, and perform decoding operation on the data output from the memory by using the key.

Preferably, the system can be implemented on an FPGA for actively defending against hardware trojans on a storage path of the FPGA.

According to the embodiment, the system provided by the embodiment is applied to the storage path, hardware Trojan defense is carried out on the memory part inside the chip, external data enter the memory, the stored data in the memory are converted into the data after being transcoded and are stored in the memory, and the data after being transcoded have good randomness, so that a hardware Trojan trigger mechanism is cut off, verification tests are triggered through Trojan triggers, the system can effectively defend against initial and high-order Trojan, the hardware Trojan resistance can be fully realized, the speed requirement of the memory can be met, and the normal work of the chip is ensured.

Example two

The present embodiment provides a system for actively defending against a hardware Trojan on a storage path, and on the basis of the first embodiment, as shown in fig. 2, the key unit 100 may include:

the controller 110 is connected to the CPU140, and is configured to receive an instruction from the CPU140, and generate an instruction for controlling the random number module according to the instruction from the CPU 140.

The random number module 120 is connected to the controller 110, and is configured to generate a master key and a first tag according to an instruction of the controller 110. Preferably, the random number module 120 may employ a random number generator, each clock signal generating a random number of a first preset bit; in the random number, one part is used as a tag signal, namely a first tag, and the other part is used as an accumulation signal, wherein the accumulation signal is accumulated continuously along with the generation of a clock signal; the accumulated signal accumulated up to the second preset bit is the master key. For example, the first preset bit is preferably 8, the second preset bit is preferably 64, and specifically, the random number module 120 generates an 8-bit (bit) random number in each clock signal CLK, wherein 6 bits are the first label used for selecting the S-box in the transcoding and decoding unit. The remaining 2 bits of the random number are used as an accumulation of the master key, which is obtained when the 64 bits are accumulated over 32 clock signals CLK, for generating a number of sub-keys.

The key generation module 130 is connected to the random number module 120, and is configured to generate a plurality of sub-keys according to the master key.

Specifically, the CPU140 controls generation of the master key and the first tag through instructions, in practical application, the CPU140 may provide an initial value to the controller 110 during the initialization process, where the initial value is used to determine what mode the system operates in, for example, when the initial value is a first set value (for example, the first set value is 1), which indicates that the system enters a working mode, and actively defends against a hardware Trojan on a storage path, where the controller 110 generates instructions for controlling the random number module 120, the random number module 120 generates the master key and the first tag according to the instructions of the controller 110, and then generates the sub-key as a key required for a transcoding operation and a decoding operation according to the master key through the key generating module 130. For another example, when the initial value is a second set value (for example, the first set value is 0), it indicates that the system enters a test mode, and the key generation module 130 in the key unit 100 is connected to the CPU140 and is configured to receive the random number and the first tag provided by the CPU140, and use the random number provided by the CPU140 as a master key to generate a subkey as a key required for the transcoding operation and the decoding operation, so as to test the system. At this time, the controller 110 does not generate an instruction to control the random number module, and the master key keyinit and the first tag_cpu are supplied from the CPU140 at this time, and the system is operated in this test mode to test the operation effect of the system.

Further, as shown in fig. 3, the key generating module 130 may further include:

a key expansion module 131 for generating a plurality of sub-keys according to the master key; preferably, the key expansion module 131 iteratively generates a number of sub-keys from the master key using Round functions (Round functions), e.g., 8 sub-keys are iteratively generated from the master key.

An update control module 132 (updater) for controlling the time when the sub-keys are generated by the key expansion module 131, controlling the order in which the sub-keys are written to the key pool, and generating a second tag for selecting the key pool in the transcoding operation or the decoding operation.

At least two sets of key pools 133 for storing sub-keys, wherein at least one set of key pools is for storing sub-keys of a current period and at least one set of key pools is for storing sub-keys of a next period update.

Fig. 4 is a system schematic diagram of a Key expansion module 131 (key_schdule), in which a master Key Keyinit is obtained, and the Key expansion module 131 iterates the master Key to generate a plurality of sub-keys by using Round Function; the update control module 132 controls the time at which the sub-keys are generated by the Key expansion module 131 through the first control signal ctrl_key, controls the order in which the sub-keys are written to the Key pools skey_reg (a group of Key pools of the current cycle is skey_reg0-7) through the second control signal key_reg_ctrl, and generates a second tag for selecting a Key pool in a transcoding operation or a decoding operation. Specifically, with S-boxes (the same encoding unit and the PUFFIN algorithm S-boxes used by the decoding unit), only half of S-boxes are used (i.e. the input [4n:4n+3] bits need to pass through the S-boxes, n is an odd number of-1, 3,5 and …), and the remaining half of S-boxes directly enter the next round of operation (i.e. Shift operation), in the Shift operation, n represents the round of the round function, the range of offset is increased, the final result is xored with the P64 result of the original input, and a sub-key can be generated after one round of iteration, so that the key generation module 130 needs to iterate 8 rounds of functions each time of key update, and 8 sub-keys are generated.

In this embodiment, the message lifetime is 10us, namely: at 10us messages must be fetched or discarded, the clock frequency of the system is 400MHZ, i.e. the clock period is 2.5ns, so the message lifetime is at least 4000 CLK, preferably 4096 CLK. Since one CLK period is required for each generation of one subkey, 8 subkeys are a set of key pools, and thus 8 CLK is required for each update of a set of key pools. In order to maintain a smooth update of 4096 CLK key pools, the update control module 132 starts the key expansion module 131 to update (the subkeys in) a set of key pools from the 4096-8 th CLK period after the start of the transcoding module.

Since the message life cycle is 4096 CLK, the minimum holding time of the key pool for decryption should be 4096 CLK cycles, and assuming that data enters the transcoding unit in 4095 th CLK cycle, the theoretical remaining life cycle of the key pool is only 1CLK, if the subkey is directly updated (i.e. the update control module 132 controls the key expansion module 131 to generate a new subkey), the problem that no key is resolvable after data encryption can occur, so two groups of key pools (64 b 16) can be set, after data enter the transcoding module, assuming that when data enter the transcoding module, the subkey of the first group of key pools is used for transcoding, and in 4096 CLK corresponding to the data, the first group of key pools are all kept valid for transcoding, after 4096 CLK, the second group of key pools are updated, and the first group of key pools need to continue to keep 4096 additional time for decoding, so that the life cycle of the first group of key pools is 8192, i.e. when the key expansion module is started every 4096 cycles and the second time and the new key pools are switched, and the first group of key pools are written with the first tag is written with the new key pool, and the first tag is written with the new tag 1, and the tag is simultaneously written with the first tag. The second tag is used for selecting the key pool in the transcoding operation or the decoding operation, so that the storage area can be optimized, and the decoding rate can be improved.

By the embodiment, random conversion of data storage can be realized, and the hardware Trojan trigger probability is greatly reduced.

Example III

The present embodiment provides a system for actively defending against a hardware Trojan on a storage path, as shown in fig. 5, on the basis of the first embodiment, the system further includes:

the first checking unit 500 is connected to the memory 400, and is used for checking the original data, calculating a first check code, and transmitting the first check code and the data after the transcoding operation to the memory 400 for storage.

The second checking unit 600 is connected to the memory 400, and is used for checking the data after decoding operation, calculating a second check code, and comparing the first check code with the second check code.

Preferably, the first checking unit 500 and the second checking unit 600 adopt a CRC checking module (cyclic redundancy check ), the first checking unit 500 performs CRC checking on the data after the transcoding operation, calculates a first CRC check code, and transmits the first CRC check code and the data after the transcoding operation to the memory 400 for storage, the second checking unit 600 performs CRC checking on the data after the decoding operation, calculates a second CRC check code, and compares the first CRC check code with the second CRC check code, if the first CRC check code is the same as the second CRC check code, the data after the decoding operation is valid, otherwise, the data is discarded.

By means of the method and the device, the check codes of the data subjected to the transcoding operation and the data subjected to the decoding operation are compared, and reliability of data transmission can be ensured.

Example IV

The present embodiment provides a system for actively defending against a hardware Trojan on a storage path, and based on the first embodiment, a transcoding unit 200 performs transcoding operation on original data by adopting a multi-round PUFFIN algorithm round function iteration structure. The decoding unit 300 decodes the data output from the memory by using a multi-round PUFFIN algorithm round function iteration structure.

Because the excessive number of code conversion rounds can reduce the code conversion efficiency, and through verification on an FPGA chip, 4 rounds are more advantageous rounds, the multi-round PUFFIN algorithm can be, but is not limited to, a 4-round PUFFIN algorithm, and the multi-round PUFFIN algorithm can also be a 2-round PUFFIN algorithm. The variable and decoding adopts a 4-stage pipeline structure, so that the efficiency is greatly improved, the on-chip area is reduced, and the randomness of the 2-stage pipeline structure still meets the requirement in the actual test.

In the Data path of the transcoding algorithm shown in fig. 6, a round function iteration structure of a 4-round PUFFIN algorithm is adopted, iteration is completed in 4 beats in a pipeline form, input original Data data_in and input labels tag_in (including a first label and a second label) are taken as inputs of a round function, each round of operation needs to select a corresponding subkey from a key pool skey_reg by the input second label, the first label selects a corresponding S-box to participate in operation, and after 4 rounds of iterative computation, data data_in_en and labels tag_out are output. It will be appreciated that if the tag indicates that active defense is not being performed on the hardware Trojan, logic is bypassed, i.e. transcoding is not being performed, and the result is buffered by one intermediate register Round after each iteration is completed, the data is read from that intermediate register Round to the next iteration if the next iteration is continued, and the data is directly from one intermediate register Round to the next intermediate register Round if the next iteration is not to be performed. FIG. 7 is a data path logic structure of a Round function of a primary pipeline, including a Tag selector (including an S-box selection logic module Sbox MUX and a Key selection logic module Key_MUX), where raw data data_in and tags Tag_in enter the Round function as inputs Input, the S-box selection logic module Sbox_MUX selects a corresponding S-box according to a first Tag, the Key selection logic module Key_MUX selects a corresponding sub-Key from a Key pool Skey_reg as a Round Key of the Round Key according to a second Tag, and enters the Round function for iterative computation, and if the tags indicate that active defense hardware Trojan is not performed (i.e. transcoding operation is not needed), logic is bypassed.

Two round functions are involved in the transcoding algorithm: head Round functions (Head functions) and normal Round functions (Round functions). The operation structure of the round function is shown in fig. 8, the input data of the round function is 64 bits, and a common round function includes a first-stage S-box, a layer of round key addition and a layer of permutation operation (P64), and it is understood that the round function can be implemented in a hard-wired manner in hardware design. If the round function is the head round function, the S box operation is not executed, other common round functions except the head round function are input with address write enable addr_w or write enable Wren, wherein round key addition is to exclusive-or the input data with 64-bit subkeys, the replacement operation (P64) of the 64-bit data is shown in a table 1, the input (input) of the table is the bit position before replacement, the table entry content is the bit position in the 64-bit result after replacement, and the hardware design can be realized in a hard-wired mode.

Table 1 substitution operation table of 64-bit data

	0	1	2	3	4	5	6	7
									0	13	2	60	50	51	27	10	36
1	25	7	32	61	1	49	47	19
									2	34	53	16	22	57	20	48	41
3	9	52	6	31	62	30	28	11
									4	37	17	58	8	33	44	46	59
5	24	55	63	38	56	39	15	23
									6	14	4	5	26	18	54	42	45
7	21	35	40	3	12	29	43	64

Taking the example that the random number module 120 generates 8 bits of random numbers in each clock signal CLK in the first embodiment, 6 bits are the first label, the embodiment provides 3 alternative transcoding S-boxes, which are respectively SA, SB, SC, and 2 bits correspond to one S-box in the 6 bits of the first label, so the first label may also be called as an S-box label tag_sbox, the S-boxes are selected according to the corresponding bits (2 bits) in the first label during round function operation, the corresponding relation is as shown in table 2, for one packet, the S-boxes used by each round function are the same, the corresponding subkey skey_n selected from the key pool skey_reg is selected for exclusive-or operation XOR, then the permutation operation is performed, and then the next round is entered. The Key selection logic module key_mux in the round function is configured to select the subkey of the current round from 8 subkeys generated by the Key expansion module 131. The Key selection logic module key_mux controls the round Key sequence number used per round by inputting a 4-bit random number (tag_skey). The round keys used in the original case are 0,1,2 and 3 in sequence, namely the first 4 keys are used in sequence, 4 rounds are sequentially corresponding to 4-bit random numbers, if the random number corresponding to a round key is 0, the sub key is kept unchanged, and if the random number corresponding to a round key is 1, the round key times are increased by 1. Illustrating: when the 4-bit random value tag_skey is 0110, the round key used is 0,2,4,5.

Table 2 correspondence table of S box labels and S box

S box label	Calculation of
		00	Does not make code change
01	SA: PUFFIN algorithm S box
		10	SB: preSENT algorithm S box
11	SC: inverse of PRESENT algorithm S-box

Wherein, three S-box operations are respectively shown in tables 3 to 5:

table 3 SA: PUFFIN algorithm S box

Input device	0	1	2	3	4	5	6	7
									Output of	D	7	3	2	9	A	C	1
Input device	8	9	A	B	C	D	E	F
									Output of	F	4	5	E	6	0	B	8

Table 4 SB: preSENT algorithm S box

x	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
																	S[x]	C	5	6	B	9	O	A	D	3	E	F	8	4	7	1	2

Table 5 PRESENT Algorithm S-box inverse operation

x	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
																	S(x)	5	E	F	8	C	1	2	D	B	4	6	3	0	7	9	A

Because of the relative nature of the PUFFIN algorithm, the encryption and decryption processes have extremely high similarity, so the decoding algorithm is also completed in 4 beats in a pipeline form by adopting a 4-round PUFFIN algorithm round function iteration structure, the overall structure is completely consistent with that of FIG. 6, the logic structure of a thinned primary pipeline is consistent with that of FIG. 7, and the round functions of a transcoding unit and a decoding unit are consistent in execution process, but have two differences:

in the first aspect, since the variable decoding needs to generate a reciprocal relationship, the variable decoding has a difference in a mapping relationship in which SA (PUFFIN algorithm S-box) itself is reciprocal, SB (presence algorithm S-box) is reciprocal to SC (inverse of presence algorithm S-box).

In a second aspect, the sub-Key selection process is determined by the tag in the Key selection logic module key_mux.

Fig. 9 is a round function operation flow chart of the decoding unit, and in contrast to the round function operation flow chart of the transcoding unit shown in fig. 8, two changes exist, namely, a mapping relationship of the S box, and the round key needs to participate in the XOR operation of the exclusive-or operation module after passing through the P64 replacement module.

Table 6 is a table of correspondence between S boxes and the first Tag in the decoding operation, and the S boxes are selected according to the corresponding bits (2 bits) in the first Tag, and the other rules are consistent with the transcoding unit.

Table 6 correspondence table of S box labels and S box

Tag_Sbox	Calculation of
		00	Does not decode
01	SA: PUFFIN algorithm S box
		10	SC: inverse of PRESENT algorithm S-box
11	SB: preSENT algorithm S box

The Key selection logic module Key_MUX has a difference in the realization flow under the condition of transcoding and decoding. The decoding unit restores the reverse order of the current round keys used in transcoding from the 8 sub-keys generated in advance (the original PUFFIN algorithm directly uses the reverse order of the round keys used in the encryption process to decrypt, that is, the round keys Skey0,1,2,3 …, k-1, k are used in sequence in encryption, and the round keys Skey k, k-1, k-2 … 1,0 are used in sequence in decryption).

The Key selection logic module key_mux controls the round Key sequence number used per round by a 4-bit random value (tag_skey) previously generated in the transcoding unit. The round keys used in the original case are sequentially 3, 2, 1 and 0, that is, the first 4 keys are sequentially used in reverse order, for 4 rounds of random numbers, the hamming weight of the round key use sequence number 3 of the last round of original and the 4-bit random number is added (this is to obtain the round key of the first round used for descrambling, that is, the round key of the last round used for transcoding) before decoding starts, then the corresponding random number bit is scanned in reverse order, if the random number corresponding to the bit is 0, its round key sequence number is decremented by 1, and if the random number corresponding to the bit is 1, the round key sequence number is decremented by 2. Illustrating: when tag_skey is 0101, the round key used according to the above transcoding is 0,2, 3,5, and in the decoding process, the round key number of the last round is calculated as 5 (3+hw (0110) = 3+z.

The system of the present embodiment can be applied to fig. 10 showing a system architecture in which dina: data; wra: write enable; csa: chip selection enabling; addra: address bits; code (Ri): wheel function of transcoding unit (ith wheel); DECODE (Ri): wheel function of decoding unit (i-th wheel); PRNG: a random number generator for generating a master key and a first tag; key_schdule: the key expansion module is used for generating a sub-key according to the main key; k master: a master Key received by a Key expansion module Key_schdule; tag_in: tag, marks key information (e.g., selected subkey) used by each data, transcoding algorithm information (e.g., S box), and CRC check bits, tag_cpu: the label provided by CPU, set-signature: a setting signal provided by the CPU.

According to the embodiment, the key is marked through the tag, so that the storage area can be optimized, the decoding rate is improved, and the variable and decoding adopts a multi-stage pipeline structure, so that the efficiency is greatly improved, and the on-chip area is reduced.

Example five

The embodiment provides a method for actively defending a hardware Trojan on a storage path, which is implemented based on the system for actively defending the hardware Trojan on the storage path in the embodiment, and the method comprises the following steps:

step S100, generating a key required by transcoding operation and decoding operation according to an instruction of a CPU;

step S200, obtaining original data, performing transcoding operation on the original data by using a secret key, and transmitting the original data to a memory for storage;

step S300, obtaining data output by the memory, and decoding the data output by the memory by using the secret key.

In step S200, a multi-round PUFFIN algorithm round function iteration structure may be used to perform transcoding operation on the original data. In step S300, the data output from the memory may be decoded using a multi-round PUFFIN algorithm round function iteration structure. The multi-round PUFFIN algorithm may be, but is not limited to, a 4-round PUFFIN algorithm, and the multi-round PUFFIN algorithm may also be a 2-round PUFFIN algorithm.

According to the embodiment, hardware Trojan protection is performed on the memory part inside the chip, external data enter the memory, stored data in the memory are converted into data after transcoding and are stored in the memory, and as the transcoded data have good randomness and no correlation among the data, a hardware Trojan triggering mechanism is cut off, initial and high-order Trojan can be effectively protected through Trojan triggering verification tests, hardware Trojan resistance can be fully achieved, the speed requirement of the memory can be met, and normal operation of the chip is ensured.

Example six

The present embodiment provides a method for actively defending a hardware Trojan on a storage path, and based on the fifth embodiment, step S100 further includes the following sub-steps:

step S110, receiving an instruction of a CPU, and generating an instruction for controlling a random number module according to the instruction of the CPU;

step S120, generating a master key and a first label according to an instruction of the controller;

specifically, step S120 further includes:

step S121, generating a random number of a first preset bit by each clock signal; in the random number, one part is used as a tag signal, namely a first tag, and the other part is used as an accumulation signal, wherein the accumulation signal is accumulated continuously along with the generation of a clock signal;

step S122, accumulating the accumulated signals reaching the second preset bit as the master key.

For example, the first preset bit is preferably 8, the second preset bit is preferably 64, and specifically, the random number module 120 generates an 8-bit (bit) random number in each clock signal CLK, wherein 6 bits are the first label used for selecting the S-box in the transcoding and decoding unit. The remaining 2 bits of the random number are used as an accumulation of the master key, which is obtained when the 64 bits are accumulated over 32 clock signals CLK, for generating a number of sub-keys.

Step S130, generating a plurality of sub-keys according to the main key.

Because there is no correlation between random data, the master key generated by random data can not only fully realize the hardware Trojan resistance, but also meet the speed requirement of the memory and ensure the normal operation of the chip.

Further, step S130 includes the following sub-steps:

step S131, generating a plurality of sub-keys according to the main key; preferably, the master key may be iteratively generated into several sub-keys using a Round Function (Round Function), e.g. 8 sub-keys are iteratively generated from the master key.

Step S132, controlling the time of generating the sub-keys, controlling the order in which the sub-keys are written into the key pool, and generating a second tag for selecting the key pool in the transcoding operation or the decoding operation. The second tag is merged with the first tag and written with the data to the tag field of the memory. The second tag is used for selecting the key pool in the transcoding operation or the decoding operation, so that the storage area can be optimized, and the decoding rate can be improved.

To ensure reliability of the data transmission, the method may further comprise:

and S500, checking the original data, calculating a first check code, and transmitting the first check code and the data subjected to the code transformation operation to a memory for storage.

Step S600, checking the data after the decoding operation, calculating a second check code, and comparing the first check code with the second check code;

step S700, if the first check code is not matched with the second check code, discarding the data after decoding operation.

The data of the transcoding operation is compared with the check code of the data after the decoding operation, unmatched data are discarded, and matched data are reserved and output, so that the reliability of data transmission can be ensured.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Although the embodiments of the present application are described above, the above description is only for the convenience of understanding the present application, and is not intended to limit the present application. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the appended claims.

Claims (9)

1. A system for actively defending against hardware trojans on a storage path, comprising:

the key unit is connected with the CPU and used for generating keys required by transcoding operation and decoding operation according to instructions of the CPU;

the code changing unit is connected with the memory and the key unit and is used for obtaining the original data, carrying out code changing operation on the original data by utilizing the key and transmitting the original data to the memory for storage;

the decoding unit is connected with the memory and the key unit and is used for acquiring the data output by the memory and decoding the data output by the memory by using the key;

the key unit includes:

the random number module is connected with the controller and used for generating a master key and a first label according to the instruction of the controller, and the first label is used for selecting an S box in the code changing and decoding unit;

the key generation module is connected with the random number module and is used for generating a plurality of sub-keys according to the master key;

the key generation module includes:

the key expansion module is used for generating a plurality of sub-keys according to the main key;

at least two groups of key pools for storing sub-keys, wherein at least one group of key pools is used for storing sub-keys of the current period, and at least one group of key pools is used for storing sub-keys updated in the next period;

the updating control module is used for controlling the time of generating the sub-keys by the key expansion module, controlling the sequence of writing the sub-keys into the key pool and generating a second label, wherein the second label realizes the selection of the key pool in the transcoding operation or the decoding operation;

when the original data enter a transcoding module, the sub-keys of a first group of key pools are firstly used for transcoding, the sub-keys of the first group of key pools are kept valid for transcoding in the message lifetime corresponding to the data, after the message lifetime, a second group of key pools are updated, the second group of key pools are started to be adopted for transcoding, and the first group of key pools continue to additionally keep the message lifetime for decoding.

2. The system for actively defending against hardware trojans on a memory path of claim 1, wherein the system is implemented on an FPGA.

3. The system for actively defending a hardware Trojan on a storage path of claim 1, wherein the key unit further comprises:

and the controller is connected with the CPU and is used for receiving the instruction of the CPU and generating an instruction for controlling the random number module according to the instruction of the CPU.

4. The system for actively defending a hardware Trojan on a storage path of claim 3 wherein said key expansion module iterates said master key using a round function to generate a number of subkeys.

5. The system for actively defending a hardware Trojan on a storage path of claim 1, further comprising:

the first verification unit is connected with the memory and used for verifying the original data and calculating a first verification code, and the first verification code and the data after the code transformation operation are transmitted to the memory for storage;

and the second check unit is connected with the memory and used for checking the data after the decoding operation, calculating a second check code and comparing the first check code with the second check code.

6. The system for actively defending against a hardware Trojan horse on a storage path according to claim 1, wherein the transcoding unit performs transcoding operation on the original data by adopting a multi-round PUFFIN algorithm round function iteration structure; and the decoding unit adopts a multi-round PUFFIN algorithm round function iteration structure to decode the data output by the memory.

7. A method of actively defending against hardware trojans on a storage path, the method implemented using the system of any of claims 1-6, the method comprising:

generating a key required by transcoding operation and decoding operation according to the instruction of the CPU;

acquiring original data, performing transcoding operation on the original data by using the secret key, and transmitting the original data to a memory for storage;

and acquiring the data output by the memory, and decoding the data output by the memory by using the secret key.

8. The method of actively defending against hardware Trojan on a memory path according to claim 7, wherein the step of generating keys required for transcoding and decoding operations according to instructions of a CPU comprises:

receiving an instruction of a CPU, and generating an instruction for controlling a random number module according to the instruction of the CPU;

generating a master key and a first tag according to an instruction of a controller;

generating a plurality of sub-keys according to the main key;

the step of generating the master key and the first tag according to the instruction of the controller includes:

each clock signal generates a random number of a first preset bit; in the random number, a part is used as a first tag, and the other part is used as an accumulation signal, and the accumulation signal is accumulated continuously along with the generation of a clock signal;

the accumulated signal accumulated up to the second preset bit is the master key.

9. The method of actively defending a hardware trojan on a storage path of claim 7, further comprising:

checking the original data, calculating a first check code, and transmitting the first check code and the data subjected to the code changing operation to a memory for storage;

checking the data after the decoding operation, calculating a second check code, and comparing the first check code with the second check code;

and if the first check code is not matched with the second check code, discarding the data after the decoding operation.