CN1114867C - 外围部件互连装置及其提供方法和计算机系统 - Google Patents
外围部件互连装置及其提供方法和计算机系统 Download PDFInfo
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Abstract
本发明公开了数据处理系统的一种增强的外围部件互连(PCI)结构。按照本发明的方法与系统,数据处理系统的外围部件互连(PCI)结构包括PCI主机总线、若干PCI局部总线及PCI热插接桥。各局部PCI总线具有一适配器卡槽。连接在PCI主机总线与PCI局部总线之间的PCI热插接桥用来控制各PCI局部总线的电源,使得在加电期间同时位于其它适配器卡槽中的适配器卡内正在进行处理时可从任何一个适配器卡槽中去掉或向其中增加一PCI适配器卡。
Description
本发明一般涉及数据处理的结构,具体地说涉及数据处理系统内的外围部件互连结构。更具体地说,本发明涉及具有数据处理系统的热插接性能的增强的外围部件互连结构。
计算机系统或数据处理系统通常包含系统总线。连接在系统总线上的有可在该系统总线上本地互相通信的各种设备。例如,典型的计算机系统包含在其上连接有中央处理单元(CPU)的系统总线,并且在其上CPU还与连接在该系统总线上的系统存储器直接通信。
此外,计算机系统可包含局部总线,用于连接与CPU在同一总线上的某些高度集成的外围部件。这种局部总线之一称作外围部件互连(PCI)总线。在PCI局部总线标准下,外围部件能直接连接在PCI局部总线上而无须“粘结”逻辑。从而,PCI提供了一种总线标准,在其上能将诸如图形显示设备与运动影象显示设备等高性能外围设备耦合在CPU上,借此能使这些高性能外围设备避免在将这些外围设备连接在标准外围总线上时会出现的通常的存取等待时间及带宽限制。
PCI局部总线为带有多路复用的地址与数据线的高性能32位或64位总线。任何PCI部件与添加卡接口都是与处理器无关的,能够高效地过渡到未来代的处理器及与多处理器体系结构使用。处理器独立性还能为I/O功能优化PCI局部总线,能进行局部总线与处理器/存储器子系统的并行操作,并接纳多个高性能外围设备。此外,在PCI局部总线下的32位数据与地址总线的透明64位扩展允许将总线带宽加倍及提供32位与64位PCI局部总线外围设备的向前与向后兼容性。
大多数计算机总线通常不设计成处理从总线本身上突然地除去外围设备。可以这样说,在连接到计算机总线上的适配器槽中插入或除去适配器卡而不遵循适当的顺序可导致意想不到的后果,其中包含数据破坏、操作系统的不正常中止或对适配器卡或平台硬件的破坏。
对在PCI局部总线下的热插接性能有着规定,并且PCI局部总线的热插接标准是根据PCI专业组颁布的PCI热插接规范定义的,这里通过引用作为参考。虽然在上述出版物中一般性地定义了PCI热插接标准,但并未规定详细的实现。本公开描述了启动这种热插接性能所必需的增强PCI体系结构的电子与服务标志器。
鉴于上文,因此本发明的目的是提供用于数据处理的改进结构。
本发明的另一目的是提供数据处理系统的改进的外围部件互连结构。
本发明的又一目的是提供具有数据处理系统的热插接性能的增强的外围部件互连结构。
按照本发明的方法与系统,数据处理系统的外围部件互连(PCI)结构包括PCI主机总线、若干PCI局部总线及PCI热插接桥。各局部PCI总线具有适配器卡槽。连接在PCI主机总线与PCI局部总线之间的PCI热插接桥是用来控制各PCI局部总线的电功率的,使得在接通期间当位于其它适配器卡槽中的适配器卡中存在着正在进行的处理时可以在任何一个适配器卡槽中去掉或增加PCI适配器卡。
在下面的详细描述中,本发明的全部目的、特征及优点将成为显而易见的。
通过结合附图阅读对照下面示例性的实施例的详细描述,将更好地理解本发明本身以及其最佳的使用模式、进一步的目的及优点,其中:
图1为具有在其中可应用本发明的较佳实施例的PCI局部总线结构的典型计算机系统的方框图;以及
图2为按照本发明的较佳实施例的数据处理系统的具有热插接性能的PCI局部总线结构的方框图。
可将本发明应用在不同操作系统下的各种计算机中。该计算机可以是诸如个人计算机、中型计算机或大型计算机。为了示例目的,下面描述的本发明的较佳实施例是实现在诸如国际商用机器公司制造的IBM AS/400TM等中型计算机上的。IBM AS400TM为国际商用机器公司的商标。
现在参见附图尤其是图1,其中描绘了具有可应用本发明的较佳实施例的PCI局部总线结构的典型计算机系统的方框图。如图所示,处理器12、高速缓冲存储器13、存储器控制器14及动态随机存取存储器(DRAM)15连接在计算机系统10的系统总线28上。处理器12、高速缓冲存储器13、存储器控制器14及DRAM15还通过PCI主桥11耦合在计算机系统10的PCI主机总线26上。此外,PCI主机总线26通过PCI局部桥25耦合在PCI局部总线20上。PCI主桥11及PCI局部桥25提供低等待时间路径,通过它处理器12可直接存取映射到总线存储器与/或I/O地址空间内任何位置上的PCI设备。PCI主桥11及PC局部桥25还提供允许PCI主直接存取DRAM15的高带宽路径。PCI主桥11及PCI局部桥25可包含诸如数据高速缓冲存储/登记及仲裁等各种功能。
连接在PCI局部总线20上的还可有诸如局域网(LAN)接口16及小型计算机系统接口(SCSI)18等其它设备。LAN接口16用于将计算机系统10连接到诸如以太网或令牌环等局域网17上。SCS1 18用来控制高速SCSI盘驱动器19。
通常,无须任何扩充性能PCI局部总线20便可支持多达4个添加板(add-in board)连接器。音频适配器板22、移动图象适配器板23及图形适配器板24为可以通过添加板连接器连接到PCI局部总线20上的一些设备的实例。
现在参见图2,其中示出了按照本发明的较佳实施例用于数据处理系统的具有热插接性能的增强的PCI局部总线结构的方框图。如图所示,PCI主机总线26通过PCI主桥11耦合在系统总线28上,而PCI主机总线26则连接在PCI热插接桥21上。诸如PCI主机总线26等在PCI热插接桥21的初级侧上的PCI总线称作PCI主机总线或初级PCI总线。PCI主桥11负责产生PCI主机总线。诸如PCI局部总线27a~27h等从PCI热插接桥21的次级侧出来的所有PCI总线称作PCI局部总线或次级PCI总线。
按照本发明的较佳实施例,对于数据处理系统内的各初级PCI总线,PCI热插接桥21可提供多达8条分离的次级PCI局部总线27a~27h。然而,熟悉本技术的人员可以理解,也有可能是任何数目的次级PCI总线。将各次级PCI局部总线进一步连接在适配器槽上。例如,如图2中所示,将次级PCI局部总线连接在适配器槽29a上。
此外,还将PCI热插接桥21耦合在锁存器25上。作为本发明的较佳实施例,PCI热插接桥21通过五个不同的I/O针耦合在锁存器25上,这五个I/O针即通电复位31、加载时钟32、移位时钟33、数据输入34及数据输出35。各相应的针31~35用于在每个适配器槽的基础上锁定、读取或驱动服务指示器及功率控制电路。另一方面,锁存器25的输出是:
·8个用于FET(场效应管)控制的输出,每个适配器槽一个
·8个用于LED(发光二极管)的输出,每个适配器槽一个
·8个用于检测电源良好的输入,每个适配器槽一个
·8个用于检测电源故障的输入,每个适配器槽一个
·16个用于检测适配器卡存在的输出,每个适配器槽两个。
为了示例目的,只将来自锁存器25的一组输出示出为耦合在适配器槽29a上。来自锁存器25的各其它组输出(未示出)耦合在对应于次级PCI总线27b~27h的各其它适配器槽(未示出)上。利用FET控制36来指示FET41为适配器槽29a接通或切断电源。FET控制36间接地受PCI热插接桥21的寄存器内的锁存器控制。在通电复位时,FET控制36将被驱动到低电平。通电复位之后,PCI热插接桥21将所有的适配器槽加电。加电可一次或顺序完成。在加电之后,可由固件接通或断开适配器槽。在加电复位活跃期间或直到对PCI热插接电桥21的电源是良好的为止,FET控制逻辑(未示出)也将保证FET41断开。
利用LED37来指示何时能进行并行的修复。LED37间接地受到PCI热插接桥21的寄存器内的锁存器控制。作为本发明的较佳实施例,LED37的有效状态为接通、断开与闪烁。在加电复位期间,LED37将关断。加电复位之后,可接通、断开LED36或将其设定为闪烁。
利用电源良好输入38来通知PCI热插接桥21对诸如适配器槽29a等单个适配器槽的电压是正常的。这是必要的,因为FET41将缓慢地接通适配器卡的电源以协助充电某些内部电容器。如果适配器卡由于某种原因短路,则功率不会上升。为了防止对热插接桥21中的驱动器的损坏,PCI热插接桥21将保持与该适配器卡关联的PCI局部总线在三态中。然后PCI热插接电桥21监视电源良好输入38,并在PCI局部总线改变其状态时通知操作系统(或任何其它有关控制软件)。当在任何时钟周期上检测到电源良好输入38向INACTIVE(不活跃)变化时,PCI热插接桥21将用于该PCI局部总线的驱动器放置在三态模式中,并将值写入寄存器中及产生一个中断。当检测到电源良好输入38进入ACTIVE(活跃)至少20毫秒时,PCI热插接桥21启动其用于PCI局部总线的驱动器,并将值写入寄存器中及产生一个中断。
电源故障输入39通知PCI热插接桥21底板FET已读到过流故障,并且这是不确立电源良好输入38的原因。在这一情况中,最有可能是涉及有缺陷的适配器卡。如果不确立电源良好输入38及未驱动过电流,则最有可能是由于有缺陷的PCI热插接桥21或故障的FET41.PCI热插接桥21监视电源故障输入39以便在电源故障输入39改变其状态时通知任何相关的软件。当在任何时钟周期上检测到电源故障输入39进入ACTIVE(活跃)时,PCI热插接桥21这时便将该值写入寄存器中及生成中断。当检测到电源故障输入39进入INACTIVE(不活跃)至少20毫秒时,PCI热插接电桥21便将该值写入寄存器中及生成中断。
此外,PCI热插接电桥21能为各适配器槽感测两个卡电源检测针(即PRSNT 40a及PRSNT 40b)。只用来自PCI热插接电桥21的5个I/O针中的4个,即加载时钟32、移位时钟33、数据输入34及数据输出35,来控制来自锁存器25的全部48个输出信号。
由于来自锁存器25的所有输出信号,还指示适配器卡电力的使用情况(瓦),也将输入信号馈送到局部功率调节器中(未示出),后者在局部功率调节器的最大功率被超过时将故障浮显给系统功率控制网(SPCN)。SPCN又将故障浮显给数据处理系统的操作系统,指出在PCI热插接桥21下的适配器卡配置是无效的。从而,如果超过了适配器卡功率,局部功率调节器防止施加电力。
虽然标准PCI桥(诸如图1中的PCI局部桥25)可以允许将多个适配器卡连接在单一的PCI局部总线上,PCI热插接桥21生成多达8个次级PCI桥并将一条次级PCI总线用于各适配器卡。因此,PCI热插接桥21能集中功率控制及其它各种服务功能到多条次级PCI总线上以及消除由每一次级PCI总线多个适配器卡引起的负荷效应。各PCI局部总线27a~27h也提供有受控的三稳态输出,从而能除去电源而不损坏PCI热插接电桥21、PCI主机电桥11或任何其它不受影响的次级PCI总线。
下面是按照本发明的较佳实施例的利用PCI热插接结构与设计的并行修复操作的实例。首先,主机接口请示切断所要求的适配器槽上的电源。然后,主机软件为所要求的适配器槽及PCI热插接电桥21的三态输出停顿对应的次级PCI总线槽。然后PCI热插接电桥21降低对所要求的适配器槽的FET的功率(+3.3V、+5.0V、+12.0V、-12.0V)。随后,PCI热插接桥21点亮与所要求的适配器槽关联的LED,以指示现在能执行并行修复。在这一点上,客户工程师(或任何有资格的技术人员)便能从该适配器槽中取出适配器卡。由于只切断一条受影响的次级PCI总线的电源,所以没有时间限制。然后PRSNT线40a、40b指示已从所要求的适配器槽中取走适配器卡。在装入了新适配器卡之后,PRSNT线40a、40b将指示装入完成。在PCI热插接桥21从底板槽接收电力之后便驱动接通该适配器槽。最后,PCI热插接电桥21恢复其正常操作。
如已描述的,本发明为数据处理系统提供具有热插接性能的增强的PCI结构。这一增强的PCI体系结构使PCI适配器卡是可以热插接的,即在接通电源期间在数据处理系统的其它部件上正在进行有用处理的同时可以去掉或增加任何单个适配器卡。本发明的PCI热插接桥具有一条初级PCI总线(PCI主机总线)作为输入,并最好8条次级PCI总线(PCI局部总线)作为输出。PCI热插接桥在所有适配器槽之间提供PCI局部电隔离,使得能执行热插接而不干扰或影响在初级PCI总线下运行的其它次级PCI总线的操作。此外,PCI热插接桥还提供逻辑总线隔离,使得可将PCI适配器卡热插接到每个或任何适配器槽中,同时其它装入的PCI适配器卡可继续运行它们的正常操作。
虽然已对照较佳实施例具体示出和描述了本发明,但熟悉本技术的人员应理解可在其中进行形式上与细节上的各种改变而不脱离本发明的精神与范围。
Claims (12)
1.一种数据处理系统的外围部件互连装置,包括:
一条PCI主机总线;
多条PCI局部总线,各具有一适配器卡槽;以及
一个PCI热插接桥,连接在所述PCI主机总线与所述多条PCI局部总线之间,用于控制所述多条PCI局部总线的电源,借此在位于其它适配器卡槽中的其它适配器卡内正在进行处理期间能从适配器卡槽中去掉或向其中增加PCI适配器卡。
2.按照权利要求1的数据处理系统的外围部件互连装置,其特征在于所述多条PCI局部总线可从两条PCI局部总线到8条PCI局部总线。
3.按照权利要求1的数据处理系统的外围部件互连装置,其特征在于所述PCI热插接桥还包括用于控制锁存器的至少四个控制信号。
4.按照权利要求3的数据处理系统的外围部件互连装置,其特征在于所述锁存器包含至少五个输出,其中所述五个输出的三个用来控制与所述多条PCI局部总线之一关联的适配器卡槽。
5.按照权利要求4的数据处理系统的外围部件互连装置,其特征在于所述五个输出的三个包括FET控制信号、电源良好信号及电源故障信号。
6.一种具有外围部件互连结构的计算机系统,包括:
一个处理器;
连接在系统总线上的与所述处理器关联的一个系统存储器;
将所述系统总线耦合到PCI主机总线上的一个PCI主机桥;
耦合在所述PCI主机总线上用于提供多条PCI局部总线的PCI热插接桥,其中各所述多条PCI局部总线与一PCI适配器卡槽关联,其中所述PCI热插接桥还控制各所述多条PCI局部总线的电源,借此,在系统加电且位于其它适配器卡槽中的其它适配器卡内正在进行处理期间可从适配器卡槽中去掉或向其中增加PCI适配器卡。
7.按照权利要求6的具有PCI结构的计算机系统,其特征在于所述多条PCI局部总线可从两条PCI局部总线到8条PCI局部总线。
8.按照权利要求6的具有PCI结构的计算机系统,其特征在于所述PCI热插接桥还包括至少4个用于控制锁存器的控制信号。
9.按照权利要求8的具有PCI结构的计算机系统,其特征在于所述锁存器还包含至少五个输出,其中所述五个输出中三个用于控制所述多条PCI局部总线之一上的适配器卡槽。
10.按照权利要求9的具有PCI结构的计算机系统,其特征在于所述五个输出中三个包含FET控制信号、电源良好信号及电源故障信号。
11.一种为数据处理系统提供增强的外围部件互连(PCI)结构的方法,其中所述数据处理系统包含系统总线及PCI主机总线,所述方法包括下述步骤:
在所述系统总线与所述PCI主机总线之间连接一PCI主机桥;以及
在所述PCI主机总线上连接用于提供多条PCI局部总线的PCI热插接桥,其中该步骤还包括:
将各所述多条PCI局部总线与一PCI适配器卡槽关联,以及
所述PCI热插接桥控制各所述多条PCI局部总线的电源,使得在系统加电及位于其它适配器卡槽中的其它适配器卡内正在进行处理期间,可从适配器卡槽中去掉或向其中增加PCI适配器卡。
12.按照权利要求11的为数据处理系统提供增强的PCI结构的方法,其特征在于所述多条PCI局部总线可从两条PCI局部总线到8条PCI局部总线。
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US878025 | 1978-02-15 | ||
US08/878,025 US5875308A (en) | 1997-06-18 | 1997-06-18 | Peripheral component interconnect (PCI) architecture having hot-plugging capability for a data-processing system |
US878,025 | 1997-06-18 |
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CN1202656A CN1202656A (zh) | 1998-12-23 |
CN1114867C true CN1114867C (zh) | 2003-07-16 |
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CN98108466A Expired - Fee Related CN1114867C (zh) | 1997-06-18 | 1998-05-15 | 外围部件互连装置及其提供方法和计算机系统 |
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US (1) | US5875308A (zh) |
CN (1) | CN1114867C (zh) |
MY (1) | MY117404A (zh) |
TW (1) | TW371330B (zh) |
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-
1998
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- 1998-05-15 MY MYPI98002183A patent/MY117404A/en unknown
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TW371330B (en) | 1999-10-01 |
US5875308A (en) | 1999-02-23 |
MY117404A (en) | 2004-06-30 |
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