CN111475869B - Communication method, device, medium, secure computing module and secure chip - Google Patents
Communication method, device, medium, secure computing module and secure chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
- G06F21/725—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits operating on a secure reference time value
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/86—Secure or tamper-resistant housings
- G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
Abstract
The present disclosure relates to a communication method, apparatus, medium, secure computing module, and secure chip. The method applied to the secure computing module comprises the following steps: and sending a first task set to the security chip in the current period, wherein the first task set comprises a first calculation task request from an application program received in the first period, so that the security chip processes the first calculation task request in the current period and/or the second period, and returns a first processing result obtained by processing the first calculation task request in a third period. And if the second task set is sent to the security chip in the fourth period, receiving a second processing result returned by the security chip in the current period. And sending the second processing result to the application program. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, and the response speed of calculation task requests is improved.
Description
Technical Field
The present disclosure relates to the field of secure communications technologies, and in particular, to a communication method, apparatus, medium, secure computing module, and secure chip.
Background
In order to ensure effective operation of the internet of vehicles communication system, vehicle data (such as a current running state of a vehicle, a current position of the vehicle, etc.) may be uploaded to a cloud end or sent to other vehicles through communication means. Many sensitive information about the privacy of the vehicle owner or important criteria affecting other vehicle behaviors are included. If such information is compromised or tampered with, it is likely that significant life and property damage will be incurred to the vehicle occupants or pedestrians. Therefore, it is necessary To establish a systematic security mechanism To protect the information security of the V2X (Vehicle-To-evaluation) system.
In modern cryptography, the public key cryptographic algorithm realizes the separation of an encryption key and a decryption key by selecting a proper trapdoor one-way function, and effectively solves the limitation of the symmetric cryptographic algorithm. However, public key cryptography algorithms generally require more computing resources to be consumed, and in an environment where such computing resources are limited and time-limited, the use of a separate security chip to accomplish the secure computing task is a better implementation.
At present, after a secure computing module sends a computing task request to a secure chip, other operations are not performed, and after the secure chip returns a computing result, the secure chip can send the next computing task request. The synchronous blocking communication mode is simple, and the communication performance and the computing resource of the security chip are wasted greatly.
Disclosure of Invention
In order to solve the problems in the related art, the present disclosure provides a communication method, apparatus, medium, secure computing module, and secure chip.
According to a first aspect of embodiments of the present disclosure, there is provided a secure chip communication method, applied to a secure computing module, including:
transmitting a first task set to a security chip in a current period, wherein the first task set comprises a first calculation task request from an application program received in the first period, so that the security chip processes the first calculation task request in the current period and/or a second period, and returns a first processing result obtained by processing the first calculation task request in a third period, wherein the first period is the last period of the current period, the second period is the next period of the current period, and the third period is the next period of the second period;
If a second task set is sent to the security chip in a fourth period, receiving a second processing result returned by the security chip in the current period, wherein the second task set comprises a second calculation task request from the application program received in a fifth period, the second processing result is a processing result obtained by the security chip processing the second calculation task request, the fifth period is a period previous to the fourth period, and the fourth period is a period previous to the first period;
and sending the second processing result to the application program.
Optionally, the secure computing module and the secure chip are in two-way communication via one of: serial peripheral interface SPI, serial computer expansion bus PCIE, universal serial bus USB.
Optionally, the sending the first task set to the security chip in the current period includes:
acquiring all the first computing task requests from the application program received in the first period to obtain the first task set;
allocating a first receiving buffer zone for the first task set, wherein the first receiving buffer zone is used for receiving the first processing result;
And sending the first task set to the security chip in the current period.
Optionally, the receiving, during the current period, the second processing result returned by the secure chip includes:
receiving the second processing result returned by the security chip through a second receiving buffer zone in the current period, wherein the second receiving buffer zone is allocated for the second task set before the second task set is sent to the security chip;
transmitting the second processing result in the second receiving buffer to the application program;
releasing the second receive buffer.
Optionally, the sending the first task set to the security chip in the current period includes:
and if a closing instruction is generated before the current period and the first calculation task request is received in the first period before the closing instruction is generated, sending the first task set to the security chip in the current period.
According to a second aspect of the embodiments of the present disclosure, there is provided a secure chip communication method, applied to a secure chip, including:
if the third task set sent by the secure computing module is received in the sixth period, processing a computing task request included in the third task set in the current period to obtain a third processing result, wherein the third processing result is sent to the secure computing module by the secure chip in the seventh period; the sixth period is a period previous to the current period, and the seventh period is a period next to the current period;
And if a fourth processing result is obtained before the sixth period is finished, sending the fourth processing result to the secure computing module in the current period, wherein the fourth processing result is a processing result obtained by the secure chip processing a computing task request included in a fourth task set, the fourth task set is received by the secure chip from the secure computing module in an eighth period, and the eighth period is the previous period of the sixth period.
Optionally, if the third task set sent by the secure computing module is received in the sixth period, processing, in the current period, a computing task request included in the third task set includes:
and if the third task set is received in the sixth period and the computing task requests in the third task set are still not processed after the sixth period is finished, processing the computing task requests which are not processed in the third task set in the current period.
Optionally, the method further comprises:
if a fifth task set sent by the secure computing module is received in the current period, then:
Processing the computing task requests included in the fifth task set in the current period when the processing of all the computing task requests in the third task set is completed before the current period is finished; or alternatively, the process may be performed,
and caching the fifth task set to process the calculation task request included in the fifth task set in the seventh period.
According to a third aspect of embodiments of the present disclosure, there is provided a secure chip communication apparatus applied to a secure computing module, including:
the first sending module is used for sending a first task set to the security chip in a current period, wherein the first task set comprises a first calculation task request from an application program received in the first period, the security chip processes the first calculation task request in the current period and/or a second period, and returns a first processing result obtained by processing the first calculation task request in a third period, wherein the first period is the period above the current period, the second period is the period below the current period, and the third period is the period below the second period;
The first receiving module is configured to receive, in the current period, a second processing result returned by the security chip if a second task set is sent to the security chip in a fourth period, where the second task set includes a second calculation task request from the application program received in a fifth period, the second processing result is a processing result obtained by the security chip processing the second calculation task request, and the fifth period is a period previous to the fourth period, and the fourth period is a period previous to the first period;
and the second sending module is used for sending the second processing result to the application program.
Optionally, the first sending module may include:
an obtaining sub-module, configured to obtain all the first computing task requests from the application program received in the first period, so as to obtain the first task set;
an allocation submodule, configured to allocate a first receiving buffer area for the first task set, where the first receiving buffer area is used to receive the first processing result;
and the first sending submodule is used for sending the first task set to the security chip in the current period.
Optionally, the first receiving module may include:
the receiving sub-module is used for receiving the second processing result returned by the security chip through a second receiving buffer zone in the current period, wherein the second receiving buffer zone is allocated for the second task set before the second task set is sent to the security chip;
a second sending sub-module, configured to send the second processing result in the second receiving buffer to the application program;
and the release submodule is used for releasing the second receiving buffer zone.
Optionally, the first sending module is configured to send the first task set to the security chip in the current period if a shutdown instruction is generated before the current period, and the first computing task request is received in the first period before the shutdown instruction is generated.
According to a fourth aspect of embodiments of the present disclosure, there is provided a secure chip communication apparatus applied to a secure chip, including:
the processing module is used for processing the calculation task request included in the third task set in the sixth period and/or the current period if the third task set sent by the security calculation module is received in the sixth period, so as to obtain a third processing result, wherein the third processing result is sent to the security calculation module by the security chip in a seventh period; the sixth period is a period previous to the current period, and the seventh period is a period next to the current period;
And the third sending module is configured to send, if a fourth processing result is obtained before the sixth period ends or if an eighth period is obtained, the fourth processing result to the secure computing module in the current period, where the fourth processing result is a processing result obtained by the secure chip processing a computing task request included in a fourth task set, the fourth task set is received by the secure chip from the secure computing module in the eighth period, and the eighth period is a period previous to the sixth period.
Optionally, the processing module is configured to, if the third task set is received in the sixth period and a computing task request in the third task set remains unprocessed after the sixth period ends, process the computing task request that has not been processed in the third task set in the current period.
Optionally, the processing module is further configured to, if the fifth task set sent by the secure computing module is received in the current period: processing the computing task requests included in the fifth task set in the current period when the processing of all the computing task requests in the third task set is completed before the current period is finished; or alternatively, the process may be performed,
And caching the fifth task set to process the calculation task request included in the fifth task set in the seventh period.
According to a fifth aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the secure chip communication method provided by the first aspect of the present disclosure.
According to a sixth aspect of embodiments of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the secure chip communication method provided by the second aspect of the present disclosure.
According to a seventh aspect of embodiments of the present disclosure, there is provided a secure computing module comprising:
a memory having a computer program stored thereon;
a processor for executing the computer program in the memory to implement the steps of the secure chip communication method provided in the first aspect of the present disclosure.
According to an eighth aspect of embodiments of the present disclosure, there is provided a security chip comprising:
a memory having a computer program stored thereon;
a processor for executing the computer program in the memory to implement the steps of the secure chip communication method provided in the second aspect of the present disclosure.
By the technical scheme, the security calculation module can send the first task set to the security chip in the current period, receive the second processing result returned by the security chip in the current period and send the second processing result to the application program. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, the security chip can process more data, and the response speed of calculation task requests is improved.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
fig. 1 is a schematic diagram illustrating an environment in which a secure chip communication method is implemented, according to an exemplary embodiment.
Fig. 2 is a flow chart illustrating a method of secure chip communication according to an exemplary embodiment.
Fig. 3 is a flow chart illustrating another secure chip communication method according to an example embodiment.
Fig. 4 is a timing diagram illustrating a secure chip communication method according to an example embodiment.
Fig. 5 is a block diagram illustrating a secure chip communication device according to an example embodiment.
Fig. 6 is a block diagram illustrating another secure chip communication device in accordance with an example embodiment.
Fig. 7 is a block diagram of an electronic device, according to an example embodiment.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
Fig. 1 is a schematic diagram of a secure chip communication system, shown in accordance with an exemplary embodiment. As shown in fig. 1, the system may include an application 101, a secure computing module 102, and a secure chip 103. The application 101 and the secure computing module 102 are communicatively coupled, for example, by Socket communication, pipeline communication, or shared memory. The secure computing module 102 is communicatively coupled to the secure chip 103, such as by a serial peripheral interface (Serial Peripheral Interface, SPI), serial computer expansion bus PCIE (Peripheral Component Interconnect Express, PCIE), universal serial bus USB (Universal Serial Bus, USB), etc., as long as full duplex communication between the secure computing module 102 and the secure chip 103 is enabled.
In the present disclosure, an internet of vehicles communication system is taken as an example to describe in detail, but the embodiments of the present disclosure are not limited thereto, and any other application scenario using the above-mentioned security chip communication system is within the scope of the present disclosure. The application 101 is an application with a safety calculation requirement, such as a speed limit early warning application, a vehicle forward collision early warning application, a red light early warning application, and the like. The secure computing module 102 is configured to receive a computing task request sent by the application 101, and send the computing task request to the secure chip 103, so that the secure chip 103 processes (e.g., encrypts, signs, decrypts, or verifies a signature, etc.) the computing task request. Thereafter, the secure chip 103 transmits the processing result to the secure computation module 102, so that the secure computation module 102 feeds back the processing result to the application 101.
In the related art, after sending a calculation task request to the security chip, the security calculation module does not perform other operations, and after waiting for the security chip to return a calculation result, the security module can send the next calculation task request. The synchronous blocking communication mode is simple, and the communication performance and the computing resource of the security chip are wasted greatly. In this regard, the present disclosure provides a secure chip communication method, apparatus, computer-readable storage medium, secure computing module, and secure chip capable of implementing two-way communication between the secure computing module and the secure chip.
It should be noted that the first period to the eighth period mentioned below are used to represent a relative timing relationship between periods, particularly a timing relationship with respect to a current period. With the change of the current period, the first period to the eighth period correspondingly change. In practical application, the period length of each period is the same, and the period length can be calibrated in advance.
Furthermore, the first to the X-th task sets mentioned below are only used to distinguish task sets transmitted by the secure computing module to the secure chip in different periods. As the current period changes, the first to the X-th task sets also change.
Fig. 2 is a flow chart illustrating a method of secure chip communication according to an exemplary embodiment. The method may be applied to a secure computing module, as shown in fig. 2, and may include the following steps.
In S201, a first task set is sent to the security chip in the current period, where the first task set includes a first computing task request from the application program received in the first period, so that the security chip processes the first computing task request in the current period and/or the second period, and returns a first processing result obtained by processing the first computing task request in the third period. The first period is a period previous to the current period, the second period is a period next to the current period, and the third period is a period next to the second period.
Wherein the first computing task request is a computing task request from an application program received by the secure computing module within a first period. For example, the first computing task request may be a decryption request or a signature verification request of vehicle data (such as a vehicle speed, a position, etc. of the other vehicle) received by the application program, or an encryption request or a signature request of vehicle data (such as a vehicle speed, a position, etc. of the host vehicle) to be sent to the other vehicle or the cloud server by the application program. Correspondingly, the first processing result obtained by processing the first computing task request may include the vehicle data of the other vehicle after decryption by the security chip, or include the vehicle data of the other vehicle after verification by the security chip, or include the vehicle data of the vehicle after encryption by the security chip after encryption, or include the vehicle data of the vehicle after signature obtained by the security chip after signature by the security chip after signing the vehicle data of the vehicle in the signature request. It should be noted that, the application program may send the first computing task request to the secure computing module at any time in the first period, and the number of the first computing task requests received by the secure computing module in the first period may be one or more.
In this step, after the security chip receives the first task set sent by the security computing module in the current period, the security chip may process the first computing task requests in the first task set in the current period and/or in the next period (i.e., the second period) of the current period, and send the first processing results obtained after the processing of all the first computing task requests in the first task set in the next two periods (i.e., the third period) of the current period to the security computing module. As described above, the number of the first calculation task requests may be plural, and in this case, the processing result corresponding to each first calculation task request is included in the first processing result.
For example, when the number of the first computing task requests included in the first task set is small (for example, lower than the first preset number), the security chip may process the first computing task requests in the first task set only in the current period, or may process the first computing task requests in the first task set only in the second period, so as to obtain a first processing result corresponding to the first computing task requests.
Also for example, when the number of first computing task requests included in the first task set is greater (for example, higher than the second preset number, which is greater than the first preset number described above), the security chip may process the first computing task requests in the first task set in the current period and the second period to obtain a first processing result corresponding to the second period before the second period ends.
In S202, if the second task set is sent to the secure chip in the fourth period, the second processing result returned by the secure chip is received in the current period. Wherein the fourth period is a period previous to the first period.
Wherein the second set of tasks includes a second request for computing tasks from the application received during the fifth period. The fifth cycle is the previous cycle to the fourth cycle. The second processing result is a processing result obtained by processing the second calculation task request by the security chip. Since the secure chip can complete the processing of the second computing task requests in the second task set before the last cycle of the current cycle (i.e., the first cycle described above) ends, the secure chip can return the second processing results to the secure computing module in the current cycle, where the second processing results include the processing results corresponding to each second computing task request.
In S203, the second processing result is transmitted to the application program.
In the current period, the secure computing module may send the second processing result to the application program after receiving the second processing result, so that the application program may use, for example, to analyze whether the decrypted data is legal or send the encrypted data to other vehicles or the cloud server.
By the technical scheme, the security calculation module can send the first task set to the security chip in the current period, receive the second processing result returned by the security chip in the current period and send the second processing result to the application program. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, the security chip can process more data, and the response speed of calculation task requests is improved.
In one possible implementation, the secure computing module and the secure chip communicate bi-directionally via one of the following: serial peripheral interface SPI, serial computer expansion bus PCIE, universal serial bus USB.
For example, the secure computing module may send the first task set to the secure chip at the start time of the current period, and receive the second processing result returned by the secure chip, so as to implement full duplex communication between the secure computing module and the secure chip, thereby improving the communication efficiency of the secure computing module and the secure chip. It should be noted that, the secure computing module and the secure chip may perform bidirectional communication at the start time of the current period, or may perform bidirectional communication at any time of the current period, which is not limited in this disclosure.
In the above S201, sending the first task set to the security chip in the current period may include:
acquiring all first computing task requests from an application program received in a first period to obtain a first task set;
allocating a first receiving buffer zone for the first task set, wherein the first buffer zone is used for receiving a first processing result;
and sending the first task set to the security chip in the current period.
For example, after the secure computing module receives the first computing task request from the application program in the first period, the secure computing module may allocate a corresponding first buffer for the first computing task request and store the first computing task request in the first buffer, so that the secure computing module may obtain, from the first buffer, all the first computing task requests received by the secure computing module in the first period in the current period, and combine all the first computing task requests in the first buffer into the first task set.
Then, the security calculation module allocates a first receiving buffer zone for the first task set, wherein the first receiving buffer zone is used for receiving the first processing result. The first receiving buffer may be a buffer with a fixed size, or the size of the first receiving buffer may be determined according to the size of the first task set, which is not limited in this disclosure. Finally, the secure computing module may send the first set of tasks to the secure chip during the current period. Therefore, after the first receiving buffer area is allocated to the first task set, the safety calculation module can receive the first processing result sent by the safety chip through the first receiving buffer area in the third period, so that the first processing result can be guaranteed to be normally received by the safety calculation module, and the loss of the first processing result is avoided.
In S202 above, receiving the second processing result returned by the secure chip in the current period may include:
in the current period, receiving a second processing result returned by the security chip through a second receiving buffer zone;
transmitting the second processing result in the second receiving buffer to the application program;
the second receive buffer is released.
Wherein the second receive buffer is allocated for the second set of tasks before sending the second set of tasks to the secure chip. In this way, in the current period, the secure computing module can receive the second processing result returned by the secure chip through the pre-allocated second receiving buffer zone, and release the second receiving buffer zone after sending the second processing result to the application program, thereby avoiding the waste of storage resources.
In the present disclosure, in S201, sending the first task set to the security chip in the current period may further include:
if a shutdown instruction is generated before the current period and a first calculation task request is received in the first period before the shutdown instruction is generated, a first task set is sent to the security chip in the current period.
For example, a close button of the secure chip communication system may be provided at a preset location (e.g., bottom) of the in-vehicle display screen. When the user operates the close button, such as clicking, the secure chip communication system may receive a close instruction. In the present disclosure, after the application program receives the shutdown instruction, the computing task request is no longer sent to the secure computing module.
If a closing instruction is generated in a period before the first period, the application program does not send a first calculation task request to the secure calculation module in the first period any more, so that the secure calculation module in the current period does not have the first calculation task request to be sent, and therefore the first task set is not sent to the secure chip any more. If a shutdown instruction is generated in the first period and the secure computing module does not receive the first computing task request before the shutdown instruction is generated, the secure computing module does not send the first task set to the secure chip in the current period. If a shutdown instruction is generated before the current period and the secure computing module receives a first computing task request within the first period before the shutdown instruction is generated, the secure computing module sends a first task set to the secure chip during the current period. Thus, whether or not to send the first set of tasks to the secure chip in the current period depends on whether or not the first computing task requests to be sent are stored in the secure computing module, and if so, all the first computing task requests are combined into the first set of tasks and sent to the secure chip. If not, the first set of tasks is no longer sent to the secure chip.
And after the secure computing module sends the first task set to the secure chip in the current period, executing the operation in S202, so that the secure computing module receives a first processing result obtained by processing the first computing task request in the first task set in a third period, and feeds the first processing result back to the application program. After which the entire secure chip communication system is shut down.
It should be noted that, after receiving the close instruction, the secure chip communication system may also directly close the secure communication system, regardless of whether the secure computing module stores the computing task request to be sent and whether the secure chip has an unprocessed computing task request. The closing manner of the secure chip communication system is not particularly limited in the present disclosure.
Fig. 3 is a flow chart illustrating another secure chip communication method according to an example embodiment. The method is applied to a security chip. As shown in fig. 3, the secure communication method may include the following steps.
In S301, if the third task set sent by the secure computing module is received in the sixth period, the computing task request included in the third task set is processed in the current period, so as to obtain a third processing result. The third processing result is sent to the secure computing module by the secure chip in a seventh period. Wherein the sixth period is the last period of the current period, and the seventh period is the next period of the current period.
For example, as described above, the computing task request may be a decryption request or a signature verification request of vehicle data (e.g., vehicle speed, position, etc. of other vehicles) of the other vehicles received by the application program, or an encryption request or a signature request of vehicle data (e.g., vehicle speed, position, etc. of other vehicles) of the host vehicle to be transmitted to the other vehicles or the cloud server by the application program. Correspondingly, the third processing result may include the vehicle data of the other vehicle after decryption by the security chip, or the vehicle data of the other vehicle after verification by the security chip, or the vehicle data of the vehicle after encryption by the security chip, or the vehicle data of the vehicle after signature by the security chip.
It should be noted that, the secure chip supports simultaneous processing of multiple paths of data, for example, supports simultaneous processing of 3 paths of data, so that after the secure chip receives a task set to be processed, for example, a third task set, a plurality of calculation task requests can be sequentially extracted from the task set, and the plurality of calculation task requests are simultaneously processed until all calculation task requests in the task set are processed, thereby improving the processing efficiency of the secure chip.
In S302, if the fourth processing result is obtained before the sixth period ends, the fourth processing result is sent to the secure computing module in the current period.
The fourth processing result is a processing result obtained by processing the computing task request included in the fourth task set by the security chip.
By the technical scheme, the security chip can process the calculation task request included in the third task set in the current period and can send a fourth processing result to the security calculation module in the current period. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, the security chip can process more data, and the response speed of calculation task requests is improved.
Optionally, if the third task set is sent by the secure computing module received in the sixth period, processing, in the current period, a computing task request included in the third task set, including:
and if the third task set is received in the sixth period and the computing task requests in the third task set are still not processed after the sixth period is finished, processing the computing task requests which are not processed in the third task set in the current period.
In the present disclosure, if the third task set is received in the sixth period, the security chip may process the computing task request included in the third task set in the current period.
For example, if the number of computing task requests in the third task set is small (e.g., lower than the first preset number), the computing task requests in the third task set may be processed only in the current period.
As another example, if the number of computing task requests in the third task set is greater (e.g., higher than the second preset number), the computing task requests in the third task set may be processed in the sixth cycle and the current cycle.
Optionally, the method may further include:
if a fifth task set sent by the secure computing module is received in the current period, then:
processing the computing task requests included in the fifth task set in the current period when the processing of all the computing task requests in the third task set is completed before the current period is finished; or alternatively, the process may be performed,
and caching the fifth task set to process the calculation task request included in the fifth task set in the seventh period.
In the present disclosure, after the secure chip receives the third task set in the sixth period, the secure chip may process the computing task request in the third task set in the sixth period, and/or in the current period, so the secure chip may complete the processing of the computing task request in the third task set in the sixth period or in the current period. If the processing of the computing task request in the third task set is completed before the end of the current period, the secure chip may begin processing the fifth task set for the remaining time of the current period. Alternatively, the security chip may also cache the received fifth task set to process the computing task request included in the fifth task set in the seventh cycle.
In order to facilitate a better understanding of the secure chip communication methods provided by the present disclosure by those skilled in the art, a complete exemplary embodiment is described below. It should be understood that the exemplary embodiments are for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Referring to fig. 4, a detailed process of the secure chip communication method provided in the present disclosure is illustrated. Fig. 4 is a timing diagram illustrating a secure chip communication method according to an example embodiment. The operation of the steps in the secure chip communication method described above in connection with fig. 2-3 can be better understood by those skilled in the art with reference to fig. 4.
Hereinafter, TM i -TM i+1 The period of time of (5) is referred to as TM i Period, e.g. TM 0 -TM 1 The period of time of (5) is referred to as TM 0 Period of TM 1 -TM 2 The period of time of (5) is referred to as TM 1 Period, and so on. The secure chip communication method of the present disclosure is described below in the order of cycles:
in S401, at TM 0 Periodically, the application program sends a computing task request to the secure computing module.
Wherein, in TM 0 Periodically, the secure chip communication system has just started. In this period, the secure computing module is configured to receive a computing task request sent by an application and to be in the TM 0 The received secure task requests in the cycle are stored in a buffer. In addition, this cycle also requires the initialization operation of the SPI communication module (not shown) and the security chip to be completed.
In S402, at TM 1 Periodically, the application program sends a computing task request to the secure computing module.
In S403, the secure computing module will be in TM 0 The computing task requests received in a cycle form a task set (denoted as DTM 0 -TM 1 ]) And sending the data to the security chip.
For example, the secure computing module may be in a TM 1 The start of the cycle will be at TM 0 All computing task requests received in a cycle are combined into a task set D [ TM ] 0 -TM 1 ]And sending to the security chip.
In S404, at TM 2 Periodically, the application program sends a computing task request to the secure computing module.
In S405, the secure computing module will be in TM 1 Periodically received set of computing task requestsTask-forming set (denoted as DTM 1 -TM 2 ]) And sending the data to the security chip.
In S406, at TM 2 Periodically, the security chip gathers the task set D [ TM ] 0 -TM 1 ]Processing to obtain the result RTM 0 -TM 1 ]。
In S407, at TM 3 Periodically, the application program sends a computing task request to the secure computing module.
In S408, the secure computing module will be in TM 2 The received computing task requests in a cycle form a task set (denoted as DTM 2 -TM 3 ]) Transmitting to the security chip, and receiving the processing result RTM returned by the security calculation module 0 -TM 1 ]。
For example, the secure computing module and secure chip may be in a TM 2 SPI full duplex communication is effected at the beginning of the cycle, i.e. at TM 2 The security computing module sends a task set D (TM) to the security chip at the beginning of the cycle 2 -TM 3 ]Simultaneously receiving the processing result RTM returned by the security chip 0 -TM 1 ]。
In S409, at TM 3 Periodically, the security chip gathers the task set D [ TM ] 1 -TM 2 ]Processing to obtain the result RTM 1 -TM 2 ]。
In S410, the secure computing module, upon receipt of the processing result Rtm 0 -TM 1 ]Thereafter, the processing result Rtm is sent to the application program 0 -TM 1 ]。
In S411, at TM 4 In the period, the application program sends a calculation task request to the secure calculation module.
In S412, the application is in TM 4 A shutdown instruction is received in a cycle. After receiving the close instruction, the application program no longer sends a computing task request to the secure computing module.
In S413, the secure computing module will be in TM 3 The received computing task requests in a cycle form a task set (denoted as DTM 3 -TM 4 ]) Sent to the security chipSimultaneously receiving the processing result RTM returned by the security calculation module 1 -TM 2 ]。
In S414, at TM 4 Periodically, the security chip gathers the task set D [ TM ] 2 -TM 3 ]Processing to obtain the result RTM 2 -TM 3 ]。
In S415, the secure computing module, upon receipt of the processing result Rtm 1 -TM 2 ]Thereafter, the processing result Rtm is sent to the application program 1 -TM 2 ]。
In S416, the secure computing module will be in TM 4 The received computing task requests in a cycle form a task set (denoted as DTM 4 -TM 5 ]) Transmitting to the security chip, and receiving the processing result RTM returned by the security calculation module 2 -TM 3 ]。
In S417, at TM 5 Periodically, the security chip gathers the task set D [ TM ] 3 -TM 4 ]Processing to obtain the result RTM 3 -TM 4 ]。
In S418, the secure computing module, upon receiving the processing result Rtm 2 -TM 3 ]Thereafter, the processing result Rtm is sent to the application program 2 -TM 3 ]。
In S419, the secure computing module receives the processing result RTM sent by the secure chip 3 -TM 4 ]。
In S420, at TM 5 Periodically, the security chip gathers the task set D [ TM ] 4 -TM 5 ]Processing to obtain the result RTM 4 -TM 5 ]。
In S421, the security computing module receives the processing result Rtm 3 -TM 4 ]Thereafter, the processing result Rtm is sent to the application program 3 -TM 4 ]。
In S422, the secure computing module receives the processing result RTM sent by the secure chip 3 -TM 4 ]。
In S423, the secure computing module, upon receiving the processing result Rtm 3 -TM 4 ]Thereafter, the processing result Rtm is sent to the application program 3 -TM 4 ]。
The security chip communication system has completed the processing of all the calculation task requests and the data transmission, and then the whole system is closed.
Based on the same inventive concept, the embodiment of the disclosure also provides a secure chip communication device. Referring to fig. 5, fig. 5 is a block diagram of a secure chip communication apparatus according to an exemplary embodiment, applied to a secure computing module, as shown in fig. 5, the apparatus 500 may include:
a first sending module 501, configured to send a first task set to a security chip in a current period, where the first task set includes a first computing task request from an application program received in a first period, so that the security chip processes the first computing task request in the current period and/or a second period, and returns a first processing result obtained by processing the first computing task request in a third period, where the first period is a period above the current period, the second period is a period next to the current period, and the third period is a period next to the second period;
The first receiving module 502 is configured to receive, if a second task set is sent to the security chip in a fourth period, a second processing result returned by the security chip in the current period, where the second task set includes a second calculation task request from the application program received in a fifth period, the second processing result is a processing result obtained by the security chip processing the second calculation task request, and the fifth period is a period previous to the fourth period, and the fourth period is a period previous to the first period;
and a second sending module 503, configured to send the second processing result to the application program.
By the technical scheme, the security calculation module can send the first task set to the security chip in the current period, receive the second processing result returned by the security chip in the current period and send the second processing result to the application program. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, the security chip can process more data, and the response speed of calculation task requests is improved.
Optionally, the first sending module 501 includes:
an obtaining sub-module, configured to obtain all the first computing task requests from the application program received in the first period, so as to obtain the first task set;
an allocation submodule, configured to allocate a first receiving buffer area for the first task set, where the first receiving buffer area is used to receive the first processing result;
and the first sending submodule is used for sending the first task set to the security chip in the current period.
Optionally, the first receiving module includes:
the receiving sub-module is used for receiving the second processing result returned by the security chip through a second receiving buffer zone in the current period, wherein the second receiving buffer zone is allocated for the second task set before the second task set is sent to the security chip;
a second sending sub-module, configured to send the second processing result in the second receiving buffer to the application program;
and the release submodule is used for releasing the second receiving buffer zone.
Optionally, the first sending module is configured to send the first task set to the security chip in the current period if a shutdown instruction is generated before the current period, and the first computing task request is received in the first period before the shutdown instruction is generated.
Based on the same inventive concept, the embodiment of the disclosure also provides a secure chip communication device. Referring to fig. 6, fig. 6 is a block diagram of another security chip communication device according to an exemplary embodiment, applied to a security chip, as shown in fig. 6, the device 600 may include:
a processing module 601, configured to, if the third task set sent by the secure computing module is received in a sixth period, process, in the sixth period and/or the current period, a computing task request included in the third task set to obtain a third processing result, where the third processing result is sent by the secure chip to the secure computing module in a seventh period; the sixth period is a period previous to the current period, and the seventh period is a period next to the current period;
and a third sending module 602, configured to send, in the current period, a fourth processing result to the secure computing module if the fourth processing result is obtained before the sixth period ends or if an eighth period is obtained, where the fourth processing result is a processing result obtained by the secure chip processing a computing task request included in a fourth task set, and the fourth task set is received by the secure chip from the secure computing module in the eighth period, and the eighth period is a period previous to the sixth period.
By the technical scheme, the security chip can process the calculation task request included in the third task set in the current period and can send a fourth processing result to the security calculation module in the current period. Therefore, the communication efficiency between the security calculation module and the security chip is effectively improved, the idle waiting time of the security chip is reduced, the security chip can process more data, and the response speed of calculation task requests is improved.
Optionally, the processing module 601 is configured to process, if the third task set is received in the sixth period and a computing task request in the third task set is still not yet processed after the sixth period is over, the computing task request in the third task set that is not yet processed in the current period.
Optionally, the processing module 601 is further configured to, if the fifth task set sent by the secure computing module is received in the current period: processing the computing task requests included in the fifth task set in the current period when the processing of all the computing task requests in the third task set is completed before the current period is finished; or alternatively, the process may be performed,
And caching the fifth task set to process the calculation task request included in the fifth task set in the seventh period.
The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.
Fig. 7 is a block diagram of an electronic device 700, according to an example embodiment. As shown in fig. 7, the electronic device 700 may include: a processor 701, a memory 702. The electronic device 700 may also include one or more of a multimedia component 703, an input/output (I/O) interface 704, and a communication component 705.
The processor 701 is configured to control the overall operation of the electronic device 700 to perform all or part of the steps in the secure chip communication method described above. The memory 702 is used to store various types of data to support operation on the electronic device 700, which may include, for example, instructions for any application or method operating on the electronic device 700, as well as application-related data, such as contact data, messages sent and received, pictures, audio, video, and so forth. The Memory 702 may be implemented by any type or combination of volatile or non-volatile Memory devices, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read-Only Memory, PROM for short), read-Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia component 703 can include a screen and an audio component. Wherein the screen may be, for example, a touch screen, the audio component being for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory 702 or transmitted through the communication component 705. The audio assembly further comprises at least one speaker for outputting audio signals. The I/O interface 704 provides an interface between the processor 701 and other interface modules, which may be a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is for wired or wireless communication between the electronic device 700 and other devices. Wireless communication, such as Wi-Fi, bluetooth, near field communication (Near Field Communication, NFC for short), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or one or a combination of more of them, is not limited herein. The corresponding communication component 705 may thus comprise: wi-Fi module, bluetooth module, NFC module, etc.
In an exemplary embodiment, the electronic device 700 may be implemented by one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated ASIC), digital signal processor (Digital Signal Processor, abbreviated DSP), digital signal processing device (Digital Signal Processing Device, abbreviated DSPD), programmable logic device (Programmable Logic Device, abbreviated PLD), field programmable gate array (Field Programmable Gate Array, abbreviated FPGA), controller, microcontroller, microprocessor, or other electronic components for performing the secure chip communication method described above.
In another exemplary embodiment, a computer readable storage medium is also provided, comprising program instructions which, when executed by a processor, implement the steps of the secure chip communication method described above. For example, the computer readable storage medium may be the memory 702 including program instructions described above, which are executable by the processor 701 of the electronic device 700 to perform the secure chip communication method described above.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.
In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.
Claims (14)
1. A secure chip communication method, applied to a secure computing module, comprising:
transmitting a first task set to a security chip in a current period, wherein the first task set comprises a first calculation task request from an application program received in the first period, so that the security chip processes the first calculation task request in the current period and/or a second period, and returns a first processing result obtained by processing the first calculation task request to the application program in a third period, wherein the first period is the last period of the current period, the second period is the next period of the current period, and the third period is the next period of the second period;
If a second task set is sent to the security chip in a fourth period, receiving a second processing result returned by the security chip in the current period, wherein the second task set comprises a second calculation task request from the application program received in a fifth period, the second processing result is a processing result obtained by the security chip processing the second calculation task request, the fifth period is a period previous to the fourth period, and the fourth period is a period previous to the first period;
and sending the second processing result to the application program.
2. The method of claim 1, wherein the secure computing module and the secure chip communicate bi-directionally via one of:
serial peripheral interface SPI, serial computer expansion bus PCIE, universal serial bus USB.
3. The method of claim 1, wherein the sending the first set of tasks to the secure chip during the current period comprises:
acquiring all the first computing task requests from the application program received in the first period to obtain the first task set;
Allocating a first receiving buffer zone for the first task set, wherein the first receiving buffer zone is used for receiving the first processing result;
and sending the first task set to the security chip in the current period.
4. The method of claim 1, wherein receiving the second processing result returned by the secure chip during the current period comprises:
receiving the second processing result returned by the security chip through a second receiving buffer zone in the current period, wherein the second receiving buffer zone is allocated for the second task set before the second task set is sent to the security chip;
transmitting the second processing result in the second receiving buffer to the application program;
releasing the second receive buffer.
5. The method according to any one of claims 1-4, wherein the sending the first set of tasks to the security chip during the current period comprises:
and if a closing instruction is generated before the current period and the first calculation task request is received in the first period before the closing instruction is generated, sending the first task set to the security chip in the current period.
6. A secure chip communication method, applied to a secure chip, comprising:
if the third task set sent by the secure computing module is received in the sixth period, processing a computing task request included in the third task set in the sixth period and/or in the current period to obtain a third processing result, wherein the third processing result is sent to the secure computing module by the secure chip in a seventh period; the sixth period is a period previous to the current period, and the seventh period is a period next to the current period;
and if a fourth processing result is obtained before the sixth period is finished, sending the fourth processing result to the secure computing module in the current period, wherein the fourth processing result is a processing result obtained by the secure chip processing a computing task request included in a fourth task set, the fourth task set is received by the secure chip from the secure computing module in an eighth period, and the eighth period is the previous period of the sixth period.
7. The method of claim 6, wherein the secure computing module and the secure chip communicate bi-directionally via one of:
Serial peripheral interface SPI, serial computer expansion bus PCIE, universal serial bus USB.
8. The method according to claim 6, wherein if the third task set sent by the secure computing module is received in the sixth period, processing the computing task request included in the third task set in the current period includes:
and if the third task set is received in the sixth period and the computing task requests in the third task set are still not processed after the sixth period is finished, processing the computing task requests which are not processed in the third task set in the current period.
9. The method of claim 6, wherein the method further comprises:
if a fifth task set sent by the secure computing module is received in the current period, then:
processing the computing task requests included in the fifth task set in the current period when the processing of all the computing task requests in the third task set is completed before the current period is finished; or alternatively, the process may be performed,
and caching the fifth task set to process the calculation task request included in the fifth task set in the seventh period.
10. A secure chip communication device, for use in a secure computing module, comprising:
the first sending module is configured to send a first task set to a security chip in a current period, where the first task set includes a first computing task request from an application program received in a first period, so that the security chip processes the first computing task request in the current period and/or a second period, and returns a first processing result obtained by processing the first computing task request to the application program in a third period, where the first period is a period above the current period, the second period is a period below the current period, and the third period is a period below the second period;
the first receiving module is configured to receive, in the current period, a second processing result returned by the security chip if a second task set is sent to the security chip in a fourth period, where the second task set includes a second calculation task request from the application program received in a fifth period, the second processing result is a processing result obtained by the security chip processing the second calculation task request, and the fifth period is a period previous to the fourth period, and the fourth period is a period previous to the first period;
And the second sending module is used for sending the second processing result to the application program.
11. A security chip communication device, characterized by being applied to a security chip, comprising:
the processing module is configured to, if the third task set sent by the secure computing module is received in the sixth period, process, in the sixth period, a computing task request included in the third task set and/or in a current period, so as to obtain a third processing result, where the third processing result is sent by the secure chip to the secure computing module in a seventh period; the sixth period is a period previous to the current period, and the seventh period is a period next to the current period;
and the third sending module is configured to send, if a fourth processing result is obtained before the sixth period ends, the fourth processing result to the secure computing module in the current period, where the fourth processing result is a processing result obtained by the secure chip processing the computing task request included in a fourth task set, and the fourth task set is received by the secure chip from the secure computing module in an eighth period, where the eighth period is a period previous to the sixth period.
12. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the method according to any one of claims 1-9.
13. A secure computing module, comprising:
a memory having a computer program stored thereon;
a processor for executing the computer program in the memory to implement the steps of the method of any one of claims 1-5.
14. A security chip, comprising:
a memory having a computer program stored thereon;
a processor for executing the computer program in the memory to carry out the steps of the method of any one of claims 6-9.
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