CN111475436A - Embedded high-speed SATA storage array system based on PCIE switching network - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses an embedded high-speed SATA storage array system based on a PCIE switching network, which belongs to the technical field of SATA storage arrays and comprises a disk array module, an exchange module, a high-speed data sorting module and a file management module, wherein disks of the array are connected to a PCIE switch through a PCIE-SATA conversion chip to provide a storage medium, the exchange module consists of a high-speed PCIE switch and provides a data exchange function for an FPGA, a CPU and an SATA disk, the high-speed data sorting module consists of the FPGA and caches high-speed data in a DDR buffer area, and the file management module uses an L inux operating system and an EXT4 file system to provide a uniform file read-write interface for a user.
Description
Technical Field
The invention relates to an embedded storage array, in particular to an embedded high-speed SATA storage array system based on a PCIE switching network, and belongs to the technical field of embedded storage.
Background
In an embedded storage system, the embedded storage system is limited by a plurality of conditions, typical limited conditions are power consumption requirements, area requirements, performance requirements, temperature requirements and the like, under limited power consumption, the frequency of a CPU is low, the computing capability is weak, the throughput of a memory bandwidth is small, and the bandwidth of a high-speed interface of the CPU is also small, but a plurality of application scenarios (such as high-speed AD data and scout data of radar echoes) need a very high storage bandwidth, and the concurrent storage usually exceeds 1GB/S, even 5-6 GB/S, which provides a great challenge for the embedded storage system.
In order to meet the requirement of the storage system with high bandwidth and low power consumption, a common processing scheme is that an FPGA is used as a storage controller, after the FPGA arranges data, the FPGA directly uses an SATA IP core to control a SATA disk and write the data into the disk, and meanwhile, the FPGA needs to perform self-defined simple file management, a block diagram of a system for controlling a disk array by the FPGA in the prior art is provided in an attached figure 1 of the specification, and the working steps of the system are as follows:
step 1: the high-speed AD data are sent to the FPGA through a high-speed interface GTX of the FPGA, and the FPGA caches the data in the DDR memory;
step 2: the FPGA arranges data in a DDR memory, then divides the data, and writes the data into the SATA disk array in parallel through a SATA ip core;
and step 3: and the CPU is interacted to realize simple file management and other functions.
The system architecture can realize high-bandwidth storage by means of parallel access to disks, but has many defects, and the main defects are as follows:
1. the access protocol of the FPGA to realize the SATA is complex;
2. the FPGA needs to realize read-write strip management of a multi-disk array and a simple file system, and is relatively complex;
3. the flexibility is poor, disks are increased and decreased, the size of a strip is changed, and the like, logic codes need to be modified, so that the stability is not easy;
4. the FPGA can only process high-speed data from a high-speed interface, the size of the data block is determined, and for the mixture of large data blocks and small data blocks, the data block not only comes from the large data blocks of the high-speed data connected with the FPGA, but also comes from scenes similar to the small data with the uncertain size of the CPU and cannot be used;
5. the data management and the simple file management of the FPGA are not good, and the universality is poor;
6. the PC accesses the files on the storage array and can only access the files through a special interface and a special application program;
7. because the FPGA realizes a simple file system, the FPGA is incompatible with a general file system, cannot be accessed through a network file system and a browser of WINDOWS or L INUX on a PC, and can only use an application specially customized by a storage system manufacturer to access data;
8. database systems cannot be used, and due to the use of custom stripes and simple file management, common database systems such as mysql, oracle and the like cannot be used.
The general processing mode of the existing storage system is that a CPU is taken as a center, and the read-write steps of control data are as follows:
1. the FPGA receives the data, arranges the data into data blocks and informs the CPU;
2. the CPU copies data to a CPU memory through PCIE/SRIO and other high-speed interfaces;
3. the CPU controls the file system to write the data in the memory into the disk array.
Such a work procedure requires a high-performance CPU, a high-speed access interface with sufficient bandwidth, and particularly, a CPU memory bandwidth with sufficient bandwidth to realize high-speed storage. For example, a PCIE data transmission channel between the FPGA and the CPU needs at least a specification of PCIE3.0x8 to satisfy a 5GB/S storage rate, a serdes frequency of each lane of PCIE3.0 is 8Gbps, a total bandwidth of 8 lanes is 8GB/S, and removing protocol coding efficiency and transmission efficiency loss, the transmission rate of 5GB/S can be basically satisfied, a memory bandwidth of the CPU needs at least an effective bandwidth of 10GB/S, because an incoming data rate of 5GB/S and a read of a write disk also need at least a bandwidth of 5GB/S, and an overhead of CPU software itself inevitably exceeds a bandwidth of 10 GB/S.
Similarly, the CPU needs at least two PCIE3.0x8 high-speed interfaces, and now, embedded CPUs rarely have interfaces that can achieve an effective memory bandwidth of 10GB/S and at least 2 PCIE3.0x8 interfaces, and also keep low power consumption and severe environmental adaptability, which is a main reason why a conventional FPGA is used to control a storage system, and preferentially ensure high bandwidth, sacrifice flexibility and robustness.
The other common solution is realized by using a high-performance x86 CPU, and the x86 solution has the disadvantages of high power consumption, low localization rate, and small working temperature adaptation range, and cannot be used in some severe working environments, such as military requirements of-55 to +85 degrees.
In order to solve the above problems, the present invention provides an embedded high-speed SATA storage array system based on a PCIE switch network to optimize the above problems.
Disclosure of Invention
The main purpose of the present invention is to provide an embedded high-speed SATA storage array system based on PCIE switching network, which solves the disadvantages of poor versatility, poor stability, and difficult maintenance of the original system while ensuring the original high bandwidth.
The purpose of the invention can be achieved by adopting the following technical scheme:
an embedded high-speed SATA storage array system based on a PCIE switching network comprises a disk array module, a switching module, a high-speed data sorting module and a file management module, wherein the system structure is shown in an appendix figure 2;
a disk array module: the system comprises a PCIE-SATA conversion chip and disks, wherein a plurality of the combinations form a disk array, and the disks of the array are connected to a switch through a PCIE interface to provide a storage medium;
a switching module: the system consists of a high-speed PCIE switchboard which provides data exchange functions for an FPGA, a CPU and an SATA disk;
a high-speed data sorting module: the system comprises an FPGA (field programmable gate array), wherein high-speed data enters the FPGA through interfaces such as a plurality of paths of GTX (global system for X) and SRIO (serial peripheral input/output) interfaces, and the FPGA caches the data in a DDR (double data rate) buffer area;
the file management module is composed of a CPU, wherein an L inux operating system is operated on the file management module, the file system uses EXT 4. big data cached by a DDR in the high-speed data sorting module and small data such as network/serial ports from the CPU and the like are all uniformly subjected to file management and disk read-write management by the file management module.
The disk array module is composed of 5 SATA3.0 M.2 disks, the speed is 6Gbps, each disk is connected with a PCIE-SATA conversion chip, MARVE LL 88SE9200, the PCIE interface of 88SE9200 is PICE2.0x2, the interface bandwidth can reach 10Gbps, and MARVE LL 88SE9200 is connected to a PCIE exchanger PEX8734 through the PCIE interface.
The switching module is that the PCIE switch PEX8734 is an 8-port switch, 32L anes, supports the PCIE3.0 protocol, the speed of each L ane port can reach 8Gbps, the PEX8734 and each disk use PCIE2.02x ports, totally uses 5 ports, uses one PCIE2.04x port with the CPU P1022, and uses a PCIE3.04x port with the FPGA.
A high-speed data sorting module: the FPGA uses XC7K325T of Sailing and a 5-path 1x high-speed Rokey IO interface for external sensors to transmit data to the FPGA. The FPGA is also provided with a PCIE3.0x 4 interface connected with the PCIE switchboard, and the FPGA is also connected with a 512MB DDR3 memory.
The file sorting module uses a PPC P1022 CPU with low power consumption, a linux 2.6.4 kernel is operated on the CPU, and 5 disks form a disk array by using a soft raid function of L inux.
The embedded high-speed SATA storage array system based on the PCIE switching network comprises the following working steps:
step 1: the FPGA receives the data, arranges the data into data blocks and informs the CPU;
step 2: the SATA drive of the CPU constructs FIS access descriptors of a plurality of disks according to the stripe division of the disks, but the physical address of the data is the data buffering PCIE address of the FPGA and is not the memory address of the CPU;
and step 3: the CPU triggers the disks in the array to perform write operation, and the disks access data in the FPGA according to respective FIS descriptors;
and 4, step 4: after the transmission of each disk is finished, the CPU updates the file information.
The invention has the beneficial technical effects that:
the embedded high-speed SATA storage array system based on the PCIE switching network provided by the invention utilizes the switch characteristic of PCIE and uses the transmission technology from EP to finish the transmission of high-speed data from FPGA cache to disk array directly, and simultaneously uses CPU to manage files, and the system can manage the data in a standard file mode regardless of the size by modifying and improving SATA driving program and file system. The invention solves the defect of the prior disk management based on FPGA management, not only considers high-speed data storage, but also considers generalization and flexibility, and because the variable parts are processed by the software of the CPU, the adjustment is convenient, the code reusability is very strong, the reliability and the flexibility of the project are ensured.
Drawings
FIG. 1 is a prior art FPGA controlled disk array;
fig. 2 is a diagram of a PCIE switch based SATA storage array system according to a preferred embodiment of a PCIE switch network based embedded high-speed SATA storage array system according to the present invention;
fig. 3 is a system diagram of the working steps of a PCIE switch-based SATA storage array in accordance with a preferred embodiment of a PCIE switch network-based embedded high-speed SATA storage array system in accordance with the present invention;
FIG. 4 is a PCIE SATA project basic schematic diagram of a preferred embodiment of an embedded high-speed SATA storage array system based on a PCIE switching network according to the present invention;
FIG. 5 is a block diagram of a RAID module according to a preferred embodiment of a PCIE switching network based embedded high speed SATA storage array system in accordance with the present invention;
FIG. 6 is a block diagram of a preferred embodiment of an embedded high-speed SATA storage array system in accordance with the present invention;
FIG. 7 is a block diagram of a data consolidation module of a preferred embodiment of an embedded high-speed SATA storage array system based on a PCIE switching network in accordance with the present invention;
FIG. 8 is a block diagram of a file management module of a preferred embodiment of a PCIE switching network based embedded high speed SATA storage array system in accordance with the present invention;
fig. 9 is a diagram of SATA drivers in an embodiment of an embedded high-speed SATA storage array system based on a PCIE switch network according to the present invention.
Detailed Description
In order to make the technical solutions of the present invention more clear and definite for those skilled in the art, the present invention is further described in detail below with reference to the examples and the accompanying drawings, but the embodiments of the present invention are not limited thereto.
As shown in fig. 1 to fig. 9, an embedded high-speed SATA storage array system based on a PCIE switching network according to this embodiment includes a disk array module, an exchange module, a high-speed data sorting module, and a file management module;
a disk array module: the system comprises a PCIE-SATA conversion chip and disks, wherein a plurality of the combinations form a disk array, and the disks of the array are connected to a switch through a PCIE interface to provide a storage medium;
a switching module: the system consists of a high-speed PCIE switchboard which provides data exchange functions for an FPGA, a CPU and an SATA disk;
a high-speed data sorting module: the system comprises an FPGA (field programmable gate array), wherein high-speed data enters the FPGA through interfaces such as a plurality of paths of GTX (global system for X) and SRIO (serial peripheral input/output) interfaces, and the FPGA caches the data in a DDR (double data rate) buffer area;
the file management module is composed of a CPU, an L inux operating system is operated on the file management module, the file system uses EXT 4. the big data cached by DDR in the high-speed data sorting module and the network/serial port small data from the CPU are all subjected to file management and disk read-write management by the module.
The method has the advantages that the transmission of high-speed data from the FPGA cache to the disk array is completed by utilizing the switch characteristic of PCIE and using the transmission technology from EP to EP, meanwhile, the CPU is used for file management, and the SATA driving program and the file system are modified and improved, so that the system can be managed in a standard file mode regardless of the size of the data. The invention solves the defect of the prior disk management based on FPGA management, not only considers high-speed data storage, but also considers generalization and flexibility, and because the variable parts are processed by the software of the CPU, the adjustment is convenient, the code reusability is very strong, the reliability and the flexibility of the project are ensured. As shown in the following table:
the table shows that the defects of the conventional FPGA control disk array are basically well solved.
In this embodiment, the disk array module is composed of 5 m.2 disks of SATA3.0, the speed is 6Gbps, each disk is connected to a PCIE-SATA conversion chip, MARVE LL 88SE9200, a PCIE interface of 88SE9200 is pice2.0x2, and the interface bandwidth can reach 10Gbps, so that the peak requirement of SATA3.0 is completely met, MARVE LL 88SE9200 is further connected to PCIE switch PEX8734 through a PCIE interface, each disk becomes a PCIE EP device, and the CPU and the FPGA can access each disk in the disk array through the PCIE switch.
In this embodiment, the switch module is a PCIE switch PEX8734, which is an 8-port switch, 32L anes, and supports a PCIE3.0 protocol, the rate of each L ane port can reach 8Gbps, the PEX8734 and each disk use PCIE2.02x ports, and use 5 ports in total, the CPU P1022 uses a PCIE2.04x port, and the FPGA uses PCIE3.04x ports, and from the viewpoint of data flow, each port can meet the full rate requirement of 5 disks, and can reach a peak rate of about 2 GB/S.
In this embodiment, the high-speed data sorting module and the FPGA use the XC7K325T of saint and the 5-way 1x high-speed roeket IO interface for the external sensor to transmit data to the FPGA. The FPGA is also connected with a PCIE3.0x 4 interface and a PCIE switch, so that the throughput bandwidth of 4GB/S can be provided, the FPGA is also connected with a 512MB DDR3 memory for sorting and buffering data received from multiple RIOs, when the buffered data reach the appointed data volume, the FPGA interrupts a CPU, the CPU constructs an SATA descriptor according to the address of the data buffer, divides data blocks to each disk in the disk array, then starts disk access, and enables a controller of the disk to directly access the data buffer area of the FPGA through the PCIE switch and the PCIE interface of the FPGA.
In this embodiment, as shown in fig. 9, the filing module uses a PPC P1022 CPU with low power consumption, the linux 2.6.4 kernel is used, the soft raid function of L INUX is used to combine 5 disks into a disk array, and meanwhile, the SATA driver under L INUX is modified to modify the command descriptor of SATA.
When the large Data of the FPGA is written, the Data Base Address in the command descriptor is changed into a PCIE physical Address of a buffer area corresponding to the FPGA instead of a CPU memory used for file management or small Data, and the physical memory Address of the CPU is directly used, so that the effective unified management of the large Data, the small Data, the file system management Data and the real Data can be considered.
On the basis, a samba system based on L INUX is also constructed on the system, the disk array is used as a network disk, and through a P1022 network port, an upper computer PC can directly use a browser to read, write, delete and the like the files of the network disk, so that the operation is very convenient, which cannot be realized by the original FPGA-based control disk system.
Using the above real system, we performed a rate test: the write rate of the disk array consisting of 5 disks can reach about 2GB/S, and the embedded system can meet the requirements of a plurality of harsh environments. Meanwhile, the system can also be provided with a database system, and the following table shows the query performance of the test when the sqlite 3.0 is used on the storage board card and the PC is used as a query terminal:
query performance (custom watch)
The system can also change PCIE switches, FPGA/CPU models and the like according to other requirements to increase/reduce the bandwidth, effectively control the power consumption and balance the performance and the power consumption. After the changes, the software flow and the software system are basically not changed, which is beneficial to the technology accumulation and the robustness of the project.
In this embodiment, the operating steps of the PCIE switching network-based embedded high-speed SATA storage array system are as follows:
step 1: the FPGA receives the data, arranges the data into data blocks and informs the CPU;
step 2: the SATA drive of the CPU constructs FIS access descriptors of a plurality of disks according to the strip division of the disks, but the physical address of the data is the data buffer address of the FPGA and not the memory address of the CPU;
and step 3: the CPU triggers the magnetic disks in the array to carry out write operation, and the magnetic disks access data in the FPGA according to respective FIS descriptors;
and 4, step 4: after the transmission of each disk is finished, the CPU updates the file information.
The above description is only for the purpose of illustrating the present invention and is not intended to limit the scope of the present invention, and any person skilled in the art can substitute or change the technical solution of the present invention and its conception within the scope of the present invention.
Claims (6)
1. An embedded high-speed SATA storage array system based on PCIE switching network is characterized in that: the system comprises a disk array module, an exchange module, a high-speed data sorting module and a file management module;
a disk array module: the system comprises a PCIE-SATA conversion chip and disks, wherein a plurality of the combinations form a disk array, and the disks of the array are connected to a switch through a PCIE interface to provide a storage medium;
a switching module: the system consists of a high-speed PCIE switchboard which provides data exchange functions for an FPGA, a CPU and an SATA disk;
a high-speed data sorting module: the system comprises an FPGA (field programmable gate array), wherein high-speed data enters the FPGA through interfaces such as a plurality of paths of GTX (global system for X) and SRIO (serial peripheral input/output) interfaces, and the FPGA caches the data in a DDR (double data rate) buffer area;
the file management module is composed of a CPU, an L inux operating system is operated on the file management module, the file system uses EXT 4. the big data cached by DDR in the high-speed data sorting module and the network/serial port small data from the CPU are all subjected to file management and disk read-write management by the module.
2. The embedded high-speed SATA storage array system as recited in claim 1, wherein the RAID module comprises 5 disks of M.2 structure with SATA3.0 at 6Gbps, each disk is connected to a PCIE-SATA conversion chip, MARVE LL 88SE9200, the PCIE interface of 88SE9200 is PICE2.0x2, the interface bandwidth can reach 10Gbps, and MARVE LL 88SE9200 is connected to the PCIE switch PEX8734 through the PCIE interface.
3. The embedded high-speed SATA storage array system as recited in claim 1, wherein the switch module is a PCIE switch PEX8734 which is an 8 port switch 32L anes, supporting PCIE3.0 protocol, the rate of each L ane port can reach 8Gbps, the PEX8734 and each disk use PCIE2.02x ports, there are 5 ports in total, one PCIE2.04x port is used with CPU P1022, and PCIE3.04x port is used with FPGA.
4. The embedded high-speed SATA storage array system according to claim 1, wherein: and the FPGA uses XC7K325T of the Serpentine and a 5-path 1x high-speed Rokey IO interface for transmitting data to the FPGA by an external sensor. The FPGA is also provided with a PCIE3.0x 4 interface connected with the PCIE switchboard, and the FPGA is also connected with a 512MB DDR3 memory.
5. The embedded high-speed SATA storage array system as recited in claim 1, wherein the filer module uses a PPC P1022 CPU with low power consumption, and the Linux 2.6.4 kernel is used, and 5 disks are combined into a disk array using the soft raid function of L inux.
6. The embedded high-speed SATA storage array system according to claim 1, wherein: the embedded high-speed SATA storage array system based on the PCIE switching network comprises the following working steps:
step 1: the FPGA receives the data, arranges the data into data blocks and informs the CPU;
step 2: the SATA drive of the CPU constructs FIS access descriptors of a plurality of disks according to the strip division of the disks, but the physical address of the data is the data buffer address of the FPGA and not the memory address of the CPU;
and step 3: the CPU triggers the magnetic disks in the array to carry out write operation, and the magnetic disks access data in the FPGA according to respective FIS descriptors;
and 4, step 4: after the transmission of each disk is finished, the CPU updates the file information.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112667165A (en) * | 2020-12-29 | 2021-04-16 | 湖南博匠信息科技有限公司 | Data storage system and data storage method thereof |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
| CN113254289A (en) * | 2021-06-11 | 2021-08-13 | 武汉卓目科技有限公司 | Single machine testing method, device and system based on NVMe disk array |
| CN114579055A (en) * | 2022-03-07 | 2022-06-03 | 重庆紫光华山智安科技有限公司 | Disk storage method, device, equipment and medium |
| CN116303185A (en) * | 2023-05-18 | 2023-06-23 | 合肥埃科光电科技股份有限公司 | PCIE 4.0-based image acquisition card and image acquisition system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652752A (en) * | 2006-07-24 | 2010-02-17 | 马维尔国际贸易有限公司 | File server for redundant array of independent disks (RAID) system |
| CN102438116A (en) * | 2011-08-17 | 2012-05-02 | 中国科学院光电技术研究所 | Embedded type Linux system-based high-speed image recording device |
| US20120110397A1 (en) * | 2010-10-29 | 2012-05-03 | Kabushiki Kaisha Toshiba | Data transmission system, storage medium and data transmission program |
| CN202979164U (en) * | 2012-12-25 | 2013-06-05 | 四川赛狄信息技术有限公司 | Embedded image recorder |
| CN103281260A (en) * | 2013-05-20 | 2013-09-04 | 华为技术有限公司 | System and device supporting PCIe (peripheral component interface express) and resource allocation method thereof |
| US20160092328A1 (en) * | 2014-09-30 | 2016-03-31 | Neosem Inc. | Memory device test apparatus and method |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
-
2020
- 2020-04-07 CN CN202010263437.XA patent/CN111475436A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652752A (en) * | 2006-07-24 | 2010-02-17 | 马维尔国际贸易有限公司 | File server for redundant array of independent disks (RAID) system |
| US20120110397A1 (en) * | 2010-10-29 | 2012-05-03 | Kabushiki Kaisha Toshiba | Data transmission system, storage medium and data transmission program |
| CN102438116A (en) * | 2011-08-17 | 2012-05-02 | 中国科学院光电技术研究所 | Embedded type Linux system-based high-speed image recording device |
| CN202979164U (en) * | 2012-12-25 | 2013-06-05 | 四川赛狄信息技术有限公司 | Embedded image recorder |
| CN103281260A (en) * | 2013-05-20 | 2013-09-04 | 华为技术有限公司 | System and device supporting PCIe (peripheral component interface express) and resource allocation method thereof |
| US20160092328A1 (en) * | 2014-09-30 | 2016-03-31 | Neosem Inc. | Memory device test apparatus and method |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 刘劲松: "关于存储系统性能的测试、仿真与评价的研究", 《中国优秀博硕士学位论文全文数据库（博士）信息科技辑》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112667165A (en) * | 2020-12-29 | 2021-04-16 | 湖南博匠信息科技有限公司 | Data storage system and data storage method thereof |
| CN112667165B (en) * | 2020-12-29 | 2023-11-17 | 湖南博匠信息科技有限公司 | Data storage system and data storage method thereof |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
| CN113254289A (en) * | 2021-06-11 | 2021-08-13 | 武汉卓目科技有限公司 | Single machine testing method, device and system based on NVMe disk array |
| CN114579055A (en) * | 2022-03-07 | 2022-06-03 | 重庆紫光华山智安科技有限公司 | Disk storage method, device, equipment and medium |
| CN116303185A (en) * | 2023-05-18 | 2023-06-23 | 合肥埃科光电科技股份有限公司 | PCIE 4.0-based image acquisition card and image acquisition system |
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