CN111464447B - Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips - Google Patents
Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips Download PDFInfo
- Publication number
- CN111464447B CN111464447B CN202010277056.7A CN202010277056A CN111464447B CN 111464447 B CN111464447 B CN 111464447B CN 202010277056 A CN202010277056 A CN 202010277056A CN 111464447 B CN111464447 B CN 111464447B
- Authority
- CN
- China
- Prior art keywords
- core
- processing
- working
- module
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention discloses a method and a device for synchronizing forwarding tables of an ultra-high bandwidth multi-core Ethernet switching chip, wherein the method comprises the steps of configuring a main working core and a slave working core; establishing an inter-core communication interface between the master working core and the slave working core; the main working core receives a self processing request and writes a processing result into the core, and simultaneously sends the processing result to the slave working core, and the slave working core writes information into the core; the slave working core receives a self processing request and sends the processing request to the master working core, the master working core writes a processing result into the self core and sends the processing result to the slave working core, and the slave working core writes information into the self core; and the main working core carries out item synchronization according to a preset period. The invention effectively solves the problem of interoperation of two cores on one package, so that the external system behavior of the multi-core Ethernet switch chip is the same as that of a single core.
Description
Technical Field
The invention belongs to the technical field of network communication, and particularly relates to a method and a device for synchronizing forwarding tables of an ultra-bandwidth multi-core Ethernet switching chip.
Background
With the development of super-large scale cloud networks, storage networks, and HPC (High Performance Computing) scenarios, the data exchange volume on the networks is increasing, and the single-chip processing capability is increasing continuously, from Gbps to Tbps magnitude. The current chip production process usually adopts 14nm/12nm or 7nm/6nm, the highest running clock frequency of an intellectual property core (IP core) can reach 1.05GHz or 1.7GHz, and the processing capacity of 25.6Tbps can not be supported on the premise of a single production line core. In order to cope with the rapidly rising message processing bandwidth, under the condition that the clock frequency of a single core is limited, the multi-core design becomes the development direction of chip design, and the system behavior exhibited by the chip during operation should not sense whether the chip architecture is a single-core design or a multi-core design, and the states among a plurality of cores must be synchronized.
With the progress of the production process, Tape Out (Tape Out) cost is also correspondingly higher and higher, in order to enrich product lines, high-bandwidth and ultra-high-bandwidth chips need to be designed, and by using a D2D (Die-to-Die, Die interconnection) technology, a single Tape can cover multiple product lines, that is, an ultra-high-bandwidth chip is packaged by two Die, and a high-bandwidth chip is packaged by one Die, on the premise of a dual-core design.
When the switch chip is packaged by interconnecting two dies, the switch chip needs the two dies to work cooperatively to achieve information synchronization of the two cores, however, how the two cores perform interactive operation on one package is a problem that needs to be solved urgently.
Disclosure of Invention
In view of the above, the present invention provides a method and an apparatus for synchronizing forwarding tables of an ultra-high bandwidth multi-core ethernet switching chip.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions: a method for synchronizing forwarding tables of an ultra-high bandwidth multi-core Ethernet switching chip, the Ethernet switching chip comprising a first core and a second core, the method comprising the steps of:
s100, configuring a first core or a second core as a main working core, and configuring the other core as a slave working core;
s200, establishing an inter-core communication interface between the master working core and the slave working core;
s300, the main working core receives a self processing request and performs information processing, a processing result is written into the self core, the processing result is sent to the slave working core through the inter-core communication interface, and the slave working core writes information into the self core;
the slave working core receives a self processing request and sends the processing request to the master working core through the inter-core communication interface, the master working core processes information and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core through the inter-core communication interface, and the slave working core writes the information into the self core;
s400, the main working core scans and reads the forwarding information table item by item according to a preset period, informs the address and the content of the current item to the slave working core, writes the content of the current item into the same address after the slave working core receives the message, and carries out item synchronization again in the next period if the current message is discarded due to errors.
Preferably, the master working core does not delay sending information out until it receives available information from the working core by more than 100 clock cycles.
Preferably, the master working core includes a first message processing module for processing a message through an information table maintained by the master working core and a first core interaction module for interaction between cores, the slave working core includes a second message processing module for processing a message through an information table maintained by the slave working core and a second core interaction module for interaction between cores, and the first core interaction module is connected to the second core interaction module through the inter-core communication interface.
Preferably, the first core interaction module receives the processing request from the first message processing module and performs information processing, writes the processing result into the first message processing module, and simultaneously sends the information to the second core interaction module through the inter-core communication interface, and the second core interaction module writes the information into the second message processing module.
Preferably, the second core interaction module receives a processing request from the second message processing module, and sends the processing request to the first core interaction module through the inter-core communication interface, the first core interaction module performs information processing and writes a processing result into the first message processing module, and simultaneously sends the processing result to the second core interaction module through the inter-core communication interface, and the second core interaction module writes information into the second message processing module.
The invention also discloses a device for synchronizing the forwarding table of the ultra-high bandwidth multi-core Ethernet switching chip, wherein the Ethernet switching chip comprises a first core and a second core, and the device is characterized by comprising a configuration module and an interface module, wherein the configuration module configures the first core or the second core as a main working core, the other core is a slave working core, the interface module establishes an inter-core communication interface between the main working core and the slave working core, the main working core receives the processing request of the main working core and processes information, the processing result is written into the core, and the processing result is sent to the slave working core through the inter-core communication interface, and the slave working core writes the information into the core; and the slave working core receives a self processing request and sends the processing request to the master working core through the inter-core communication interface, the master working core processes information and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core through the inter-core communication interface, and the slave working core writes the information into the self core.
Preferably, the master working core does not delay sending information out until it receives available information from the working core by more than 100 clock cycles.
Preferably, the master working core includes a first message processing module for processing a message through an information table maintained by the master working core and a first core interaction module for interaction between cores, the slave working core includes a second message processing module for processing a message through an information table maintained by the slave working core and a second core interaction module for interaction between cores, and the first core interaction module is connected to the second core interaction module through the inter-core communication interface.
The invention has the following beneficial effects:
the invention effectively solves the problem of interoperation of two cores on one package, namely the problem of synchronization of forwarding tables, so that the external system behavior of the multi-core Ethernet switching chip is the same as that of a single core. Meanwhile, the limitation that a high-cost error-free communication interface must be used by a synchronous interface is changed, and the chip cost is greatly reduced by using a low-cost error-free inter-core communication interface.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a multi-core Ethernet switch chip;
fig. 2 is a schematic diagram of a flow chart of a method for synchronizing forwarding tables of a multi-core ethernet switching chip.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, which is a schematic structural diagram of a multi-core ethernet switching chip, the multi-core ethernet switching chip includes a first core and a second core, where the first core includes a first message processing module and a first core interaction module, the second core includes a second message processing module and a second core interaction module, the first message processing module is configured to process a message through an information table maintained by the first message processing module, the information table may be configured through an external CPU or maintained through the first core interaction module, and similarly, the second message processing module is configured to process a message through an information table maintained by the second message processing module, and the information table may be configured through an external CPU or maintained through the second core interaction module; the first core interaction module and the second core interaction module are used for interaction between cores.
Referring to fig. 1 and fig. 2, a method for synchronizing forwarding tables of an ultra-high bandwidth multi-core ethernet switching chip disclosed in the present invention includes the following steps:
s100, configuring a first core or a second core as a main working core, and configuring the other core as a slave working core;
specifically, the ethernet switch chip needs to maintain message processing information during message processing, some message processing information in the multi-core ethernet switch chip may be maintained inside the core, some message processing information needs to be maintained globally, and the message processing information needing to be maintained globally needs to satisfy consistency, so that the two cores need to allocate roles to process the information, that is, when the two cores work cooperatively, a certain core needs to be configured as a master work core, the other core needs to be a slave work core, for example, the first core is configured as the master work core, the second core is a slave work core, or the first core is configured as the slave work core, the second core is the master work core, and the setting may be performed according to actual requirements. If the main working core and the slave working core are not configured, errors are easy to occur, for example, for ethernet two-layer forwarding, the first message processing module performs message forwarding processing by querying an FDB (Forward Database, forwarding information table) maintained by the first message processing module, and if corresponding message processing information is not queried in the FDB maintained by the first message processing module, the first core interaction module needs to be informed to perform FDB entry learning operation, and finally, a learning result is fed back to the first message processing module, and the first message processing module adds the learning result to the FDB of the first message processing module for subsequent message processing. For a single-core ethernet switch chip, that is, for an ethernet switch chip including only a first core, adding a learning result in an FDB table will not cause an error, but for a dual-core ethernet switch chip, if a packet is processed from a first packet processing module of the first core and triggers an FDB table entry learning operation, a learning request is sent to a first core interaction module, the first core interaction module sends the learning result to a first packet processing module and a second packet processing module of a second core at the same time, if the second core interaction module of the second core also sends the learning request sent by the second packet processing module and sends the learning result out, a collision may occur with the result of the first core, for example, when the FDB is stored in a Hash (Hash) mode, a position collision may occur when two learning results are written. Therefore, the master working core and the slave working core are arranged when the two cores work together, and the error can be avoided.
In this embodiment, a first core interaction module of a first core is configured as a Master working mode (Master), the first core is configured as a Master working core, and a second core interaction module of a second core is configured as a Slave working mode (Slave), and the second core is configured as a Slave working core.
S200, establishing an inter-core communication interface between the master working core and the slave working core;
specifically, after the master work core and the slave work core are configured, the slave work core needs to send a processing request to the master work core, and execute a corresponding operation under the instruction of the master work core. In order to enable the master working core and the slave working core to complete an interaction process, a group of inter-core communication interfaces are required to be established between the first core and the second core, and the inter-core communication interfaces are used for sending one part of information of the master working core to the slave working core and sending one part of information of the slave working core to the master working core in each clock cycle, namely, transmitting the information between the cores. The inter-core communication interface allows errors to be generated when communicating and has n bits, n depending on the size of the information to be communicated.
In order to prevent the forwarding performance from being lost, the time delay from the sending of the information by the master working core to the receiving of the available information by the slave working core is not more than 100 clock cycles, preferably 20 clock cycles, and of course, the time delay can be set according to the actual requirement.
S300, the main working core receives a self processing request and performs information processing, a processing result is written into the self core, the processing result is sent to the slave working core through the inter-core communication interface, and the slave working core writes information into the self core;
and the slave working core receives a self processing request and sends the processing request to the master working core through the inter-core communication interface, the master working core processes information and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core through the inter-core communication interface, and the slave working core writes the information into the self core.
Specifically, the first core interaction module receives a processing request from the first message processing module and performs information processing, and further writes a processing result into the first message processing module, and simultaneously sends the processing result to the second core interaction module through the inter-core communication interface, and the second core interaction module further writes the processing result into the second message processing module; and the second core interaction module receives the processing request from the second message processing module and sends the processing request to the first core interaction module through the inter-core communication interface, the first core interaction module processes information and writes a processing result into the first message processing module, and meanwhile, sends the processing result to the second core interaction module through the inter-core communication interface, and the second core interaction module writes the processing result into the second message processing module.
S400, the main working core scans and reads the forwarding information table item by item according to a preset period, informs the address and the content of the current item to the slave working core, writes the content of the current item into the same address after the slave working core receives the message, and carries out item synchronization again in the next period if the current message is discarded due to errors.
Specifically, since an error may occur in the inter-core communication interface, an error may occur in the interaction process between the master working core and the slave working core, which results in data inconsistency, for example, the master working core is responsible for aging the FDB, and it is determined that a certain forwarding entry needs to be aged, for example, entry a, and the entry is stored in a Hash table 0x8246 of the FDB. The first core interaction module sends a command of deleting 0x8246 of the Hash table to the first message interaction module, and the first message processing module further deletes the entry at the position of 0x8246 of the Hash table. The first core interaction module sends a command of deleting the Hash table 0x8246 to the second core interaction module, and the command is discarded due to an error interface, so that the second core interaction module does not inform the second message processing module of deleting the entry at the position of the Hash table 0x 8246.
If an interface on the second core receives a message at this time, the address of the message corresponds to the entry at the position of 0x8246, so that the entry at the position of 0x8246 no longer meets the aging condition. The second core interaction module sends an aging updating state message to the first core interaction module, and the first core interaction module updates the aging state of the same position of the first core interaction module. Because the second core interaction module needs a certain clock cycle to send a message to the first core interaction module, before the first core interaction module does not receive the aging update state message, the first core interaction module receives the learning request of the first message processing module, the Hash value corresponding to the learned address information is 0x8246, the first core interaction module informs the first message processing module to write a newly-learned forwarding entry at the position of 0x8246, the newly-learned forwarding entry is marked as an entry B, and simultaneously sends the message to the second core interaction module, and the second core interaction module informs the second message processing module to write the entry B at the position of 0x8246, but the message is discarded due to transmission errors.
Further, at this time, the first core interaction module receives the aging update status request, and if it is found that a valid entry does exist in the 0x8246 position, the aging status is updated normally. In the subsequent forwarding process, because the messages of the addresses corresponding to the entry a and the entry B are both forwarded normally, the entry B at the position of 0x8246 on the first core and the entry a at the position of 0x8246 on the second core will always remain, resulting in the phenomenon that the forwarding information of the first core is inconsistent with that of the second core.
The main working core scans and reads items of a forwarding information table in the first message processing module one by one according to a preset period, informs the slave working core of the address and the content of the current item, writes the content of the current item into the same address after receiving the message from the slave working core, and carries out item synchronization again in the next period if the current message is discarded due to errors. By means of the entry synchronization mode, the forwarding information table can be ensured to keep consistent data.
The invention also discloses a device for synchronizing the forwarding tables of the ultra-bandwidth multi-core Ethernet switching chip, wherein the Ethernet switching chip comprises a first core and a second core, and the device comprises a configuration module and an interface module, wherein the configuration module is used for configuring the first core or the second core as a main working core, and the other core is a slave working core; the interface module is used for establishing an inter-core communication interface between the main working core and the slave working core;
the main working core receives a self processing request and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core, and the slave working core writes information into the self core;
and the slave working core receives the own processing request and sends the processing request to the main working core through the inter-core communication interface, the main working core processes information and writes a processing result into the own core, and simultaneously sends the processing result to the slave working core, and the slave working core writes the information into the own core. Specifically, the configuration module may configure the first core as a master working core and the second core as a slave working core, or configure the first core as a slave working core and the second core as a master working core, and may be set according to actual requirements. In this embodiment, a first core interaction module of a first core is configured as a Master working mode (Master), the first core is configured as a Master working core, and a second core interaction module of a second core is configured as a Slave working mode (Slave), and the second core is configured as a Slave working core.
In order to enable the master working core and the slave working core to complete an interaction process, a group of inter-core communication interfaces are required to be established between the first core and the second core, and the inter-core communication interfaces are used for sending one part of information of the master working core to the slave working core and sending one part of information of the slave working core to the master working core in each clock cycle, namely, transmitting the information between the cores. The inter-core communication interface allows errors to be generated when communicating and has n bits, n depending on the size of the information to be communicated.
In order to prevent the forwarding performance from being lost, the time delay from the sending of the information by the master working core to the receiving of the available information by the slave working core is not more than 100 clock cycles, preferably 20 clock cycles, and of course, the time delay can be set according to the actual requirement.
The invention effectively solves the problem of interoperation of two cores on one package, namely the problem of synchronization of forwarding tables, so that the system behavior of alignment of a multi-core Ethernet switching chip is the same as that of a single core. Meanwhile, the limitation that a high-cost error-free communication interface must be used by a synchronous interface is changed, and the chip cost is greatly reduced by using a low-cost error-free inter-core communication interface.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the modules may be implemented in the same one or more software and/or hardware implementations in implementing one or more embodiments of the present description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
One or more embodiments of the present description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. A method for synchronizing forwarding tables of an ultra-high bandwidth multi-core Ethernet switch chip, wherein the Ethernet switch chip comprises a first core and a second core, the method comprising the steps of:
s100, configuring a first core or a second core as a main working core, and configuring the other core as a slave working core;
s200, establishing an inter-core communication interface between the master working core and the slave working core;
s300, the main working core receives a self processing request and performs information processing, a processing result is written into the self core, the processing result is sent to the slave working core through the inter-core communication interface, and the slave working core writes the processing result into the self core;
the slave working core receives a self processing request and sends the processing request to the master working core through the inter-core communication interface, the master working core processes information and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core through the inter-core communication interface, and the slave working core writes the processing result into the self core;
s400, the main working core scans and reads the forwarding information table item by item according to a preset period, informs the address and the content of the current item to the slave working core, writes the content of the current item into the same address after the slave working core receives the message, and carries out item synchronization again in the next period if the current message is discarded due to errors.
2. The method of claim 1, wherein the master worker core delays sending information out to receiving information available from the worker core by no more than 100 clock cycles.
3. The method according to claim 1, wherein the master working core includes a first message processing module for processing the message through the self-maintained information table and a first core interaction module for inter-core interaction, the slave working core includes a second message processing module for processing the message through the self-maintained information table and a second core interaction module for inter-core interaction, and the first core interaction module is connected to the second core interaction module through the inter-core communication interface.
4. The method according to claim 3, wherein the first core interaction module receives the processing request from the first message processing module and performs information processing, writes the processing result into the first message processing module, and simultaneously sends the processing result to the second core interaction module through the inter-core communication interface, and the second core interaction module writes the processing result into the second message processing module.
5. The method according to claim 3, wherein the second core interaction module receives a processing request from the second packet processing module and sends the processing request to the first core interaction module through the inter-core communication interface, the first core interaction module performs information processing and writes a processing result into the first packet processing module, and simultaneously sends the processing result to the second core interaction module through the inter-core communication interface, and the second core interaction module writes the processing result into the second packet processing module.
6. A device for synchronizing forwarding tables of an ultra-high bandwidth multi-core Ethernet switching chip comprises a first core and a second core, and is characterized in that the device comprises a configuration module and an interface module, wherein the configuration module configures the first core or the second core as a main working core, the other core is a slave working core, the interface module establishes an inter-core communication interface between the main working core and the slave working core, the main working core receives a self processing request and performs information processing, a processing result is written into the core, and meanwhile, the processing result is sent to the slave working core through the inter-core communication interface, and the slave working core writes the processing result into the core; and the slave working core receives a self processing request and sends the processing request to the master working core through the inter-core communication interface, the master working core processes information and writes a processing result into the self core, and simultaneously sends the processing result to the slave working core through the inter-core communication interface, and the slave working core writes the processing result into the self core.
7. The apparatus of claim 6, wherein the master worker core is configured to delay sending information out until it receives available information from a worker core by no more than 100 clock cycles.
8. The apparatus according to claim 6, wherein the master working core includes a first packet processing module for processing packets through the self-maintained information table and a first core interaction module for inter-core interaction, the slave working core includes a second packet processing module for processing packets through the self-maintained information table and a second core interaction module for inter-core interaction, and the first core interaction module is connected to the second core interaction module through the inter-core communication interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010277056.7A CN111464447B (en) | 2020-04-08 | 2020-04-08 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010277056.7A CN111464447B (en) | 2020-04-08 | 2020-04-08 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111464447A CN111464447A (en) | 2020-07-28 |
| CN111464447B true CN111464447B (en) | 2021-08-13 |
Family
ID=71681010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010277056.7A Active CN111464447B (en) | 2020-04-08 | 2020-04-08 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111464447B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022041158A1 (en) * | 2020-08-28 | 2022-03-03 | 华为技术有限公司 | Multi-chip packaging structure and switch |
| CN113364685B (en) * | 2021-05-17 | 2023-03-14 | 中国人民解放军国防科技大学 | Distributed MAC table item processing device and method |
| CN117472844B (en) * | 2023-12-27 | 2024-03-19 | 中诚华隆计算机技术有限公司 | Multi-chip module and data processing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105913119A (en) * | 2016-04-06 | 2016-08-31 | 中国科学院上海微系统与信息技术研究所 | Row-column interconnection heterogeneous multi-core brain-like chip and usage method for the same |
| CN106685826A (en) * | 2016-12-01 | 2017-05-17 | 瑞斯康达科技发展股份有限公司 | Interchanger stacking system, slave unit, switching chip and method for processing protocol message |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU4848799A (en) * | 1998-07-08 | 2000-02-01 | Broadcom Corporation | High performance self balancing low cost network switching architecture based ondistributed hierarchical shared memory |
| CN101217492A (en) * | 2008-01-04 | 2008-07-09 | 福建星网锐捷网络有限公司 | Address information processing method and device and system |
| CN101515890B (en) * | 2009-04-03 | 2012-09-05 | 中兴通讯股份有限公司 | Message encapsulating method and device thereof |
| US8843682B2 (en) * | 2010-05-18 | 2014-09-23 | Lsi Corporation | Hybrid address mutex mechanism for memory accesses in a network processor |
| CN101729410B (en) * | 2009-11-10 | 2012-06-06 | 中兴通讯股份有限公司 | Synchronization method and device of media access control (MAC) address table |
| CN101808091A (en) * | 2010-03-11 | 2010-08-18 | 中兴通讯股份有限公司 | Control method and control system for supporting data protocol protection |
| CN103559095B (en) * | 2013-10-30 | 2016-08-31 | 武汉烽火富华电气有限责任公司 | Method of data synchronization for the double-core multiple processor structure of relay protection field |
| CN104486117B (en) * | 2014-12-12 | 2018-04-06 | 上海斐讯数据通信技术有限公司 | A kind of the configuration order exchange method and system of more board core switch |
| CN104967579B (en) * | 2015-06-30 | 2018-04-06 | 上海斐讯数据通信技术有限公司 | Interchanger MAC address synchronizations method and system |
| CN108134855B (en) * | 2017-12-18 | 2021-03-09 | 东软集团股份有限公司 | ARP table management method, processor core, storage medium and electronic device |
-
2020
- 2020-04-08 CN CN202010277056.7A patent/CN111464447B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105913119A (en) * | 2016-04-06 | 2016-08-31 | 中国科学院上海微系统与信息技术研究所 | Row-column interconnection heterogeneous multi-core brain-like chip and usage method for the same |
| CN106685826A (en) * | 2016-12-01 | 2017-05-17 | 瑞斯康达科技发展股份有限公司 | Interchanger stacking system, slave unit, switching chip and method for processing protocol message |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111464447A (en) | 2020-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111464447B (en) | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips | |
| CN110262902B (en) | Information processing method and system, medium, and computing device | |
| CN112583931B (en) | Message processing method, message middleware, electronic device, and storage medium | |
| CN109376197B (en) | Data synchronization method, server and computer storage medium | |
| CN108804238B (en) | Soft bus communication method based on remote procedure call | |
| WO2022001417A1 (en) | Data transmission method, processor system, and memory access system | |
| WO2021147332A1 (en) | Information processing method, ethernet switching chip, and storage medium | |
| CN111585862A (en) | Method and device for realizing network intercommunication between EtherCAT and TSN | |
| CN111736867A (en) | FPGA updating device, method and storage medium | |
| CN114285695B (en) | Communication method, device, apparatus, system and storage medium | |
| CN114301995A (en) | Conversion switching and intercommunication fusion system and method of real-time industrial Ethernet protocol | |
| CN112052104A (en) | Message queue management method based on multi-computer-room realization and electronic equipment | |
| CN105357148A (en) | Method and system for preventing output message of network exchange chip from being disordered | |
| CN112153114A (en) | Method, system, equipment and medium for time-sharing access to shared device | |
| CN113691466A (en) | Data transmission method, intelligent network card, computing device and storage medium | |
| CN111343107B (en) | Information processing method, Ethernet switching chip and storage medium | |
| CN114915516A (en) | Communication method and device | |
| CN112751789A (en) | Method and system for realizing asymmetric SDN controller cluster | |
| CN106603188A (en) | Frequency converter interface device | |
| CN103870318A (en) | Non-symmetric-processing multi-core system and network device thereof | |
| CN113179228A (en) | Method, device, equipment and medium for improving switch stacking reliability | |
| CN102681881B (en) | Across machine dispatching method and system thereof | |
| CN107370652B (en) | Computer node dynamic interconnection platform and platform networking method | |
| WO2024103983A1 (en) | Distributed dispatch system deployment method, system and apparatus, distributed dispatch system dispatch method, system and apparatus, and medium | |
| CN116662037B (en) | Processing method and device for shared memory, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Shengke Communication Co.,Ltd. Address before: Unit 13 / 16, floor 4, building B, No. 5, Xinghan street, Suzhou Industrial Park, Suzhou, Jiangsu Province, 215000 Applicant before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |