CN111463187A - Flexible device based on system-in-package and manufacturing method thereof - Google Patents
Flexible device based on system-in-package and manufacturing method thereof Download PDFInfo
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- CN111463187A CN111463187A CN202010284723.4A CN202010284723A CN111463187A CN 111463187 A CN111463187 A CN 111463187A CN 202010284723 A CN202010284723 A CN 202010284723A CN 111463187 A CN111463187 A CN 111463187A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The present disclosure relates to a system-in-package based flexible device and a method of manufacturing the same. The device sequentially comprises a bottom substrate, a middle substrate and a packaging layer from bottom to top, wherein a bottom wire is arranged on the bottom substrate; the middle layer substrate is provided with a middle layer lead, a functional chip with pins connected with a bottom layer chip lead in the bottom layer lead is arranged in a chip mounting position on the middle layer substrate in an inverted mode, and an interlayer connecting lead used for connecting the middle layer lead and the bottom layer lead is arranged in a lead through hole on the middle layer substrate; the packaging layer is used for packaging the device, and a passive device with a pin connected with a passive device wire in the middle layer wire is arranged in a device groove on the packaging layer; the packaging layer is provided with a top pin and is connected with the middle layer wire through a pin connecting wire arranged in the pin wire through hole. The device and the method provided by the embodiment of the disclosure have the advantages of simple manufacturing process, good ductility and flexibility of the device, small size of the device, good reliability and better performance; the application range is wide.
Description
Technical Field
The present disclosure relates to the field of flexible electronic technologies, and in particular, to a system-in-package flexible device and a method for manufacturing the same.
Background
Since the flexible electronic device enters the field of vision of people, the flexible electronic device attracts extensive attention of the academic world due to the characteristics of portability, extensibility and convenient integration, and the flexible electronic device is rapidly developed. Compared with the traditional hard electronic device, the flexible electronic device has wider application range, can be applied to various curved surfaces including a human body and a flexible screen, and can meet the requirements of future demands on the electronic device.
In the related art, most of the Flexible electronic devices are produced on a Flexible printed circuit board (FPC), which inevitably limits the performance of the devices to the performance of the FPC, and thus is difficult to meet the development requirements of Flexible devices with miniaturization, rapidity and integration.
Disclosure of Invention
In view of the above, the present disclosure provides a system-in-package based flexible device and a method for manufacturing the same.
According to an aspect of the present disclosure, there is provided a system-in-package based flexible apparatus, the apparatus including:
the chip comprises a bottom substrate, wherein one surface of the bottom substrate is provided with a patterned bottom wire, and the bottom wire comprises a bottom chip wire;
the middle layer substrate is positioned above the bottom layer substrate and is contacted with the bottom layer lead, one surface of the middle layer substrate, which is far away from the bottom layer lead, is provided with a patterned middle layer lead, the middle layer lead comprises a passive device lead or a middle layer chip lead,
the middle layer substrate is provided with a lead through hole and at least one chip mounting position, the position of the chip mounting position corresponds to the position of the lead of the bottom layer chip, a functional chip is arranged in the chip mounting position in an inverted mode, a pin of the functional chip is connected with the lead of the bottom layer chip, an interlayer connecting lead is arranged in the lead through hole and used for realizing the connection of the middle layer lead and the bottom layer lead;
the packaging layer is used for packaging the device and is positioned above the middle layer substrate to be in contact with the middle layer lead, at least one device groove is formed in one surface, close to the middle layer lead, of the packaging layer, the position of the device groove corresponds to the position of the passive device lead, a passive device is installed in the device groove, and a pin of the passive device is connected with the passive device lead;
still be provided with pin wire through-hole in the encapsulation layer, keep away from on the encapsulation layer the one side of intermediate level wire is provided with the top pin of device, be provided with pin connecting wire in the pin wire through-hole, pin connecting wire is used for realizing the top pin with the connection of intermediate level wire, wherein, the bottom substrate the intermediate level substrate the material of encapsulation layer is flexible material.
For the above-described device, in one possible implementation, the bottom layer conductors further include bottom pins of the device,
the size of the middle layer substrate is smaller than that of the bottom layer substrate, and the part of the bottom layer lead which is not covered by the middle layer substrate is the bottom pin.
For the above-described device, in one possible implementation, the interlayer substrate comprises at least one layer,
wherein, when the interlayer substrate includes a first interlayer substrate and a second interlayer substrate, the interlayer wire includes a first wire and a second wire, the interlayer connection wire includes a first interlayer connection wire and a second interlayer connection wire, the wire through hole includes a first wire through hole and a second wire through hole, the chip mounting site includes a first chip mounting site and a second chip mounting site,
the first middle layer substrate is positioned above the bottom layer substrate and is contacted with the bottom layer lead, one surface of the first middle layer substrate, which is far away from the bottom layer substrate, is provided with a patterned first lead, the first lead comprises a middle layer chip lead,
the first interlayer substrate is provided with a first lead through hole and at least one first chip mounting position, the position of the first chip mounting position corresponds to the position of the lead of the bottom chip, a first functional chip is arranged in the first chip mounting position in a flip-chip mode, a pin of the first functional chip is connected with the lead of the bottom chip, and a first interlayer connecting lead is arranged in the first lead through hole;
the second interlayer substrate is positioned above the first interlayer substrate and is contacted with the first lead, a second lead through hole and at least one second chip mounting position are arranged on the second interlayer substrate, the position of the second chip mounting position corresponds to the position of the first chip lead, a second functional chip is arranged in the second chip mounting position in a flip manner, a pin of the second functional chip is connected with the first chip lead, and a second interlayer connecting lead is arranged in the second lead through hole,
a patterned second wire is arranged on one surface, far away from the first wire, of the second interlayer substrate, the second wire comprises a passive device wire, and the second interlayer connecting wire is used for realizing the connection of the second wire and the first wire;
the encapsulation layer is located over the second interlayer substrate in contact with the second conductive line.
For the above-described device, in one possible implementation, the shape of the bottom layer conductive lines and/or the middle layer conductive lines is a malleable shape, the malleable shape including any of a serpentine type and/or a fractal type.
For the above device, in one possible implementation, the thickness of the interlayer substrate is the same as the thickness of the functional chip.
For the above device, in one possible implementation, the thickness of the interlayer substrate is greater than the thickness of the functional chip,
the flip chip is arranged in the chip mounting position and is provided with a functional chip connected with the bottom chip through a wire, a filling layer is arranged above the functional chip, and one surface of the functional chip, which is far away from the filling layer, and one surface of the bottom wire, which is far away from the middle layer substrate, are on the same plane.
According to another aspect of the present disclosure, there is provided a method of manufacturing a system-in-package based flexible device, the method including:
depositing metal on a pre-prepared bottom substrate to obtain a bottom metal layer to be etched, and patterning the bottom metal layer to be etched to form a bottom lead, wherein the bottom lead comprises a bottom chip lead;
preparing a middle layer substrate on the bottom layer lead;
etching the middle layer substrate to form a lead through hole and at least one chip mounting position in the middle layer substrate, wherein the chip mounting position corresponds to the bottom layer chip lead;
installing a functional chip in a corresponding chip installation position by using a flip-chip process, wherein a pin of the functional chip is connected with the bottom chip through a wire;
depositing metal in the wire through hole of the interlayer substrate to form an interlayer connecting wire;
depositing metal on the middle layer substrate to obtain a middle layer metal layer to be etched, and patterning the middle layer metal layer to be etched to form a middle layer lead, wherein the middle layer lead comprises a passive device lead or a middle layer chip lead, and the middle layer connecting lead is used for realizing the connection of the middle layer lead and the bottom layer lead;
mounting at least one passive device on the interlayer substrate and having pins of the passive device wire-connected with the passive device;
mounting a pre-prepared packaging layer on the intermediate layer substrate, wherein the packaging layer is provided with a pin lead through hole and a device groove corresponding to the passive device;
depositing metal in the pin conductor through holes of the packaging layer to form pin connecting conductors, and preparing top pins on one side of the packaging layer far away from the middle layer conductors to obtain the flexible device based on the system-in-package,
the pin connecting lead is used for realizing the connection of the top pin and the middle layer lead,
the bottom substrate, the middle substrate and the packaging layer are made of flexible materials.
For the above method, in one possible implementation, the bottom layer conductors further include bottom pins of the device,
the size of the middle layer substrate is smaller than that of the bottom layer substrate, and the part of the bottom layer lead which is not covered by the middle layer substrate is the bottom pin.
For the above method, in one possible implementation, the shape of the bottom layer conductive lines and/or the middle layer conductive lines is a malleable shape, the malleable shape including any of a serpentine type and/or a fractal type.
With regard to the above method, in one possible implementation, the thickness of the interlayer substrate is the same as the thickness of the functional chip.
With regard to the above method, in a possible implementation manner, when the thickness of the interlayer substrate is greater than the thickness of the functional chip, the method further includes:
after the functional chip is installed in the corresponding chip installation position, a filling layer is deposited on the functional chip, and one surface of the filling layer, which is far away from the functional chip, and one surface of the middle-layer substrate, which is far away from the bottom layer lead are in the same plane.
The system-in-package-based flexible device and the manufacturing method thereof provided by the embodiment of the disclosure have the advantages that the manufacturing process is simple, the manufactured device is good in ductility and flexibility, small in size, good in reliability and better in performance; can be attached to various curved surfaces, such as the interior and the surface of organisms such as human beings and the like; the method is suitable for various application scenes, biological physiological parameter detection and the like.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 2 shows a schematic structural diagram of an intermediate layer substrate in a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 3 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 4 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 5 shows a lead diagram of a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 6 shows a schematic structural diagram of an intermediate layer substrate (part) of a system-in-package based flexible device according to an embodiment of the present disclosure.
Fig. 7 shows a flow chart in a method of manufacturing a system-in-package based flexible device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
System In Package (SiP) technology is a technology for integrating a plurality of electronic components such as chips, MEMS devices, etc. having different functions into one package system. The integrated packaging after the chips with various different technologies and different functions are connected with each other can greatly reduce the number of welding spots, reduce the connection loss between components, reduce the parasitic impedance, improve the reliability and adapt to high-frequency and high-speed signals, so that the integrated process of the single chip becomes very high-efficiency, and the integrated packaging method is an effective way for reducing the line width, reducing the size and improving the integration level.
Fig. 1 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure. Fig. 2 shows a schematic structural diagram of an intermediate layer substrate in a system-in-package based flexible device according to an embodiment of the present disclosure. As shown in fig. 1 and 2, the device includes a base substrate 100, an intermediate substrate 200, and an encapsulation layer 300.
The chip comprises a bottom substrate 100, wherein one surface of the bottom substrate 100 is provided with a patterned bottom layer lead, and the bottom layer lead comprises a bottom layer chip lead 101.
The middle layer substrate 200 is positioned above the bottom layer substrate 100 and is in contact with the bottom layer wires, patterned middle layer wires are arranged on one surface, far away from the bottom layer wires, of the middle layer substrate 200, and the middle layer wires 203 comprise passive device wires or middle layer chip wires.
The middle-layer substrate 200 is provided with a wire through hole 202 and at least one chip mounting position 201, the position of the chip mounting position 201 corresponds to the position of the bottom-layer chip wire 101, a functional chip 400 is placed in the chip mounting position 201 in an inverted mode, a pin of the functional chip 400 is connected with the bottom-layer chip wire 101, an interlayer connecting wire 204 is arranged in the wire through hole 202, and the interlayer connecting wire 204 is used for achieving connection of the middle-layer wire 203 and the bottom-layer wire.
The packaging layer 300 is used for packaging the device and is positioned above the middle layer substrate 200 and contacted with the middle layer lead 203, at least one device groove 301 is formed in one surface, close to the middle layer lead 203, of the packaging layer 300, the position of the device groove 301 corresponds to the position of the passive device lead, a passive device 500 is installed in the device groove 301, and a pin of the passive device 500 is connected with the passive device lead.
Still be provided with pin wire through-hole 302 in the packaging layer 300, keep away from on the packaging layer 300 the one side of intermediate level wire 203 is provided with the top pin 600 of device, be provided with pin connecting wire 303 in the pin wire through-hole 302, pin connecting wire 303 is used for realizing top pin 600 with the connection of intermediate level wire 203.
Wherein, the materials of the bottom substrate 100, the middle substrate 200 and the packaging layer 300 are flexible materials.
In this embodiment, the flexible materials of the bottom substrate 100, the middle substrate 200, and the encapsulation layer 300 used in the device may be the same or different. The flexible material from which the substrates (including the base substrate, the intermediate substrate) are made may have the following characteristics: good ductility and flexibility to ensure the flexibility and extensibility of the device; low elastic modulus (e.g., the elastic modulus can range from 100KPa to 100 MPa); the reliability is good, and the reliability of deposition and etching in the device manufacturing process and the reliability of the device are ensured; has good waterproof and heat-conducting properties. The initial state of the flexible material can be liquid, so that the size of the prepared substrate can be accurately controlled by the liquid material in the process of preparing the device. The flexible material of the encapsulation layer may have the following properties: the waterproof and sealing performances are good, the air permeability is certain, and the heat conductivity is good; there may also be certain electromagnetic shielding properties to protect the device from external electromagnetic interference.
The functional chip can be a small, light and thin chip, for example, the size of the functional chip can be 1mm × 1mm, and the thickness can be less than or equal to 300 μm.
In this embodiment, the passive device may be a resistor, a capacitor, or other devices that can display the electrical characteristics of the display without an external power source, and implement the functions of the apparatus together with the functional chip. The passive device can be a patch type light and thin device.
In this embodiment, since the functional chip is fragile and vulnerable, the chip mounting position may be disposed in the middle region of the device. Moreover, the functional chip can be arranged on a neutral layer of the device, and the device is analyzed from a mechanical angle, when the whole device is only subjected to bending deformation, the upper surface and the lower surface generally bear tensile stress and compressive stress with the same magnitude, and the stress linearly changes along the thickness direction, namely, at a certain thickness (generally half of the total thickness), a neutral surface exists, the stress on the neutral surface is 0, and only bending exists, so that if the functional chip can be arranged on the neutral surface or a layer near the neutral surface, the stress condition of the functional chip can be greatly optimized, and the functional chip can be protected. Meanwhile, the passive device cannot be thinned generally, and the thickness of the passive device is relatively larger than that of the functional chip, so that the position of a neutral layer of the device can be adjusted by placing the passive device in the uppermost layer (namely, a packaging layer), and the overall thickness of the device can be reduced.
In this embodiment, the passive device and the functional chip may also be mounted in the package layer, and the intermediate layer wires on the intermediate layer substrate are correspondingly arranged to meet the use requirements of the passive device and the functional chip.
In this embodiment, the material of the wires (including the bottom layer wires, the middle layer wires, the interlayer connection wires, the passive device wire connections, the pin connection wires, etc.) in the device may be a metal material having good flexibility and ductility, such as gold, copper.
In this embodiment, the wire through holes and the pin wire through holes need to be staggered to ensure the electrical connection of the device.
The flexible device based on the system-in-package provided by the embodiment of the disclosure has good ductility and flexibility, small size, good reliability and better performance; can be attached to various curved surfaces, such as the interior and the surface of organisms such as human beings and the like; the method is suitable for various application scenes, biological physiological parameter detection and the like.
Fig. 3 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 3, the bottom layer conductive line 101 further includes a bottom pin 102 of the device. The size of the middle substrate 200 is smaller than that of the bottom substrate 100, and the part of the bottom wire not covered by the middle substrate 200 is the bottom pin 102.
In this implementation, the bottom pins and/or the top pins may be prepared according to device needs. For example, the device described above in connection with fig. 3 may be provided without top pins 600, pin connection leads 303, and pin lead through holes 302, when only bottom pins are required for the device. Where both bottom pins and top pins are required for a device, a device comprising top pins 600 and bottom pins 102 as shown in fig. 3 may be prepared. The device as shown in fig. 1 can be prepared when only the top pin is required for the device. The pins (bottom pins and/or top pins) of the device can be configured by those skilled in the art according to actual needs, and the present disclosure is not limited thereto.
In one possible implementation, the interlayer substrate may include at least one layer. Fig. 4 shows a schematic structural diagram of a system-in-package based flexible device according to an embodiment of the present disclosure. When the interlayer substrate includes the first interlayer substrate 210 and the second interlayer substrate 220, as shown in fig. 4, the interlayer wiring 203 may include a first wiring 2031 and a second wiring 2032, and the interlayer connection wiring 204 includes a first interlayer connection wiring 2041 and a second interlayer connection wiring 2042. The wire through holes 202 include a first wire through hole and a second wire through hole, and the chip mounting sites 201 include a first chip mounting site and a second chip mounting site (not shown).
The first intermediate substrate 210 is located above the base substrate 100 and contacts with the base wires, a patterned first wire 2031 is disposed on a surface of the first intermediate substrate 210 away from the base substrate 100, and the first wire 2031 includes an intermediate chip wire.
Be provided with first wire through-hole and at least one first chip installation position on the first intermediate level substrate 210, the position of first chip installation position with bottom chip wire 101's position is corresponding, first functional chip 401 has been placed in the flip-chip in the first chip installation position, first functional chip 401's pin with bottom chip wire 101 is connected, be provided with first interbedded connecting wire 2041 in the first wire through-hole.
The second interlayer substrate 220 is located above the first interlayer substrate 210 and is in contact with the first wire 2031, a second wire through hole and at least one second chip mounting position are arranged on the second interlayer substrate 220, the position of the second chip mounting position corresponds to the position of the interlayer chip wire, a second functional chip 402 is placed in the second chip mounting position in a flip-chip manner, a pin of the second functional chip 402 is connected with the interlayer chip wire, and a second interlayer connecting wire 2042 is arranged in the second wire through hole.
A patterned second conductive line 2032 is disposed on a surface of the second interlayer substrate 220 away from the first conductive line 2031, the second conductive line 2032 includes a passive device conductive line, and the second interlayer connection conductive line 2042 is used to connect the second conductive line 2032 and the first conductive line 2031.
The encapsulation layer 300 is over the second interlayer substrate 220 in contact with the second wire 2032. The pin connecting conductor 303 is used to connect the top pin 600 to the second conductor 2032. The pin of the passive device 500 is connected to the passive device wire (i.e., second wire 2032).
In this implementation, the number of layers of the interlayer substrate may be set according to the actual needs of the device, which is not limited by the present disclosure. Since the structures of the devices have similarities when the intermediate layer substrate is a plurality of layers, the present disclosure does not exemplify devices with different numbers of layers of intermediate layer substrates, and those skilled in the art can refer to the structure of an example of a device with two layers of intermediate layer substrates (i.e., fig. 3). The first lead through hole, the second lead through hole and the pin lead through hole are required to be arranged in a staggered mode, and the through holes in adjacent layers cannot be on the same vertical line.
Fig. 5 shows a lead diagram of a system-in-package based flexible device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 5, the shape of the bottom layer wires and/or the middle layer wires may be a malleable shape, including any of a serpentine and/or fractal.
In this implementation, providing the bottom layer wires and/or the middle layer wires with an extensible shape may increase their extensibility, increasing the tensile properties of the device.
In one possible implementation, the thickness of the interlayer substrate is the same as the thickness of the functional chip. Therefore, the functional chip can be ensured to be arranged behind the chip mounting position, and one surface of the middle layer substrate, which is far away from the bottom layer wire, is ensured to form a smooth plane, so that the middle layer wire can be conveniently prepared subsequently, and the reliability and the stability of the middle layer wire can be ensured.
Fig. 6 shows a schematic structural diagram of an intermediate layer substrate (part) of a system-in-package based flexible device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 6, the thickness of the interlayer substrate 200 is greater than the thickness of the functional chip 400. The functional chip 400 with pins connected with the bottom layer chip wires 101 is placed in the chip mounting position in an inverted mode, a filling layer 700 is arranged above the functional chip 400, and one face, far away from the functional chip 400, of the filling layer 700 is located on the same plane as one face, far away from the bottom layer wires 101, of the middle layer substrate 200. Therefore, the functional chip can be ensured to be arranged behind the chip mounting position, and the surface of the middle layer substrate, which is far away from the bottom layer wire, is ensured to form a smooth plane under the action of the filling layer, so that the middle layer wire can be conveniently prepared subsequently, and the reliability and the stability of the middle layer wire can be ensured.
Fig. 7 shows a flow chart in a method of manufacturing a system-in-package based flexible device according to an embodiment of the present disclosure. As shown in fig. 7, the method is used for manufacturing the system-in-package based flexible device, and includes steps S101 to S109.
In step S101, a metal is deposited on a pre-prepared bottom substrate to obtain a bottom metal layer to be etched, and the bottom metal layer to be etched is patterned to form a bottom wire, where the bottom wire includes a bottom chip wire.
In this embodiment, the bottom metal layer to be etched may be etched by using a photolithography technique, and the bottom conductive line may be obtained by patterning.
In step S102, an intermediate layer substrate is prepared on the underlying wire.
In step S103, the middle layer substrate is etched to form a wire via and at least one chip mounting location in the middle layer substrate, where the chip mounting location corresponds to the bottom layer chip wire.
In this embodiment, the intermediate layer substrate may be etched by using a photolithography technique, and patterned to obtain the wire through hole and the at least one chip mounting site.
In step S104, a flip-chip process is used to mount a functional chip in the corresponding chip mounting location, and the pins of the functional chip are connected to the bottom chip by wires.
In this embodiment, the functional chip can be thinned before flip-chip mounting as needed to reduce the thickness of the entire device.
In step S105, a metal is deposited in the wire via hole of the interlayer substrate to form an interlayer connection wire.
In step S106, depositing a metal on the middle layer substrate to obtain a middle layer metal layer to be etched, and patterning the middle layer metal layer to be etched to form a middle layer wire, where the middle layer wire includes a passive device wire or a middle layer chip wire, and the interlayer connection wire is used to connect the middle layer wire and the bottom layer wire. The etching method is the same as step S101, and is not described herein.
In step S107, at least one passive device is mounted on the interlayer substrate, and the pins of the passive device are wire-connected with the passive device.
In step S108, a pre-prepared encapsulation layer is mounted on the interlayer substrate, and pin wire through holes and device grooves corresponding to the passive devices are formed in the encapsulation layer.
In step S109, metal is deposited in the pin conductor through holes of the package layer to form pin connection conductors, and a top pin is prepared on a side of the package layer away from the middle layer conductors, so as to obtain a system-in-package based flexible device.
The pin connecting lead is used for realizing the connection between the top pin and the middle layer lead, wherein the bottom layer substrate, the middle layer substrate and the packaging layer are made of flexible materials.
In this embodiment, the prepared encapsulation layer may be etched in advance to etch the pin wire through hole and the device groove corresponding to the passive device in the encapsulation layer.
In this embodiment, set up chip installation position in the intermediate level substrate, fine solution flip chip in the chip counterpoint not accurate problem enough, when having guaranteed the reliability of device, improved the manufacturing efficiency and the speed of device.
In this embodiment, when the interlayer substrate is a multilayer, the preparation process of each interlayer substrate is described in step S102 to step S106, which is not repeated herein.
The manufacturing method of the system-in-package-based flexible device provided by the embodiment of the disclosure has the advantages that the process is simple, the manufactured device is good in ductility and flexibility, small in size, good in reliability and better in performance; can be attached to various curved surfaces, such as the interior and the surface of organisms such as human beings and the like; the method is suitable for various application scenes, biological physiological parameter detection and the like.
It should be noted that, although the system-in-package based flexible device and the manufacturing method thereof are described above by taking the above-mentioned embodiments as examples, those skilled in the art can understand that the disclosure should not be limited thereto. In fact, the user can flexibly set each part or step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (11)
1. A system-in-package based flexible apparatus, the apparatus comprising:
the chip comprises a bottom substrate, wherein one surface of the bottom substrate is provided with a patterned bottom wire, and the bottom wire comprises a bottom chip wire;
the middle layer substrate is positioned above the bottom layer substrate and is contacted with the bottom layer lead, one surface of the middle layer substrate, which is far away from the bottom layer lead, is provided with a patterned middle layer lead, the middle layer lead comprises a passive device lead or a middle layer chip lead,
the middle layer substrate is provided with a lead through hole and at least one chip mounting position, the position of the chip mounting position corresponds to the position of the lead of the bottom layer chip, a functional chip is arranged in the chip mounting position in an inverted mode, a pin of the functional chip is connected with the lead of the bottom layer chip, an interlayer connecting lead is arranged in the lead through hole and used for realizing the connection of the middle layer lead and the bottom layer lead;
the packaging layer is used for packaging the device and is positioned above the middle layer substrate to be in contact with the middle layer lead, at least one device groove is formed in one surface, close to the middle layer lead, of the packaging layer, the position of the device groove corresponds to the position of the passive device lead, a passive device is installed in the device groove, and a pin of the passive device is connected with the passive device lead;
the packaging layer is also provided with a pin lead through hole, one surface of the packaging layer, which is far away from the middle layer lead, is provided with a top pin of the device, the pin lead through hole is provided with a pin connecting lead, the pin connecting lead is used for realizing the connection between the top pin and the middle layer lead,
the bottom substrate, the middle substrate and the packaging layer are made of flexible materials.
2. The device of claim 1, wherein the bottom layer of conductive lines further comprises a bottom pin of the device,
the size of the middle layer substrate is smaller than that of the bottom layer substrate, and the part of the bottom layer lead which is not covered by the middle layer substrate is the bottom pin.
3. The apparatus of claim 1 or 2, wherein the intermediate layer substrate comprises at least one layer,
wherein, when the interlayer substrate includes a first interlayer substrate and a second interlayer substrate, the interlayer wire includes a first wire and a second wire, the interlayer connection wire includes a first interlayer connection wire and a second interlayer connection wire, the wire through hole includes a first wire through hole and a second wire through hole, the chip mounting site includes a first chip mounting site and a second chip mounting site,
the first middle layer substrate is positioned above the bottom layer substrate and is contacted with the bottom layer lead, one surface of the first middle layer substrate, which is far away from the bottom layer substrate, is provided with a patterned first lead, the first lead comprises a middle layer chip lead,
the first interlayer substrate is provided with a first lead through hole and at least one first chip mounting position, the position of the first chip mounting position corresponds to the position of the lead of the bottom chip, a first functional chip is arranged in the first chip mounting position in a flip-chip mode, a pin of the first functional chip is connected with the lead of the bottom chip, and a first interlayer connecting lead is arranged in the first lead through hole;
the second interlayer substrate is positioned above the first interlayer substrate and is contacted with the first lead, a second lead through hole and at least one second chip mounting position are arranged on the second interlayer substrate, the position of the second chip mounting position corresponds to the position of the first chip lead, a second functional chip is arranged in the second chip mounting position in a flip manner, a pin of the second functional chip is connected with the first chip lead, and a second interlayer connecting lead is arranged in the second lead through hole,
a patterned second wire is arranged on one surface, far away from the first wire, of the second interlayer substrate, the second wire comprises a passive device wire, and the second interlayer connecting wire is used for realizing the connection of the second wire and the first wire;
the encapsulation layer is located over the second interlayer substrate in contact with the second conductive line.
4. The device of claim 1, wherein the shape of the bottom layer wires and/or the middle layer wires is a malleable shape, the malleable shape including any of a serpentine and/or fractal.
5. The device of claim 1, wherein the thickness of the intermediate layer substrate is the same as the thickness of the functional chip.
6. The apparatus of claim 1, wherein the thickness of the interlayer substrate is greater than the thickness of the functional chip,
the flip chip is arranged in the chip mounting position and is provided with a functional chip connected with the bottom chip through a wire, a filling layer is arranged above the functional chip, and one surface of the functional chip, which is far away from the filling layer, and one surface of the bottom wire, which is far away from the middle layer substrate, are on the same plane.
7. A method for manufacturing a system-in-package based flexible device, the method comprising:
depositing metal on a pre-prepared bottom substrate to obtain a bottom metal layer to be etched, and patterning the bottom metal layer to be etched to form a bottom lead, wherein the bottom lead comprises a bottom chip lead;
preparing a middle layer substrate on the bottom layer lead;
etching the middle layer substrate to form a lead through hole and at least one chip mounting position in the middle layer substrate, wherein the chip mounting position corresponds to the bottom layer chip lead;
installing a functional chip in a corresponding chip installation position by using a flip-chip process, wherein a pin of the functional chip is connected with the bottom chip through a wire;
depositing metal in the wire through hole of the interlayer substrate to form an interlayer connecting wire;
depositing metal on the middle layer substrate to obtain a middle layer metal layer to be etched, and patterning the middle layer metal layer to be etched to form a middle layer lead, wherein the middle layer lead comprises a passive device lead or a middle layer chip lead, and the middle layer connecting lead is used for realizing the connection of the middle layer lead and the bottom layer lead;
mounting at least one passive device on the interlayer substrate and having pins of the passive device wire-connected with the passive device;
mounting a pre-prepared packaging layer on the intermediate layer substrate, wherein the packaging layer is provided with a pin lead through hole and a device groove corresponding to the passive device;
depositing metal in the pin conductor through holes of the packaging layer to form pin connecting conductors, and preparing top pins on one side of the packaging layer far away from the middle layer conductors to obtain the flexible device based on the system-in-package,
the pin connecting lead is used for realizing the connection of the top pin and the middle layer lead,
the bottom substrate, the middle substrate and the packaging layer are made of flexible materials.
8. The method of claim 7, wherein the bottom layer of conductive lines further comprises bottom pins of the device,
the size of the middle layer substrate is smaller than that of the bottom layer substrate, and the part of the bottom layer lead which is not covered by the middle layer substrate is the bottom pin.
9. The method of claim 7, wherein the shape of the bottom layer wires and/or the middle layer wires is a malleable shape, the malleable shape including any of a serpentine and/or fractal.
10. The method of claim 7, wherein the thickness of the interlayer substrate is the same as the thickness of the functional chip.
11. The method of claim 7, wherein when the thickness of the interlayer substrate is greater than the thickness of the functional chip, the method further comprises:
after the functional chip is installed in the corresponding chip installation position, a filling layer is deposited on the functional chip, and one surface of the filling layer, which is far away from the functional chip, and one surface of the middle-layer substrate, which is far away from the bottom layer lead are in the same plane.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105659375A (en) * | 2014-09-26 | 2016-06-08 | 英特尔公司 | Flexible packaging architecture |
| US9812386B1 (en) * | 2002-05-01 | 2017-11-07 | Amkor Technology, Inc. | Encapsulated semiconductor package |
| CN108666308A (en) * | 2018-06-19 | 2018-10-16 | 清华大学 | Flexible integration package system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9812386B1 (en) * | 2002-05-01 | 2017-11-07 | Amkor Technology, Inc. | Encapsulated semiconductor package |
| CN105659375A (en) * | 2014-09-26 | 2016-06-08 | 英特尔公司 | Flexible packaging architecture |
| CN108666308A (en) * | 2018-06-19 | 2018-10-16 | 清华大学 | Flexible integration package system |
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