CN111459735A - Hardware circuit fault injection test method, device, equipment, medium and system - Google Patents
Hardware circuit fault injection test method, device, equipment, medium and system Download PDFInfo
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- CN111459735A CN111459735A CN202010188315.9A CN202010188315A CN111459735A CN 111459735 A CN111459735 A CN 111459735A CN 202010188315 A CN202010188315 A CN 202010188315A CN 111459735 A CN111459735 A CN 111459735A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a hardware circuit fault injection test method, a device, equipment, a medium and a system, wherein the method comprises the following steps: generating a fault generation instruction according to a preset fault information table; controlling the relay card to generate a target fault in a hardware circuit to be tested according to the fault generation instruction; and acquiring the fault information of the hardware circuit to be tested after the target fault is generated. According to the technical scheme of the embodiment of the invention, the fault injection test of the hardware circuit is realized by presetting the fault information table and the relay card, the coverage degree of the test is improved, the accuracy of the hardware circuit test is enhanced, and the functional safety of the hardware circuit can be improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of automatic testing, in particular to a hardware circuit fault injection testing method, device, equipment, medium and system.
Background
With the implementation of functional safety standards in the automotive field at home and abroad, higher requirements are put forward on the functional safety of a hardware circuit in the automotive field, for example, requirements on a hardware circuit fault injection test are explicitly put forward for an automotive controller of an ASI L D class in the functional safety standards, but the hardware fault injection test is not yet explained and explained in the prior art, and how to carry out the fault injection test on the hardware circuit with high efficiency and high execution degree becomes a research focus in the current field.
Disclosure of Invention
The invention provides a hardware circuit fault injection test method, a device, equipment, a storage medium and a system, which are used for realizing the fault injection test of a hardware circuit and realizing high-efficiency hardware function safety verification.
In a first aspect, an embodiment of the present invention provides a hardware circuit fault injection testing method, where the method includes:
generating a fault generation instruction according to a preset fault information table;
controlling the relay card to generate a target fault in a hardware circuit to be tested according to the fault generation instruction;
and acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
A second method, an embodiment of the present invention, provides a hardware circuit fault injection testing apparatus, including:
the fault instruction module is used for generating a fault generation instruction according to a preset fault information table;
the fault generation module is used for controlling the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction;
and the information acquisition module is used for acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
In a third aspect, an embodiment of the present invention provides an apparatus, where the apparatus includes:
one or more processors;
a memory for storing one or more programs for execution by the one or more processors to cause the one or more processors to implement the hardware fault injection testing method as described in any of the embodiments of the present invention.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program is used to implement a hardware fault injection testing method according to any one of the embodiments of the present invention when executed by a processor.
In a fifth aspect, an embodiment of the present invention provides a hardware fault injection test system, where the system includes a hardware circuit to be tested, a relay card, and a terminal device;
the hardware circuit to be tested is connected with at least one relay card through a relay card interface, the relay card is connected to the terminal equipment through a communication serial port, and the relay card is used for generating hardware faults in the hardware circuit to be tested;
the terminal equipment is also connected to the hardware circuit to be tested through a universal interface to acquire fault information of the hardware circuit to be tested;
the terminal equipment comprises the hardware circuit fault injection testing device according to any one of the embodiments of the invention.
According to the technical scheme of the embodiment of the invention, the corresponding fault generation instruction is generated through the preset fault information table, the relay card is controlled to generate the target fault in the hardware circuit to be tested according to the fault generation instruction, and the fault information of the hardware circuit to be tested after the target fault is generated is obtained, so that the injection test of the hardware circuit is realized, the full fault coverage test is realized, and the safety of the hardware circuit is improved.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for testing fault injection of a hardware circuit according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating detailed steps of a hardware circuit fault injection testing method according to a second embodiment of the present invention;
FIG. 3 is a diagram illustrating an exemplary operation of a fault-generating device according to a second embodiment of the present invention;
fig. 4 is a diagram illustrating an example of a circuit for acquiring fault information according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a hardware circuit fault injection testing apparatus according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of an apparatus according to a fourth embodiment of the present invention;
fig. 7 is a schematic structural diagram of a hardware circuit fault injection test system according to a sixth embodiment of the present invention;
fig. 8 is an exemplary diagram of a terminal device according to a sixth embodiment of the present invention;
fig. 9 is a diagram illustrating a structure of a relay card according to a sixth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only a part of the structures related to the present invention, not all of the structures, are shown in the drawings, and furthermore, embodiments of the present invention and features of the embodiments may be combined with each other without conflict.
Example one
Fig. 1 is a flowchart of steps of a hardware circuit fault injection testing method according to an embodiment of the present invention, where the present embodiment is applicable to a situation of an automated hardware circuit test, and the method may be executed by a hardware circuit fault injection testing apparatus, and the apparatus may be implemented in a hardware and/or software manner, see fig. 1, where the method according to the embodiment of the present invention specifically includes the following steps:
The preset fault information table may be a storage table in which at least one hardware circuit fault is stored, the preset fault information table may store information such as an identification number, a name, and a fault description of the hardware circuit fault, and the preset fault information table may be specifically stored through an Excel table.
Specifically, the fault generation instruction corresponding to the fault may be searched in the preset fault information table according to the circuit structure and the circuit type of the hardware circuit to be tested, and it may be understood that one fault instruction or a plurality of fault instructions may be determined in the preset fault information table. Illustratively, the preset fault information table may be stored in the upper computer in an Excel form, and the VBA code may be used to search the preset fault information table to obtain the fault generation instruction.
And step 102, controlling the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction.
The relay card may be a relay switch array, and may control a circuit in the hardware circuit to be tested to generate a corresponding circuit fault, such as a short circuit and an open circuit, according to the fault generation instruction. The hardware circuit to be tested can be a hardware circuit to be tested, specifically a vehicle control circuit and the like, the target fault can be a fault to be tested in the hardware circuit to be tested, the target fault can correspond to the circuit structure of the hardware circuit to be tested, and the corresponding target faults in different hardware circuits to be tested can be different.
Specifically, the fault generation instruction can be sent to the relay card, and the relay card is controlled to generate a corresponding target fault in the circuit to be tested.
And 103, acquiring fault information of the hardware circuit to be tested after the target fault is generated.
The fault information may be information output by the hardware circuit to be tested after the target fault is generated, and may include power supply error information, processor error information, sensor error information, actuator error information, and the like.
Specifically, the fault information of the hardware circuit to be tested, which generates the target fault, can be obtained by connecting the universal serial port to the hardware circuit to be tested.
According to the technical scheme of the embodiment of the invention, the fault generation instruction is generated according to the preset fault information table, the relay card is controlled to generate the target fault in the hardware circuit to be tested through the fault generation instruction, and the fault information fed back by the hardware circuit to be tested after the target fault is generated is obtained, so that the fault injection test of the hardware circuit is realized, the coverage of the test process is ensured to be comprehensive, the reliability of the hardware test is enhanced, and the safety of the hardware circuit is improved.
Example two
Fig. 2 is a flowchart illustrating detailed steps of a hardware circuit fault injection testing method according to a second embodiment of the present invention; the embodiment of the present invention is embodied on the basis of the above embodiment, and referring to fig. 2, the method of the embodiment of the present invention includes the following steps:
The target relay card may be a relay card controlled by a fault generation instruction, and it can be understood that one fault generation instruction table may correspond to one target relay card or to a plurality of relay cards.
Specifically, a target address of the fault generation instruction may be acquired, the relay card corresponding to the target address may be used as the target relay card, and the fault generation instruction may be transmitted to the corresponding relay card according to the target address.
And 203, controlling the target relay card to generate a target fault which generates short circuit and/or open circuit in the hardware circuit to be tested according to the fault generation instruction.
The fault generating element may be a hardware device that generates a circuit fault in the hardware circuit to be tested, and the fault generating element may be mounted in the hardware circuit to be tested and may generate a fault in the hardware circuit to be tested in an opening and closing manner. For example, fig. 3 is a working example diagram of a fault generating device according to a second embodiment of the present invention, taking the fault generating device as a pin, referring to fig. 3, a hardware circuit to be tested may include elements such as a sensor, a resistor, a main control chip, a capacitor, and an actuator, and the hardware circuit to be tested may be failure-controlled by setting a plurality of pins in the hardware circuit to be tested, so that a corresponding fault is generated in the hardware circuit to be tested.
Specifically, the fault generating element can be controlled by the target relay card, so that the fault generating element generates faults such as short circuit and/or open circuit in the hardware circuit to be tested, and corresponding component elements in the hardware circuit to be tested generate faults.
Further, on the basis of the above embodiment of the present invention, the fault generating element includes at least one of a pin, a short-circuit jumper cap, and a relay card. The contact pin and/or the short circuit jump cap can be used for carrying out partial manual test verification in the early stage of automatic test, and the relay card is used for automatic test.
And step 204, acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
Specifically, the device executing the method of the embodiment of the present invention may be connected to the circuit of the hardware to be tested through the universal interface card, and may send a command through the serial port to receive the fault information fed back by the hardware to be tested. Fig. 4 is an exemplary diagram of a circuit for acquiring fault information according to a second embodiment of the present invention, and referring to fig. 4, the circuit for acquiring fault information may be composed of a single chip microcomputer, a CAN interface filter circuit, and a serial port level conversion chip, and a device for executing the method according to the second embodiment of the present invention may send a command to a hardware circuit to be tested through an RS232 serial port to acquire feedback fault information.
In the embodiment of the invention, the fault information can be counted, the classification statistics can be carried out according to different fault types to generate the test result, illustratively, different result scores can be determined according to the severity of the fault, and the fault information of the hardware to be tested can be synthesized to determine the test result.
According to the technical scheme of the embodiment of the invention, the fault generation instruction is determined through the preset fault information table, the target relay card corresponding to each fault generation instruction is determined and sent, each target relay card is controlled to realize short circuit or open circuit in the hardware circuit to be tested according to the fault generation instruction so as to generate the target fault, the fault information of the hardware circuit to be tested after the target fault is generated is obtained, and the fault information is counted so as to determine the test result of the hardware circuit to be tested, so that the injection test of the hardware circuit is realized, the comprehensiveness of the hardware test is improved, and the safety of the hardware circuit is improved.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a hardware circuit fault injection testing apparatus provided in the third embodiment of the present invention, which is capable of executing a hardware circuit fault injection testing method provided in any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method. The device can be implemented by software and/or hardware, and specifically comprises: a fault instruction module 301, a fault generation module 302 and an information acquisition module 303.
The fault instruction module 301 is configured to generate a fault generation instruction according to a preset fault information table.
And a fault generation module 302, configured to control the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction.
An information obtaining module 303, configured to obtain fault information of the hardware circuit to be tested after the target fault is generated.
According to the technical scheme of the embodiment of the invention, the fault instruction module is used for presetting the fault information table to generate the corresponding fault generation instruction, the fault generation module is used for controlling the relay card to generate the target fault in the hardware circuit to be tested according to the fault generation instruction, and the information acquisition module is used for acquiring the fault information of the hardware circuit to be tested after the target fault is generated, so that the injection test of the hardware circuit is realized, the full-fault coverage test is realized, and the safety of the hardware circuit is improved.
Further, on the basis of the above embodiment of the present invention, the fault generating module 302 includes:
and the instruction sending unit is used for determining a target relay card corresponding to the fault generation instruction and sending the fault generation instruction to the target relay card.
And the fault generating unit is used for controlling the target relay card to generate a target fault of short circuit and/or open circuit in the hardware circuit to be tested according to the fault generating instruction.
Further, on the basis of the above-mentioned embodiment of the present invention, the fault generating element in the fault generating module 302 includes at least one of a pin, a short-circuit jumper, and a relay card.
Further, on the basis of the above embodiment of the present invention, the apparatus further includes a result counting module, configured to count the fault information to determine a test result of the hardware circuit to be tested.
Example four
Fig. 6 is a schematic structural diagram of an apparatus according to a fourth embodiment of the present invention, referring to fig. 6, the apparatus includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of processors 40 in the device may be one or more, and one processor 40 is taken as an example in fig. 4; the device processor 40, the memory 41, the input device 42 and the output device 43 may be connected by a bus or other means, and the bus connection is exemplified in fig. 6.
The memory 41 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as the modules (the fault instruction module 301, the fault generation module 302, and the information acquisition module 303) corresponding to the hardware circuit fault injection test in the embodiment of the present application. The processor 40 executes various functional applications and data processing of the device by running software programs, instructions and modules stored in the memory 41, that is, implements the hardware circuit fault injection test method described above.
The memory 41 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 41 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 41 may further include memory located remotely from processor 40, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 42 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the apparatus. The output device 43 may include a display device such as a display screen. EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are executed by a computer processor to perform a hardware circuit fault injection testing method, where the method includes:
generating a fault generation instruction according to a preset fault information table;
controlling the relay card to generate a target fault in a hardware circuit to be tested according to the fault generation instruction;
and acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
Of course, the storage medium containing the computer-executable instructions provided by the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the hardware circuit fault injection test method provided by any embodiments of the present invention.
Based on the understanding that the technical solutions of the present invention can be embodied in the form of software products, such as floppy disks, Read-Only memories (ROMs), Random Access Memories (RAMs), flash memories (F L ASHs), hard disks or optical disks of a computer, etc., and include instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
EXAMPLE six
Fig. 7 is a schematic structural diagram of a hardware circuit fault injection test system according to a sixth embodiment of the present invention; the present embodiment may be applied to the case of automated testing of hardware circuits, and referring to fig. 7, the system of the embodiment of the present invention includes: a hardware circuit to be tested 61, a relay card 62 and a terminal device 63.
The hardware circuit to be tested 61 is connected with at least one relay card 62 through a relay card interface, the relay card 62 is connected to the terminal device 63 through a communication serial port, and the relay card 62 is used for generating a hardware fault in the hardware circuit to be tested 61; the terminal device 63 is further connected to the hardware circuit to be tested 61 through a general interface to acquire fault information of the hardware circuit to be tested 61; wherein the terminal equipment 63 includes a hardware circuit fault injection testing device as described in any of the embodiments of the present invention.
Specifically, the hardware circuit 61 to be tested may be an expanded hardware circuit, and may have a hardware circuit the same as that of the device to be tested, and may implement the product function of the device to be tested, it may be understood that the hardware circuit 61 to be tested may include a fault generating element, for example, may include at least one pin socket and a short-circuit trip cap, and the hardware circuit to be tested may generate different faults according to the control condition of the relay card, so as to implement fault injection.
In the embodiment of the present invention, the relay card 62 may specifically be a control circuit or a control device that controls the to-be-tested hardware circuit 61 to generate a fault, and the to-be-tested hardware circuit 61 may generate different failure modes, such as controller failure or capacitance failure, by opening and closing circuit faults such as open circuit or short circuit generated in the to-be-tested hardware circuit 61. The terminal device 63 may specifically be a device having the hardware fault injection test apparatus provided in any embodiment of the present invention, and may be, for example, an upper computer, in which a preset fault information table may be stored, and the terminal device may send a command through a serial port, generate a fault in the hardware circuit 61 to be tested, and acquire fault information. For example, fig. 8 is a diagram of an embodiment of a terminal device according to a sixth embodiment of the present invention, and referring to fig. 8, a terminal device 63 may have a test result statistics function, may implement a fault generation command by combining an MScomm control in Excel with a VBA code, and implement information interaction with a hardware circuit to be tested 61 through an interface.
Further, on the basis of the embodiment of the invention, the relay card 62 at least comprises a serial port level conversion chip, a single chip microcomputer, a relay set and a contact pin, wherein the serial port level conversion chip is connected to the single chip microcomputer through a TT L serial port and used for converting an obtained RS232 level standard signal into a TT L level standard signal corresponding to the single chip microcomputer, and the single chip microcomputer is sequentially connected to the relay set and the contact pin through a universal input/output port and used for controlling the contact pin to generate faults on the hardware circuit to be tested.
Specifically, the relay card 62 may be a relay switch array essentially, and the relay card 62 may have a single chip microcomputer, and may receive a control instruction sent by the terminal device 63, so that a corresponding relay in the relay group generates an on and/or off action, for example, fig. 9 is a structural example diagram of a relay card provided in a sixth embodiment of the present invention, and referring to fig. 9, the relay card 62 may be formed by sequentially connecting a level conversion chip, the single chip microcomputer, an input/output interface, and a pin.
Further, on the basis of the above embodiment of the invention, the relay set includes at least one of a horizontal relay set and a vertical relay set. The arrangement of the relay groups in the relay card 62 in the embodiment of the present invention may include horizontal relays and vertical relays.
It should be noted that, in the embodiment of the hardware circuit injection testing apparatus, each unit and each module included in the embodiment are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A hardware circuit fault injection test method is characterized by comprising the following steps:
generating a fault generation instruction according to a preset fault information table;
controlling the relay card to generate a target fault in a hardware circuit to be tested according to the fault generation instruction;
and acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
2. The method according to claim 1, wherein the controlling the relay card to generate the target fault in the hardware circuit to be tested according to the fault generation instruction comprises:
determining a target relay card corresponding to the fault generation instruction, and sending the fault generation instruction to the target relay card;
and controlling the target relay card to generate a target fault of short circuit and/or open circuit in the hardware circuit to be tested according to the fault generation instruction.
3. The method of claim 2, wherein the fault generating element comprises at least one of a pin, a short jumper, and a relay.
4. The method of claim 1, further comprising:
and counting the fault information to determine the test result of the hardware circuit to be tested.
5. A hardware circuit fault injection testing apparatus, comprising:
the fault instruction module is used for generating a fault generation instruction according to a preset fault information table;
the fault generation module is used for controlling the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction;
and the information acquisition module is used for acquiring the fault information of the hardware circuit to be tested after the target fault is generated.
6. An apparatus, comprising:
one or more processors;
memory to store one or more programs that, when executed by the one or more processors, cause the one or more processors to implement the hardware fault injection testing method of any of claims 1-4.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the hardware fault injection testing method according to any one of claims 1 to 4.
8. A hardware fault injection test system, comprising: the system comprises a hardware circuit to be tested, a relay card and terminal equipment;
the hardware circuit to be tested is connected with at least one relay card through a relay card interface, the relay card is connected to the terminal equipment through a communication serial port, and the relay card is used for generating hardware faults in the hardware circuit to be tested;
the terminal equipment is also connected to the hardware circuit to be tested through a universal interface to acquire fault information of the hardware circuit to be tested;
wherein the terminal device comprises the hardware circuit fault injection testing apparatus of claim 5.
9. The system of claim 8, wherein the relay card comprises at least a serial level conversion chip, a single chip, a relay set and a pin;
the serial port level conversion chip is connected to the single chip microcomputer through a TT L serial port and used for converting the obtained RS232 level standard signal into a TT L level standard signal corresponding to the single chip microcomputer;
the single chip microcomputer is sequentially connected to the relay group and the contact pin through a general input/output port and is used for controlling the contact pin to be in when the hardware circuit to be tested breaks down.
10. The system of claim 9, wherein the relays comprise at least one of horizontal relays and vertical relays.
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| CN202010188315.9A CN111459735A (en) | 2020-03-17 | 2020-03-17 | Hardware circuit fault injection test method, device, equipment, medium and system |
| PCT/CN2021/079539 WO2021185107A1 (en) | 2020-03-17 | 2021-03-08 | Hardware circuit fault injection test method, apparatus, and device, medium and system |
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| CN202010188315.9A CN111459735A (en) | 2020-03-17 | 2020-03-17 | Hardware circuit fault injection test method, device, equipment, medium and system |
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| CN114415637B (en) * | 2022-01-21 | 2023-09-22 | 苏州挚途科技有限公司 | Consistency test method, device and system for CAN communication |
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| WO2021185107A1 (en) * | 2020-03-17 | 2021-09-23 | 中国第一汽车股份有限公司 | Hardware circuit fault injection test method, apparatus, and device, medium and system |
| CN112631846A (en) * | 2020-12-25 | 2021-04-09 | 广州品唯软件有限公司 | Fault drilling method and device, computer equipment and storage medium |
| CN114063598A (en) * | 2021-10-14 | 2022-02-18 | 摩拜(北京)信息技术有限公司 | Bicycle firmware test method and device and firmware test system |
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