CN111446268A - Novel single-transistor active pixel sensor and preparation method thereof - Google Patents
Novel single-transistor active pixel sensor and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 77
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 77
- 239000010703 silicon Substances 0.000 claims abstract description 77
- 238000002955 isolation Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 238000005530 etching Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000012212 insulator Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 7
- 101001096169 Homo sapiens Phosphatidylserine decarboxylase proenzyme, mitochondrial Proteins 0.000 description 5
- 101000739146 Homo sapiens Protein SFI1 homolog Proteins 0.000 description 5
- 102100037271 Protein SFI1 homolog Human genes 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
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Abstract
The invention provides a novel single transistor active pixel sensor and a preparation method thereof, wherein a substrate, a lower buried oxide layer, an intermediate silicon layer, an upper buried oxide layer and an upper silicon layer are sequentially arranged on a silicon on an insulating layer from bottom to top, and the intermediate silicon layer is used as a photoelectric sensitive layer to carry out photoelectron conversion; the converted photoelectrons are limited in the pixel by the first isolation groove, the second isolation groove and the lower buried oxide layer at two ends of the intermediate silicon layer and cannot migrate to the adjacent pixel; applying a back grid pulse on the substrate to form deep depletion in the substrate and the middle silicon layer, wherein incident light generates photo-generated electrons in a deep depletion region, the photo-generated electrons are driven by an electric field to gather on an interface of an upper buried oxide layer/the middle silicon layer, and the gathered photo-generated electrons cause threshold voltage movement in a MOSFET (metal-oxide-semiconductor field effect transistor) in the upper silicon layer; reading out the threshold voltage to obtain the exposure dose of the pixel; the invention can reduce light loss, improve quantum efficiency and prevent photo-generated electronic crosstalk between different pixels.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a novel single-transistor active pixel sensor and a preparation method thereof.
Background
Conventional image sensors are largely classified into two major categories, namely, CMOS (Complementary Metal oxide semiconductor) active pixel sensors and CCD (charged coupled device) image sensors. Due to the defects of high power consumption, incompatibility with a CMOS (complementary metal oxide semiconductor) process, incapability of random reading and the like of the CCD image sensor, the market share of the CCD image sensor in the field of image sensors is small. The CMOS image sensor is completely compatible with the CMOS process, has low cost and low power consumption, and can perform random reading, and thus is a mainstream image sensor device widely used at present. Active pixel sensors typically require integration of the photoelectric conversion, photoelectron integration, signal buffering amplification and cell gating functions. Therefore, each pixel cell of a CMOS image sensor generally requires a plurality of components. The conventional CMOS image sensor generally uses one photodiode to perform photoelectric conversion, and uses three additional transistors to perform other necessary functions. Therefore, the pixel unit of the CMOS image sensor is complex, and the design and process manufacturing thereof are greatly limited, so that the continuous reduction of the pixel size thereof is difficult. On the other hand, due to the addition of an additional transistor, a portion of the effective photosensitive area is lost, resulting in a reduction in the photoelectric quantum efficiency.
In the active pixel sensor based on a single transistor in the prior art, namely a primary optical electronic sensor (PISD), functions of photoelectric conversion, photoelectron integration, signal amplification, random gating of pixels and the like in the active pixel sensor are integrated in the single transistor, so that the complexity of a pixel unit is greatly reduced, the effective sensing area is increased, and high-sensitivity, low-power consumption and high-speed image sensing is realized. The working mechanism of the sensor is different from that of the existing CCD and CMOS sensors. It utilizes a unique buried oxide structure in a silicon-On-Insulator substrate (soi-On-Insulator) to create a deep depletion region in the substrate by applying a voltage pulse across a back gate electrode. The photogenerated electrons generated in this depletion region are utilized to accumulate at the buried oxide/substrate interface. And the threshold voltage in the upper silicon transistor is influenced by utilizing the photo-generated electrons collected at the substrate interface, so that the photo-generated electrons are read out in situ. However, conventional SOI substrates are fully connected, with a path for carrier flow between different pixels. Therefore, in the PISD based on the conventional SOI substrate, crosstalk is liable to occur between pixels, affecting the operation of the entire image sensing array.
Disclosure of Invention
The invention aims to provide a novel single-transistor active pixel sensor and a preparation method thereof. The converted photoelectrons are confined in the present pixel by the first isolation trench, the second isolation trench, and the lower buried oxide layer under the intermediate silicon layer, and cannot migrate to an adjacent pixel. Thus, the flow of photo-generated electrons is isolated, thereby fundamentally avoiding crosstalk between different pixels. Photogenerated electrons generated in the intermediate silicon layer collect at the upper buried oxide/intermediate silicon layer interface above the intermediate silicon layer. These photo-generated electrons will modulate the threshold voltage of the transistor in the upper silicon layer above the upper buried oxide layer. By reading out the threshold voltage of this transistor, the exposure dose of the pixel can be obtained.
To achieve the above object, the present invention provides a novel single-transistor active pixel sensor, comprising:
a substrate;
the lower buried oxide layer is arranged on the substrate;
an intermediate silicon layer disposed on the lower buried oxide layer;
an upper buried oxide layer disposed on the intermediate silicon layer;
the upper silicon layer is arranged on the upper buried oxide layer;
the two isolation grooves are respectively arranged on two sides of the upper silicon layer;
a positive gate oxide layer disposed on the upper silicon layer;
a positive gate disposed on the positive gate oxide layer;
a gate metal contact disposed on the positive gate;
a source region disposed on a first side of the upper silicon layer;
a drain region disposed on a second side of the upper silicon layer;
a back gate metal contact disposed on the substrate;
the two grid side walls are respectively attached to two sides of the positive grid oxide layer, the positive grid and the grid metal contact;
a source metal contact arranged on the source region and positioned between the source region and a first grid side wall of the two grid side walls;
the drain metal contact is arranged on the drain region and is positioned between the drain region and the second grid side wall of the two grid side walls;
the isolation groove is vertically grooved downwards until the isolation groove is communicated with the middle silicon layer (3) and is contacted with the lower buried oxide layer (2);
the first isolation groove of the two isolation grooves is positioned on one side, away from the positive grid, of the source electrode region; the second isolation groove of the two isolation grooves is positioned on one side, away from the positive grid, of the drain region.
Preferably, a first gap region not covered by the metal electrode is included above the source region, and the width of the first gap region is a horizontal distance between the source metal contact and the first isolation groove; and a second gap region which is not covered by the metal electrode is arranged above the drain region, and the width of the second gap region is the horizontal distance from the drain metal contact to the second isolation groove.
Preferably, the width of the first gap region and the second gap region is 100nm to 10000 nm.
Preferably, the thickness of the upper silicon layer is less than 100 nm; the thickness of the intermediate silicon layer is greater than 500 nm.
Preferably, the substrate is undoped or weakly doped.
Preferably, the source region is heavily doped, and the drain region and the source region are doped in the same type.
Preferably, the substrate (1), the middle silicon layer (3) and the upper silicon layer (5) are any one of silicon, silicon germanium, gallium nitride and indium gallium arsenide; the lower buried oxide layer (2) and the upper buried oxide layer (4) are any one of silicon dioxide, aluminum oxide and hafnium oxide.
The invention also provides a manufacturing method of the single-transistor active pixel sensor, which is used for manufacturing the novel single-transistor active pixel sensor and comprises the following steps:
s1, manufacturing double-layer silicon on insulator, wherein the silicon on insulator comprises a substrate, a lower buried oxide layer, a middle silicon layer, an upper buried oxide layer and an upper silicon layer which are sequentially arranged from bottom to top;
s2, photoetching and etching the silicon on the double-layer insulating layer, depositing an oxide layer and then polishing to form a first isolation groove and a second isolation groove;
s3, depositing a positive grid oxide layer and a positive grid material, and photoetching and etching to finally form a positive grid oxide layer and a positive grid; forming a first grid side wall and a second grid side wall by deposition and etching;
s4, photoetching and injecting N-type doped ions to form a source electrode region and a drain electrode region;
s5, photoetching and etching, and opening a metal contact window; metal contacts are deposited and annealed to form source metal contacts, drain metal contacts, gate metal contacts and back gate metal contacts.
Compared with the prior art, the invention has the beneficial effects that:
1) the single transistor active pixel sensor of the present invention is an in-situ optoelectronic sensor based on a double silicon-on-insulator (DSOI) substrate having two buried oxide layers and two silicon layers. The single transistor active pixel sensor of the present invention is based on the deep depletion and in-situ charge induction principles with an upper silicon layer (also called channel region) having a thickness below 100 nm. By means of the fully depleted thin silicon layer (upper silicon layer), the back gate is enabled to generate an interface coupling Effect in the channel region, thereby enabling photogenerated electrons to change the threshold voltage of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). In addition, the thin silicon layer also helps to reduce the loss of light, further improving quantum efficiency. The middle silicon layer is a photoelectric sensitive layer, and the thickness of the middle silicon layer is set to be more than 500nm so as to effectively absorb light and carry out photoelectron conversion.
2) Under a fast back gate pulse, a deep depletion region is created in the substrate and the intermediate silicon layer. And the incident optical signal generates photo-generated electrons in the deep depletion region of the middle silicon layer and is driven by an electric field to gather at the interface of the upper buried oxide layer/the middle silicon layer. The collected photo-generated electrons lower the effective back gate voltage, causing the threshold voltage of the MOSFET in the upper silicon layer to shift, thereby causing a change in its current. By reading out the threshold voltage, the exposure dose of the pixel can be obtained.
3) The generated photoelectrons cannot drift to adjacent pixel units through the complete isolation effect of the first isolation groove, the second isolation groove and the lower buried oxide layer, so that crosstalk between pixels is avoided.
4) The source electrode area and the drain electrode area are provided with a first gap area and a second gap area which are not covered by the metal electrode so as to transmit light, and therefore, the light incident from the upper side can penetrate into the photosensitive area at the lower side.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:
FIG. 1 is a schematic diagram of a novel single-transistor active pixel sensor in accordance with the present invention;
FIGS. 2 a-2 e are schematic flow charts illustrating a method for fabricating a single-transistor active pixel sensor according to the present invention;
FIG. 3 is a schematic diagram of a new single-transistor active pixel sensor in accordance with a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a novel one-transistor active pixel sensor in accordance with a third embodiment of the present invention;
in the figure: 1. a substrate; 2. a lower buried oxide layer; 3. an intermediate silicon layer; 4. an upper buried oxide layer; 5. an upper silicon layer; 6. a first isolation trench; 7. a second isolation trench; 8. a positive gate oxide layer; 9. a positive gate electrode; 10. a source region; 11. a drain region; 12. a first gate spacer; 13. a second gate spacer; 14. a source metal contact; 15. a drain metal contact; 16. a gate metal contact; 17. back gate metal contacts; 18. a first gap region; 19. a second gap region; 20. and improving the source-drain structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a conventional CMOS active image sensor, a single pixel unit needs to be formed by combining at least three transistors and a photodiode, so as to complete the functions of photoelectric conversion, photoelectron integration, signal buffer amplification and random reading which are necessary for the active pixel sensor. This results in a complex structure, a difficult process and design, and a low quantum efficiency. In the novel in-situ optoelectronic sensor (PISD) based on the deep depletion effect of the substrate 1 in the prior art, all functions of active pixel sensing are integrated in one transistor, and the active pixel sensing of a single transistor is realized. However, in the PISD based on the silicon-on-insulator substrate 1 of the common single insulating layer, since the substrate 1 is completely connected between all the pixels, the pixels are easy to form mutual crosstalk, and the performance of the image sensing array is reduced.
In the invention, a PISD device based on a silicon substrate 1 on a double insulating layer is provided, and photoelectron flow between pixel units is isolated by an isolation region by means of an additional buried oxide layer, so that the problem of crosstalk in an image sensing array is thoroughly solved.
As shown in fig. 1, the present invention provides a novel single-transistor active pixel sensor, which is an in-situ optoelectronic sensor based on a double silicon-on-insulator (DSOI) substrate 1, comprising, sequentially from bottom to top: a back gate metal contact 17, a substrate 1, a lower buried oxide layer 2, an intermediate silicon layer 3 (in embodiments of the invention, the preferred thickness is greater than 500nm), an upper buried oxide layer 4, an upper silicon layer 5 (in embodiments of the invention, the preferred thickness is 2nm to 100nm), a positive gate oxide layer 8, a positive gate 9, a gate metal contact 16. The substrate 1 is undoped or weakly doped. In the embodiment of the present invention, the substrate 1, the middle silicon layer 3, and the upper silicon layer 5 are any one of silicon, silicon germanium, gallium nitride, and indium gallium arsenide, according to different optical wavelengths for sensing. In the embodiment of the present invention, the lower buried oxide layer 2 and the upper buried oxide layer 4 are any one of silicon dioxide, aluminum oxide, and hafnium oxide.
The single transistor active pixel sensor of the present invention further comprises two isolation trenches, a source region 10, a drain region 11, two gate spacers, a source metal contact 14, a drain metal contact 15.
The two isolation grooves are respectively arranged on two sides of the upper silicon layer 5. The two isolation grooves are respectively a first isolation groove 6 and a second isolation groove 7, and are vertically downwards grooved until the two isolation grooves are communicated with the middle silicon layer 3 and are in contact with the lower buried oxide layer 2.
The source region 10 is disposed on a first side of the upper silicon layer 5. The drain region 11 is disposed on a second side of the upper silicon layer 5. The source region 10 includes a first gap region 18 without a metal electrode covering the first gap region, and the width of the first gap region 18 is the horizontal distance from the source metal contact 14 to the first isolation trench 6. The upper side of the drain region 11 comprises a second gap region 19 not covered by the metal electrode, and the width of the second gap region 19 is the horizontal distance from the drain metal contact 15 to the second isolation groove 7. In the embodiment of the present invention, the width of the first gap region 18 and the second gap region 19 is 100nm to 10000 nm. The first isolation groove 6 is positioned on one side of the source electrode region far away from the positive grid 9; the second isolation trench 7 is located on a side of the drain region 11 away from the positive gate 9.
The source region 10 is heavily doped, and the drain region 11 and the source region 10 are doped in the same type.
The two grid side walls are respectively attached to two sides of the positive grid oxide layer 8, the positive grid 9 and the grid metal contact 16; the two gates are respectively a first gate sidewall 12 and a second gate sidewall.
The source metal contact 14 is disposed on the source region 10 and between the source region 10 and the first gate sidewall 12.
The drain metal contact 15 is disposed on the drain region 11 and located between the drain region 11 and the second gate sidewall 13.
Example one
The invention relates to a method for manufacturing a single-transistor active pixel sensor, which is used for manufacturing the novel single-transistor active pixel sensor and comprises the following steps:
s1, as shown in FIG. 2a, preparing a starting double-layer silicon-on-insulator wafer; the double-layer silicon-on-insulator wafer comprises a substrate 1, a lower buried oxide layer 2, an intermediate silicon layer 3, an upper buried oxide layer 4 and an upper silicon layer 5 which are arranged in sequence from bottom to top. Wherein the silicon doping of the substrate 1 and the intermediate layer is generally weakly p-type doped with a doping concentration of 1015cm-2To 1017cm-2To (c) to (d);
s2, as shown in fig. 2b, first and second isolation trenches 7 are formed. And photoetching and opening windows of the first isolation groove 7 and the second isolation groove 7, and then etching by using the photoresist as a mask to form patterns of the first isolation groove 7 and the second isolation groove 7 respectively. The etching can be dry or wet. The dry etching generally uses a fluorine-based or halogen element gas such as SF6, CHF3, HBr or Cl2, or the like. In the wet etching, a solution such as TMAH or KOH is generally used. Thereafter, the trenches are filled with silicon dioxide by Chemical Vapor Deposition (CVD), and then first and second isolation trenches 7 are formed by chemical mechanical polishing, respectively. The isolation trench needs to be communicated with the whole middle silicon layer 3 and is contacted with the lower buried oxide layer 2, and the depth is generally 500nm to 5000 nm;
s3, as shown in fig. 2c, a positive gate oxide layer 8, a positive gate 9, and two gate spacers are formed. Firstly, depositing a positive grid oxide layer 8 and a positive grid 9; the positive gate oxide layer 8 is typically silicon dioxide (SiO2), and may be silicon nitride, aluminum oxide, or hafnium oxide. The thickness is preferably 2nm to 30 nm. The deposition method can be thermal oxidation, chemical vapor deposition or atomic layer deposition. The positive gate 9 is typically polysilicon, and may be a transparent material such as Indium Tin Oxide (ITO) or a metal such as aluminum, and may have a thickness of 10nm to 200 nm. Photoetching and opening a window of the positive grid pattern, and then etching the positive grid 9 by using photoresist as a mask to form a grid pattern; the etching can be dry or wet. The dry etching generally uses a fluorine-based or halogen element gas such as SF6, CHF3, HBr or Cl2, or the like. In the wet etching, a solution such as TMAH or KOH is generally used.
And depositing a dielectric layer and etching to form two grid side walls by using a chemical vapor deposition method. The dielectric material is typically silicon nitride, aluminum oxide or a low dielectric spacer material such as SiOCN or SiBCN. The thickness is generally from 5nm to 50 nm. Dry etching generally uses fluorine-based or halogen element gases, such as SF6, CHF3, HBr or Cl 2;
s4, as shown in fig. 2d, the source region 10 and the drain region 11 are formed. Photoetching and opening windows for injecting source and drain ions, and injecting ions to form a source region 10 and a drain region 11; the source region 10 and the drain region 11 are both heavily doped regions; the ion implantation is generally carried out with arsenic or phosphorus in a dose of 1013cm-2To 1016cm-2And the energy is between 1keV and 100 keV. High temperature annealing is used to activate the ions after ion implantation. The ion activated annealing temperature is typically between 900 and 1200 degrees for a time period of 1 microsecond to 10 seconds.
S5, as shown in fig. 2e, a source metal contact 14, a drain metal contact 15, a gate metal contact 16 and a back gate metal contact 17 are formed. Depositing metal and annealing to form corresponding source metal contacts 14, drain metal contacts 15, gate metal contacts 16 and back gate metal contacts 17 in the source region 10, drain region 11, positive gate 9 and back gate under the substrate 1; the common metal is aluminum, nickel or titanium, and the annealing temperature is between 300 and 900 ℃. As shown in fig. 2e, the source metal contact 14 and the drain metal contact 15 do not cover the whole of the source region 10 and the drain region 11, and a region without metal coverage, i.e. the first gap region 18 and the second gap region 19, respectively, needs to be left. The first and second gap regions 18, 19 are typically between 100nm and 10000nm in length.
Example two
As shown in fig. 3, the second embodiment is similar to the first embodiment except that the transistors in the upper silicon layer 5 are P-type MOSFETs instead of N-type MOSFETs. The source and drain are heavily P-type doped. Therefore, the process flow of this embodiment is similar to that of embodiment 1, and only the ion implantation type of step S4 needs to be changed to P-type ions, such as boron or BF 2. The implant dose and energy are as in step S4.
EXAMPLE III
As shown in fig. 4, the third embodiment is similar to the first embodiment, and the source and drain regions of the transistor in the upper silicon layer 5 have a structure with raised source and drain heights (RSD). Raised source drain structures 20(RSD) are a common technique used to reduce source drain resistance in current small-scale transistors. The process flow of this embodiment is similar to that of the embodiment, and only one step of source-drain epitaxy process needs to be added after S4. The height of the raised source and drain is generally 10nm to 100 nm.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A novel single-transistor active pixel sensor, comprising:
a substrate (1);
the lower buried oxide layer (2) is arranged on the substrate (1);
an intermediate silicon layer (3) disposed on the lower buried oxide layer (2);
an upper buried oxide layer (4) disposed on the intermediate silicon layer (3);
an upper silicon layer (5) disposed on the upper buried oxide layer (4);
two isolation grooves (6) respectively arranged on two sides of the upper silicon layer (5);
a positive gate oxide layer (8) disposed on the upper silicon layer (5);
a positive gate (9) disposed on the positive gate oxide layer (8);
a gate metal contact (16) disposed on the positive gate (9);
a source region (10) disposed on a first side of the upper silicon layer (5);
a drain region (11) disposed on a second side of the upper silicon layer (5);
a back gate metal contact (17) disposed on the substrate (1);
the two grid side walls are respectively attached to two sides of the positive grid oxide layer (8), the positive grid (9) and the grid metal contact (16);
a source metal contact (14) disposed on the source region (10) and between the source region (10) and a first gate sidewall (12) of the two gate sidewalls;
and the drain metal contact (15) is arranged on the drain region (11) and is positioned between the drain region (11) and a second grid side wall (13) of the two grid side walls.
2. A new type of single transistor active pixel sensor according to claim 1 characterized by the fact that the isolation trench is notched vertically down until it passes through the intermediate silicon layer (3) and contacts the underlying buried oxide layer (2);
a first isolation groove (6) of the two isolation grooves is positioned on one side, away from the positive grid (9), of the source electrode region (10); the second (7) of the two isolation trenches is located on the side of the drain region (11) remote from the positive gate (9).
3. A new type of single transistor active pixel sensor according to claim 1, characterized in that the source region (10) comprises above it a first gap region (18) not covered by a metal electrode, the width of the first gap region (18) being the horizontal distance between the source metal contact (14) and the first isolation trench (6); the upper part of the drain region (11) comprises a second gap region (19) which is not covered by the metal electrode, and the width of the second gap region (19) is the horizontal distance from the drain metal contact (15) to the second isolation groove (7).
4. A new type of single transistor active pixel sensor according to claim 4, characterized in that the width of the first (18) and second (19) gap regions is between 100nm and 10000 nm.
5. A new type of single transistor active pixel sensor according to claim 1, characterized in that the thickness of the upper silicon layer (5) is less than 100 nm; the thickness of the intermediate silicon layer (3) is greater than 500 nm.
6. The novel single-transistor active pixel sensor of claim 1, wherein the substrate is undoped or weakly doped.
7. A new type of single transistor active pixel sensor as claimed in claim 1, characterized in that the source region (10) is heavily doped and the drain region (11) and the source region (10) are homodoped.
8. A new type of single transistor active pixel sensor according to claim 1, characterized in that the substrate (1), the intermediate silicon layer (3), the upper silicon layer (5) is any one of silicon, silicon germanium, gallium nitride, indium gallium arsenic; the lower buried oxide layer (2) and the upper buried oxide layer (4) are any one of silicon dioxide, aluminum oxide and hafnium oxide.
9. A method of manufacturing a single-transistor active pixel sensor for use in manufacturing a novel single-transistor active pixel sensor as claimed in any one of claims 1 to 8, comprising the steps of:
s1, manufacturing double-layer silicon-on-insulator, wherein the silicon-on-insulator comprises a substrate (1), a lower buried oxide layer (2), a middle silicon layer (3), an upper buried oxide layer (4) and an upper silicon layer (5) which are sequentially arranged from bottom to top;
s2, photoetching and etching the silicon on the double-layer insulating layer, depositing an oxide layer and then polishing to form a first isolation groove (6) and a second isolation groove (7);
s3, depositing positive grid oxide layer (8) and positive grid (9) materials, and photoetching and etching to finally form the positive grid oxide layer (8) and the positive grid (9); forming a first gate side wall (12) and a second gate side wall (13) by deposition and etching;
s4, photoetching and implanting N-type doped ions to form a source region (10) and a drain region (11);
s5, photoetching and etching, and opening a metal contact window; metal contacts are deposited and annealed to form a source metal contact (14), a drain metal contact (15), a gate metal contact (16) and a back gate metal contact (17).
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| CN110890418A (en) * | 2019-12-02 | 2020-03-17 | 中国科学院上海微系统与信息技术研究所 | Transistor structure with double buried oxide layers and preparation method thereof |
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| CN109728019A (en) * | 2019-01-04 | 2019-05-07 | 复旦大学 | Single-transistor active pixel sensor and preparation method based on silicon on insulating layer |
| CN110890418A (en) * | 2019-12-02 | 2020-03-17 | 中国科学院上海微系统与信息技术研究所 | Transistor structure with double buried oxide layers and preparation method thereof |
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Application publication date: 20200724 |