CN111446179B - Wafer testing method and device - Google Patents
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Abstract
The invention discloses a wafer testing method and a device, wherein the method comprises the following steps: screening out a target chip set with the approximation degree of the front-layer optical spectrum meeting a preset approximation requirement according to the front-layer optical spectrum of each chip in the wafer set to be detected; executing a to-be-tested process on the to-be-tested wafer group to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure; screening out a chipset set to be tested, wherein the difference degree of the optical spectrum of the current layer meets the preset difference requirement, according to the optical spectrum of the current layer of each chip in the target chipset set; and taking the set of the chip sets to be tested as a test sample, and verifying the optical model of the current layer structure. The method and the device provided by the invention are used for solving the technical problems that in the prior art, the accuracy of the verified optical model is poor and the accuracy of the optical measurement result is reduced because the test sample is selected only according to the position relation between the chip and the center and the edge of the wafer. The accuracy of the optical measurement result is effectively improved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a wafer testing method and apparatus.
Background
In the field of semiconductor technology, optical metrology is more commonly used to monitor and inspect device structure parameters (e.g., feature sizes) during semiconductor fabrication processes. In order to ensure the accuracy of optical measurement, a spectrum library and an optical model need to be established through modeling simulation. Therefore, it is necessary to use a transmission electron microscope as a reference measurement technique to perform test analysis on the wafer with the experimental design for calibrating the optical model.
In order to ensure the comprehensiveness of the chip as the test sample and verify the optical model more accurately, it is often necessary to select a chip with a large morphological difference from the current layer structure to be tested after the current layer structure is formed by performing the process to be tested on the wafer, and to test the chip for verifying the optical model. The method for selecting the core chip from the wafer to be tested for modeling verification at present is to consider that the difference of the shapes of a middle chip and an edge chip on the same wafer is large, so that the chips are selected as test samples at intervals from the center to the edge of the wafer according to the coordinates of the chips on the wafer.
However, the test sample is selected only according to the position relationship between the chip and the center and the edge of the wafer, and it is difficult to select a sample with a large difference in current layer structure formed by the process to be tested, which results in poor accuracy of the verified optical model, thereby reducing the accuracy of the optical measurement result.
Disclosure of Invention
The present disclosure is directed, at least in part, to solving the technical problem of the prior art semiconductor processing apparatus that the chamber is susceptible to contamination by impurity particles.
In a first aspect, the present disclosure provides a wafer testing method, including:
screening out a target chip set according to the front-layer optical spectrum of each chip in the wafer set to be tested, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement;
executing a process to be tested on the wafer group to be tested to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure of each chip in the target chip group set;
screening out a set of chips to be tested according to the current-layer optical spectrum of each chip in the target chip set, wherein the set of chips to be tested is a set of chips with the current-layer optical spectrum having the difference degree meeting the preset difference requirement;
and taking the chipset set to be tested as a test sample, and verifying the optical model of the current layer structure.
Optionally, the number of chips in the target chipset set is uniformly distributed on each wafer in the wafer group to be tested; the number of chips in the chipset set to be tested is uniformly distributed on each wafer in the wafer set to be tested.
Optionally, screening out a set of target chip sets according to the front-layer optical spectrum of each chip in the wafer set to be tested includes: sorting the chips in each wafer according to the spectrum value according to the front-layer optical spectrum of each chip in each wafer in the wafer group to be detected, and grouping the chips in each wafer into a plurality of chip groups according to the adjacent rule in sequence; executing a process of determining a most similar chip set for each wafer, and screening out a most similar chip set with the highest approximation degree from all the determined most similar chip sets to be used as the target chip set; wherein the process of determining the most likely set of chips comprises: determining similar chip sets with the highest approximation degree of each chip set on the ith wafer in the wafer set to be tested on other wafers in the wafer set to be tested, and taking each chip set on the ith wafer and the corresponding similar chip set as a similar chip set; wherein each chipset on the ith wafer corresponds to a similar chipset on each of the other wafers; each chip set on the ith wafer corresponds to a similar chip set; i is more than equal to 1 and less than or equal to the number of the wafers in the wafer group to be tested; and determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to all chip sets on the ith wafer as the most similar chip set of the ith wafer.
Optionally, the grouping the chips in each wafer into a plurality of chip groups according to the sequentially adjacent rules includes: grouping the chips in each wafer into n-2m +2 chip groups according to a rule of sequential adjacency and the number of the chips of each chip group is 2m-1, wherein at least one different chip is arranged in each two chip groups; wherein m is a natural number greater than 1, and n is the number of chips on each wafer.
Optionally, the determining similar chip sets with the highest similarity to each chip set on the ith wafer in the wafer group to be tested on other wafers in the wafer group to be tested includes: executing a process of determining similar chip sets on each chip set on the ith wafer on each other wafer in the wafer set to be tested so as to obtain the similar chip sets of each chip set on each other wafer; wherein the process of determining similar chipsets comprises: screening x groups of undetermined chip sets with the average value of the spectrum values closest to the reference average value from the k wafer of the wafer group to be detected according to the reference average value of the spectrum values of the j chip sets on the ith wafer, wherein x is greater than 1, j is greater than equal 1 and is less than or equal to the number of the chip sets on the ith wafer; k is more than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested, and k is not equal to i; and determining a similar chip set of the jth chip set on the ith wafer on the kth wafer from the x groups of chip sets to be determined.
Optionally, the determining, from the x groups of pending chip sets, a similar chip set of the jth chip set on the ith wafer on the kth wafer, includes: judging whether the average value of the x groups of the to-be-determined chip sets is equal to the reference average value or not; if yes, taking the chip set with the minimum mean square error of the spectrum values in the x groups of undetermined chip sets as a similar chip set of the jth chip set on the kth wafer; and if not, taking the chip set with the minimum coefficient of variation of the spectral values in the x groups of pending chip sets as a similar chip set of the jth chip set on the kth wafer.
Optionally, determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to each chip set on the ith wafer, as a most similar chip set of the ith wafer, includes: and determining a similar chip set with the minimum mean square deviation of the spectral values from all similar chip sets corresponding to all chip sets on the ith wafer to serve as the most similar chip set of the ith wafer.
Optionally, the selecting, as the target chipset set, the most similar chip set with the highest similarity from all the determined most similar chip sets includes: and screening out the minimum similar chip set with the minimum mean square error of the spectrum values from all the determined most similar chip sets as the target chip set.
Optionally, the screening out a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set includes: sorting the chip sub-wafers in the target chipset set according to the current-layer optical spectrum of each chip in the target chipset set; in each wafer of the wafer group to be tested, screening out the chip group to be tested of the wafer according to the sorting equal step length by taking a as an interval step length, and forming the chip group to be tested by the chip group to be tested of each wafer, wherein a is more than or equal to 1.
In a second aspect, the present disclosure provides a wafer testing apparatus, comprising:
the first screening module is used for screening a target chip set according to the front-layer optical spectrum of each chip in the wafer set to be tested, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement;
the acquisition module is used for executing a process to be tested on the wafer group to be tested, forming a current layer structure and acquiring a current layer optical spectrum of the current layer structure of each chip in the target chip group set;
the second screening module screens out a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is the chipset set of which the difference degree of the current-layer optical spectrum meets the preset difference requirement;
and the test module is used for verifying the optical model of the current layer structure by taking the chipset set to be tested as a test sample.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the wafer testing method and device provided by the embodiment of the application, the obtained difference of the current-layer optical spectrum quality inspection of the current-layer structure not only comprises the difference between parameters to be tested in the current-layer structure, but also comprises the difference between the previous-layer structures. In order to ensure the accuracy of the optical model of the current-layer structure, a target chipset set with the approximation degree meeting the preset approximation requirement is screened out according to the front-layer optical spectrum of each chip in the wafer group to be detected, so as to ensure that the morphological characteristics of the front-layer structures of the chips in the target chipset set are as close as possible, and further reduce the interference of the front-layer structure on the optical spectrum of the current-layer structure. And after the current layer structure is formed by executing the process to be tested, screening a chipset set to be tested with the difference degree meeting the preset difference requirement from the target chipset set, and verifying the optical model of the current layer structure by taking the chipset set to be tested as a test sample. Therefore, the situation that the appearance of the front layer structure of the test sample is as close as possible, and the accuracy of optical simulation modeling of the current layer structure is ensured when the appearance of the current layer structure of the test sample is different as much as possible, so that the accuracy of an optical measurement result is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required to be used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the description below are only embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the provided drawings without creative efforts.
Fig. 1 is a flow diagram of a wafer testing method in accordance with one or more embodiments of the present disclosure;
FIG. 2 is a flow diagram of screening a set of target chipsets in accordance with one or more embodiments of the disclosure;
fig. 3 is a schematic view of a wafer testing apparatus according to one or more embodiments of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be referred to by the same or similar reference numerals.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and examples of the present disclosure are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and examples of the present application may be combined with each other without conflict.
According to an aspect of the present disclosure, there is provided a wafer testing method, as shown in fig. 1, including:
s101, screening out a target chip set according to the front-layer optical spectrum of each chip in the wafer set to be tested, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement;
step S102, executing a process to be tested on a wafer group to be tested to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure of each chip in a target chip group set;
step S103, screening out a chipset set to be tested according to the optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is the chipset set of which the difference degree of the optical spectrum of the current layer meets the preset difference requirement;
and step S104, taking the chipset set to be tested as a test sample, and verifying the optical model of the current layer structure.
The current optical model verification test usually defaults that the shape and the size of a front layer structure on a wafer are consistent before a to-be-tested process is executed on a to-be-tested wafer group, and defaults that the front layer optical spectrum of the front layer structure is consistent, so that after the to-be-tested process is executed on the to-be-tested wafer group to form a current layer structure, the current layer optical spectrum of the current layer structure is theoretically considered to only represent the parameter difference of the current layer structure, and sampling is only carried out according to the positions of a chip on the wafer, away from the center and the edge. However, the same wafer has different chip features and sizes produced by the same process, and the different chip features on different wafers are different, so according to the research of the applicant, the difference of the front layer structure can affect and sacrifice the modeling simulation accuracy of the current layer structure during the optical model simulation, and the accuracy of the optical measurement result is reduced. Therefore, when the chip sample for testing is selected, the influence factors of the front layer structure and the distribution characteristics of the current layer structure are comprehensively considered, the selected sample is the chip set with the appearance difference of the front layer structure as small as possible and the appearance difference of the current layer structure as large as possible, so that the modeling simulation accuracy is ensured, and the accuracy of the optical measurement result is improved.
The following describes the detailed steps of the wafer testing method provided by the present application in an embodiment:
firstly, a wafer group to be tested needs to be prepared, different experimental designs can be performed according to different characteristics of the process to be tested, and therefore the number h of the wafers in the wafer group to be tested is determined, wherein h is a natural number.
Then, step S101 is executed to screen out a target chipset set whose approximation degree meets a preset approximation requirement according to the front-layer optical spectrum of each chip in the wafer group to be tested. Optionally, in order to ensure that the chip structure on each wafer can be fully verified, a sufficient number of chips to be tested can be sampled, and the number of chips in the target chipset set can be set to be uniformly distributed on each wafer in the wafer group to be tested.
It should be noted that, according to different processes to be tested, both the optical spectrum of the front layer and the optical spectrum of the current layer in the present application may be a scattering spectrum, a reflection spectrum, an absorption spectrum, or the like, the abscissa of the corresponding spectral curve may be a wavelength, and the ordinate may be a scattering intensity, a reflectivity, an absorption rate, or the like of light, which is not limited herein.
The screening of the target chip set is to select chips with the morphology characteristics of the front layer structure as close as possible before the process to be tested is executed on the wafer set to be tested. Specifically, different screening methods can be selected according to different requirements on the proximity of the front layer structure, and two methods are listed as examples below:
first, a target chipset is determined from sub-wafers and then combined into a target chipset set.
That is, the chips on each wafer can be grouped according to the number of the chips in the target chip set to be screened on each wafer. And after grouping, calculating the spectral value of each group of each chip, and taking the chip group with the minimum mean square deviation of the spectral values as a target chip group on the wafer. And forming a target chipset set by the target chipsets of all the wafers.
The spectrum value of each chip may be an average value of ordinate parameters of a spectrum curve of the chip. Or a value of a vertical coordinate parameter corresponding to a predetermined key horizontal coordinate of the chip, which is not limited herein.
Secondly, the similarity of the target chip sets of all the wafers in the wafer set to be tested is comprehensively considered.
The step of screening out the target chipset set with the approximation degree meeting the preset approximation requirement includes steps S1011 to S1014.
As shown in fig. 2, step S1011 is executed to sort the chips in each wafer according to the spectrum value of the front layer optical spectrum of each chip in each wafer in the group of wafers to be tested, and group the chips in each wafer into a plurality of chip groups according to the rule of adjacent order. The spectrum value of each chip may be an average value of ordinate parameters of a spectrum curve of the chip. Or a value of a vertical coordinate parameter corresponding to a predetermined key horizontal coordinate of the chip, which is not limited herein.
Specifically, h wafers are in the wafer group to be tested, and taking the ith wafer as an example, chips in the ith wafer are sorted from large to small or from small to large according to the spectral value. Grouping chips in the ith wafer according to a sequential adjacent rule and with the number of the chips of each chipset being 2m & lt-1 & gt, wherein the maximum grouping number on the ith wafer is n & lt-2m & gt & lt 2 & gt chipsets, and at least one different chip is arranged in each two chipsets; wherein m is a natural number greater than 1, and n is the number of chips on the ith wafer. And repeatedly executing the grouping step to finish grouping the h wafers.
Of course, in the implementation process, the number of chips in each chipset may also be 2m, and correspondingly, the maximum grouping number on each wafer is n-2m +1 chipsets, which is not limited herein.
Certainly, the spectral values may not be sorted, but the spectral values may be directly grouped in an exhaustive manner, but the execution efficiency is greatly lower than that of the method provided in this embodiment in which sorting is performed first and then grouping is performed according to the rules adjacent in sequence, and sorting and then grouping are performed according to the rules adjacent in sequence, so that the spectral values of the chips in the separated chip sets are relatively close to each other, a large number of chip sets with relatively large differences in the spectral values of the chips are eliminated, and the calculation amount is greatly reduced.
After grouping of all wafers is completed, the mean and mean square deviation of the spectral values of each chipset can be calculated for subsequent steps. The average value of the spectrum values of the chip groups can be obtained by adding the spectrum values of the chips in the chip groups and dividing the added spectrum values by the number of the reorganized chips, and then the mean square error is further calculated.
Next, step S1012 is executed to determine similar chip sets on other wafers with the highest similarity of each chip set on each wafer in the wafer set to be tested, and use each chip set and its corresponding similar chip set as a similar chip set.
Specifically, taking the ith wafer as an example, taking the average value of the spectral values of the jth chip set on the ith wafer as a reference average value, and screening the x groups of undetermined chip sets with the average value of the spectral values closest to the reference average value from the kth wafer of the wafer group to be detected. And selecting a similar chip set of the jth chip set on the kth wafer from the x groups of chip sets to be determined. Wherein x is more than 1, j is more than equal to 1 and is less than or equal to the number of chip sets on the ith wafer; k is more than equal to 1 and less than or equal to the number of the wafers in the wafer group to be tested, and k is not equal to i. (ii) a
Preferably, an embodiment of selecting a similar chipset from the x groups of pending chipsets may be: firstly, judging whether the average value of x groups of to-be-determined chip sets is equal to a reference average value or not; if yes, taking the chip set with the minimum mean square error of the spectrum values in the x groups of undetermined chip sets as a similar chip set of the jth chip set on the kth wafer; and if not, taking the chip set with the minimum coefficient of variation of the spectral values in the x groups of pending chip sets as a similar chip set of the jth chip set on the kth wafer. Specifically, the method for selecting the similar chip sets in the case can eliminate the influence of measurement scale, so that the similarity between the determined similar chip sets and the jth chip set is higher.
Of course, the method for selecting a similar chipset from the x groups of pending chipsets may also be random selection, may also be selecting a chipset with the smallest mean square error, and may also be selecting a chipset with the mean value closest to the reference mean value, which is not limited herein.
And circularly setting the k value from 1 to h (h is the number of wafers in the wafer group to be detected) except the i value, and repeating the method to determine that the h-1 similar chip sets correspond to the similar chip sets of the jth chip set on the ith wafer on other h-1 wafers except the ith wafer in the wafer group to be detected. The h-1 similar chip sets and the jth chip set are used as a similar chip set.
Then, the j value is set from 1 to f (f is the number of chip sets in the ith wafer) in a circulating manner, and the method is repeated, so that the similar chip sets of all the chip sets on the ith wafer can be determined, and the ith wafer has f similar chip sets in total.
And then, circularly setting the value i from 1 to h, and repeating the method to determine the similar chip sets of all chip sets on each wafer, wherein if the number of the chip sets on each wafer is f, each wafer has f similar chip sets, and the wafer group to be detected has f x h similar chip sets.
Next, step S1013 is executed to determine a similar chip set with the highest similarity from the plurality of similar chip sets of each wafer as the most similar chip set of each wafer.
Specifically, taking the ith wafer as an example, a similar chip set with the highest spectral numerical approximation is determined from all f similar chip sets corresponding to each chip set on the ith wafer, and is taken as the most similar chip set of the ith wafer. Preferably, the similar chip set with the highest approximation degree is the similar chip set with the smallest mean square deviation of the spectral values. Of course, the variance may be the smallest set of similar chips, and is not limited herein.
Assuming that the number of chips per chip group is 2m-1, there are h (2 m-1) chips in each similar chip group, i.e., there are h (2 m-1) spectra. The mean square error of the spectral values for each set of similar chips is obtained by calculating the mean square error of the spectral values for the h x (2 m-1) chips. And traversing and calculating the mean square deviations of the f similar chip sets, and selecting the similar chip set with the minimum mean square deviation as the most similar chip set.
And circularly setting the value i from 1 to h, and repeating the method to determine the most similar chip set of each wafer in the wafer group to be detected, wherein the most similar chip sets are h.
Then, step S1014 is executed to screen out the most similar chip set with the highest approximation degree from all the most similar chip sets of the determined wafer group to be tested, and the most similar chip set is used as the target chip set.
Optionally, the minimum chip-like set with the minimum mean square error of the spectral values in all the maximum chip-like sets may be used as the target chip set. Of course, the minimum set of similar chips with the minimum variance may be used as the target set of chipsets, and is not limited herein.
The target chipset determined by the second method not only considers the proximity of the chips selected on each wafer, but also considers the proximity of the chips selected on all wafers in the wafer group to be tested. The method can better ensure that the appearance characteristics of the front-layer structures of all chips in the target chip set approach, can better represent the parameter characteristics of the current structure when used for optical model verification, and can ensure the accuracy of an optical measurement result.
Of course, in the implementation process, the method for determining the target chipset is not limited to the above two methods, and is not limited herein.
After the target chipset is determined, step S102 and step S103 are continuously executed, a process to be tested is executed on the wafer group to be tested, a current-layer structure is formed, and a current-layer optical spectrum of the current-layer structure of each chip in the target chipset set is obtained. Screening out a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is the chipset set with the difference degree of the current-layer optical spectrum meeting the preset difference requirement.
In a specific implementation process, the process to be tested may be deposition, polishing, etching, or the like, which is not limited herein. In the specific implementation process, in order to analyze the process to be tested more comprehensively, the wafer group to be tested may be experimentally designed in advance, and some process parameters of the process to be tested implemented on each wafer are adjusted, so that the process to be tested on each wafer of the wafer group to be tested is slightly different, so as to analyze the influence of the process parameters on the current structural performance parameters, that is, different parameter settings of the process to be tested implemented on each wafer are allowed. For example, assume that the wafer to be tested has 3 wafers, wherein wafer 1 uses the standard temperature to perform the process to be tested, wafer 2 uses the standard temperature to decrease by 5 degrees to perform the process to be tested, and wafer 3 uses the standard temperature to increase by 5 degrees to perform the process to be tested.
Optionally, in order to ensure that the chip structure on each wafer can be fully verified, a sufficient number of chips to be tested can be sampled, and the number of chips in the set of chips to be tested can be set to be uniformly distributed on each wafer in the set of wafers to be tested.
The screening of the chipset set to be tested is to select the chips with the largest difference in the morphological characteristics of the current layer structure. Specifically, different screening methods can be selected according to different requirements on the difference degree of the current layer structure, and two methods are listed as follows:
firstly, the minimum difference value of the spectrum numerical value of the chip to be detected is preset.
The minimum difference is determined in advance according to experience or experiments, and the absolute value of the difference between the spectrum values of any two chips is larger than the minimum difference, which belongs to the target chip set, from each wafer of the wafer set to be detected. Therefore, the difference of the spectrum of the current layer structure of the chip group to be tested selected from each wafer is ensured to be large enough.
And secondly, extracting the chips to be tested in equal step length after sorting.
Firstly, sorting the sub-wafers of the chips in the target chip set according to the current-layer optical spectrum of each chip in the target chip set according to the spectrum value. And then screening the chipset to be tested of each wafer in the wafer group to be tested according to the sorting equal step length by taking the numerical value a greater than or equal to 1 as the interval step length, and forming a chipset set to be tested by using the chipset to be tested of each wafer. And the value of a is determined according to the required number of chips to be tested and the required difference degree of the current layer structure.
For example, the wafer set to be tested has h wafers, and the target chipset set has 2m-1 chips on each wafer. And sequencing 2m-1 chips belonging to the target chip set on the ith wafer according to the spectral values from small to large or from large to small. Considering that each chip needs m chips to be tested, a =1 is set, and chips with 2 as step length and 1 as interval step length are selected from 2m-1 chips which are sequenced to form a chip set to be tested, wherein the chip set to be tested specifically comprises m chips which are sequenced in the past and are numbered 1, 3, 5 \8230, 2m-1, and therefore m chips with larger difference in current structural morphology are obtained. And (4) executing the steps on the h wafers to obtain h chipsets to be tested, and forming a chipset set to be tested.
After the chipset set to be tested is screened out, step S104 is executed to verify the optical model of the current layer structure by using the chipset set to be tested as a test sample.
In the specific implementation process, the method provided by this embodiment may be applicable to optical modeling verification of each layer of OCD, and is particularly applicable to optical modeling verification of OCD with a complex structure, such as optical metrology modeling verification of PSR, NSR, siGe, EPI, or SIP structures.
Specifically, a target chip set with small morphology difference of a front layer structure is obtained by screening before a process to be tested is implemented, and after the process to be tested is implemented, a chip set to be tested with large difference in a spectrum of a current layer structure is selected from the target chip set and is used as a test sample to perform reference analysis for verifying optical model simulation of the current layer structure. Although the spectrum of the front layer structure still has weak difference, compared with the existing chip selection mode, the test sample selected by the method provided by the embodiment not only meets the condition that the contour difference of the current layer structure is large, but also is beneficial to referring to an analysis verification model, and ensures that the contour difference of the front layer structure is small, thereby reducing the error caused by the difference of the front layer structure and being beneficial to improving the accuracy of the structural parameters obtained by modeling the current layer structure.
In another aspect, the present disclosure provides a wafer testing apparatus, as shown in fig. 3, including:
the first screening module 301 is configured to screen out a target chipset set according to a front-layer optical spectrum of each chip in the wafer group to be tested, where the target chipset set is a chipset set whose proximity of the front-layer optical spectrum meets a preset proximity requirement;
an obtaining module 302, configured to perform a process to be tested on a wafer group to be tested, form a current-layer structure, and obtain a current-layer optical spectrum of the current-layer structure of each chip in a target chip group set;
the second screening module 303 screens out a set of chips to be tested according to the current-layer optical spectrum of each chip in the target chip set, wherein the set of chips to be tested is a set of chips with the difference degree of the current-layer optical spectrum meeting the preset difference requirement;
the test module 304 is configured to verify the optical model of the current layer structure by using the set of chipsets to be tested as a test sample.
It should be noted that the wafer testing apparatus is a corresponding apparatus to the wafer testing method provided in the foregoing embodiments, and the technical features described in the description of the wafer testing method are all applicable to the apparatus, and will not be described herein again.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
according to the wafer testing method and device provided by the embodiment of the application, the obtained difference of the current-layer optical spectrum quality inspection of the current-layer structure not only includes the difference between parameters to be tested in the current-layer structure, but also includes the difference between the previous-layer structures. In order to ensure the accuracy of the optical model of the current-layer structure, a target chipset set with the approximation degree meeting the preset approximation requirement is screened out according to the front-layer optical spectrum of each chip in the wafer group to be detected, so as to ensure that the morphological characteristics between the front-layer structures of the chips in the target chipset set are as close as possible, and further reduce the interference of the front-layer structure on the optical spectrum of the current-layer structure. And after the current layer structure is formed by executing the process to be tested, screening a chipset set to be tested with the difference degree meeting the preset difference requirement from the target chipset set, and verifying the optical model of the current layer structure by taking the chipset set to be tested as a test sample. Therefore, the situation that the appearance of the front layer structure of the test sample is as close as possible, and the accuracy of optical simulation modeling of the current layer structure is ensured when the appearance of the current layer structure of the test sample is different as much as possible, so that the accuracy of an optical measurement result is improved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.
Claims (10)
1. A wafer testing method, comprising:
according to the front-layer optical spectrum of each chip in the wafer group to be detected, executing the process of determining the most similar chip set for each wafer, and screening out a target chip set, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement; wherein, according to the front layer optical spectrum of each chip in the wafer group to be measured, screen out the set of target chip groups, including:
sorting the chips in each wafer according to the spectrum value according to the front-layer optical spectrum of each chip in each wafer in the wafer group to be detected, and grouping the chips in each wafer into a plurality of chip groups according to the adjacent rule in sequence;
executing a process of determining a most similar chip set for each wafer, and screening out the most similar chip set with the highest approximation degree from all the determined most similar chip sets to be used as the target chip set;
executing a process to be tested on the wafer group to be tested to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure of each chip in the target chip group set;
screening a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is a chipset set with larger morphological feature difference of the current-layer structure and the difference degree of the current-layer optical spectrum meeting the preset difference requirement;
and taking the chipset set to be tested as a test sample, and verifying the optical model of the current layer structure.
2. The method of claim 1, wherein:
the number of chips in the target chip set is uniformly distributed on each wafer in the wafer set to be tested;
the number of chips in the chipset set to be tested is uniformly distributed on each wafer in the wafer set to be tested.
3. The method of claim 1, wherein the process of determining the most likely set of chips comprises:
determining similar chip sets with the highest approximation degree on other wafers in the wafer set to be detected by each chip set on the ith wafer in the wafer set to be detected, and taking each chip set on the ith wafer and the corresponding similar chip set as a similar chip set; each chipset on the ith wafer corresponds to a similar chipset on each of the other wafers; each chip set on the ith wafer corresponds to a similar chip set; i is more than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested;
and determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to all chip sets on the ith wafer to serve as the most similar chip set of the ith wafer.
4. The method of claim 3, wherein the sequentially adjacent rule groups the chips in each wafer into a plurality of chip groups, comprising:
grouping the chips in each wafer into n-2m +2 chip groups according to a rule of sequential adjacency and the number of the chips of each chip group is 2m-1, wherein at least one different chip is arranged in each two chip groups; wherein m is a natural number greater than 1, and n is the number of chips on each wafer.
5. The method of claim 3, wherein the determining similar chip sets on other wafers in the set of wafers to be tested that each chip set on the ith wafer in the set of wafers to be tested has a highest degree of similarity thereto comprises:
executing a process of determining similar chip sets on each chip set on the ith wafer on each other wafer in the wafer set to be tested so as to obtain the similar chip sets of each chip set on each other wafer;
wherein the process of determining similar chipsets comprises:
screening x groups of undetermined chip sets with the average value of the spectrum values closest to the reference average value from the k wafer of the wafer group to be detected according to the reference average value of the spectrum values of the j chip set on the ith wafer, wherein x is greater than 1, j is greater than equal to 1 and is less than or equal to the number of the chip sets on the ith wafer; k is more than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested, and k is not equal to i;
and determining a similar chip set of the jth chip set on the ith wafer on the kth wafer from the x groups of chip sets to be determined.
6. The method of claim 5, wherein said determining, from said x sets of pending chipsets, a similar chipset on said kth wafer for said jth chipset on said ith wafer, comprises:
judging whether the average value of the x groups of the to-be-determined chip sets is equal to the reference average value or not;
if yes, taking the chip set with the minimum mean square error of the spectrum values in the x groups of undetermined chip sets as a similar chip set of the jth chip set on the kth wafer;
and if not, taking the chip set with the minimum coefficient of variation of the spectral values in the x groups of pending chip sets as a similar chip set of the jth chip set on the kth wafer.
7. The method of claim 3, wherein determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to each chip set on the ith wafer as the most similar chip set of the ith wafer comprises:
and determining a similar chip set with the minimum mean square deviation of the spectral values from all similar chip sets corresponding to all chip sets on the ith wafer as the most similar chip set of the ith wafer.
8. The method of claim 3, wherein the selecting a most similar chip set with a highest approximation from all the determined most similar chip sets as the target chip set comprises:
and screening out the minimum similar chip set with the minimum mean square error of the spectrum values from all the determined minimum similar chip sets as the target chip set.
9. The method of claim 1, wherein screening out the set of chipsets to be tested according to the current-layer optical spectrum of each chip in the target chipset set comprises:
sorting the sub-wafers of the chips in the target chip set according to the spectrum value according to the current-layer optical spectrum of each chip in the target chip set;
and screening out the chip groups to be tested of the wafers in each wafer of the wafer group to be tested according to the sorting equal step length by taking a as an interval step length, and forming the chip group set to be tested by using the chip groups to be tested of each wafer, wherein a is more than or equal to 1.
10. A wafer test apparatus, comprising:
the first screening module is used for performing a process of determining a most similar chip set on each wafer according to a front-layer optical spectrum of each chip in a wafer group to be detected, and screening out a target chip set, wherein the target chip set is a chip set of which the approximation degree of the front-layer optical spectrum meets a preset approximation requirement; wherein, according to the front optical spectrum of each chip in the wafer group that awaits measuring, select target chip group set, include:
sorting the chips in each wafer according to the spectrum value according to the front-layer optical spectrum of each chip in each wafer in the wafer group to be detected, and grouping the chips in each wafer into a plurality of chip groups according to the adjacent rule in sequence;
executing a process of determining a most similar chip set for each wafer, and screening out the most similar chip set with the highest approximation degree from all the determined most similar chip sets to be used as the target chip set;
the acquisition module is used for executing a process to be tested on the wafer group to be tested, forming a current-layer structure and acquiring a current-layer optical spectrum of the current-layer structure of each chip in the target chip group set;
the second screening module screens a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is a chipset set with larger morphological feature difference of the current-layer structure and the current-layer optical spectrum difference meeting the preset difference requirement;
and the test module is used for verifying the optical model of the current layer structure by taking the chipset set to be tested as a test sample.
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