CN111443948B - Instruction execution method, processor and electronic equipment - Google Patents
Instruction execution method, processor and electronic equipment Download PDFInfo
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- CN111443948B CN111443948B CN202010236471.8A CN202010236471A CN111443948B CN 111443948 B CN111443948 B CN 111443948B CN 202010236471 A CN202010236471 A CN 202010236471A CN 111443948 B CN111443948 B CN 111443948B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention provides an instruction execution method, a processor and electronic equipment, wherein the instruction execution method comprises the following steps: acquiring an instruction to be executed; decoding the instruction to be executed, and if the instruction to be executed is determined to be a first instruction, acquiring the number of a first register, the number of a second register and the number of a third register; the register comprises a first register, a second register, a third register and a third instruction, wherein the first register stores a first source operand, the second register stores a second source operand, the first register or the second register further stores alignment information, the third register is used for writing a target operand, the alignment information is used for indicating the byte position of the target operand in the first source operand and the second source operand, and the first instruction is used for writing the target operand into the third register; and executing the first instruction, and writing the target operand into the third register. The instruction execution method provided by the embodiment of the invention shortens the running period of the processor and improves the data processing efficiency.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to an instruction execution method, a processor and electronic equipment.
Background
In order to increase the data processing speed, the processor often needs to take out and process a plurality of consecutive data at a time, for example, character string data, array data, or the like. However, the data may be stored in unaligned locations in memory.
In order to fetch one piece of data at a time in a non-aligned position or fetch a plurality of pieces of data consecutively misaligned in their entirety at a time, data at an aligned position in the vicinity of the non-aligned data may be sequentially read by a data read instruction. At this time, the data at the aligned position is typically stored in two different registers, separated by a stride. In subsequent processing, an alignment operation and a stitching operation need to be performed on data that spans two registers, so as to acquire the required data.
Currently, in the operation of performing the alignment and the splicing, at least three processor instructions are required, which results in at least three processor cycles being required to complete, and thus the data processing efficiency is low.
Disclosure of Invention
The embodiment of the invention provides an instruction execution method, a processor and electronic equipment, which shorten the running period of the processor and improve the data processing efficiency.
In a first aspect, an embodiment of the present invention provides an instruction execution method, including:
acquiring an instruction to be executed;
decoding the instruction to be executed;
if the instruction to be executed is determined to be a first instruction, acquiring the number of a first register, the number of a second register and the number of a third register; wherein the first register stores a first source operand, the second register stores a second source operand, either the first register or the second register further stores alignment information, the third register is to be used to write a target operand, the alignment information is to indicate a byte position of the target operand in the first source operand and in the second source operand, the first instruction is to write the target operand to the third register;
and executing the first instruction, and writing the target operand into the third register.
Optionally, the executing the first instruction to write the target operand into the third register includes:
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
concatenating the first and/or second target operands into the target operand;
writing the target operand to the third register.
Optionally, the determining, according to the alignment information, a first destination operand in the first source operand and/or a second destination operand in the second source operand includes:
acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information; wherein the predetermined alignment position is used to indicate a byte position of the first target operand in the first source operand and/or a byte position of the second target operand in the second source operand;
determining the first target operand and/or the second target operand according to the target alignment position.
Optionally, the instruction to be executed includes an operation code, and the determining that the instruction to be executed is a first instruction includes:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
Optionally, before the obtaining the instruction to be executed, the method further includes:
executing the insert instruction; wherein the insert instruction is to write the alignment information in the first register or the second register.
Optionally, the first register or the second register includes an indication field, and the indication field is used for storing the alignment information.
Optionally, a position of the indication field in the first register or the second register is related to data storage formats of the first register and the second register, where the data storage formats include a big-end mode and a small-end mode.
Optionally, the bit length of the alignment information is positively correlated to the bit lengths of the first register and the second register.
Optionally, the bit length of the first register and the second register is B × N, the bit length of the alignment information is M, B is a positive integer, M is a positive integer smaller than or equal to B, and N is a positive integer and is smaller than or equal to the M-th power of 2.
In a second aspect, an embodiment of the present invention provides a processor, including:
the instruction fetching unit is used for acquiring an instruction to be executed;
the decoding unit is used for decoding the instruction to be executed;
the processing unit is used for acquiring the number of a first register, the number of a second register and the number of a third register when the decoding unit determines that the instruction to be executed is a first instruction; wherein the first register stores a first source operand, the second register stores a second source operand, either the first register or the second register further stores alignment information, the third register is to be used to write a target operand, the alignment information is to indicate a byte position of the target operand in the first source operand and in the second source operand, the first instruction is to write the target operand to the third register;
and the processing unit is also used for executing the first instruction and writing the target operand into the third register.
Optionally, the processing unit is specifically configured to:
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
concatenating the first and/or second target operands into the target operand;
writing the target operand to the third register.
Optionally, the processing unit is specifically configured to:
acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information; wherein the predetermined alignment position is used to indicate a byte position of the first target operand in the first source operand and/or a byte position of the second target operand in the second source operand;
determining the first target operand and/or the second target operand according to the target alignment position.
Optionally, the instruction to be executed includes an operation code, and the decoding unit is specifically configured to:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
Optionally, the processing unit is further configured to:
executing an insert instruction before the instruction fetch unit obtains an instruction to be executed; wherein the insert instruction is to write the alignment information in the first register or the second register.
Optionally, the first register or the second register includes an indication field, and the indication field is used for storing the alignment information.
Optionally, the position of the indication field in the first register or the second register is related to data storage formats of the first register and the second register, where the data storage formats include a big-end mode and a small-end mode.
Optionally, the bit length of the alignment information is positively correlated to the bit lengths of the first register and the second register.
Optionally, the bit length of the first register and the second register is B × N, the bit length of the alignment information is M, B is a positive integer, M is a positive integer smaller than or equal to B, and N is a positive integer and is smaller than or equal to the M-th power of 2.
In a third aspect, an embodiment of the present invention provides an electronic device, including: a processor and a memory;
the processor is configured to call a program stored in the memory to execute the method provided by any implementation manner of the first aspect of the embodiment of the present invention.
In a fourth aspect, an embodiment of the present application provides a storage medium, including: the computer program is used for implementing the method provided by any implementation manner of the first aspect of the embodiment of the invention.
The embodiment of the invention provides an instruction execution method, a processor and electronic equipment, after a to-be-processed instruction is obtained, the number of a first register, the number of a second register and the number of a third register can be obtained according to the to-be-processed instruction, two source operands and alignment information can be obtained according to the number of the first register and the number of the second register, partial data in the two source operands can be aligned and spliced into new data according to the alignment information and written into the third register, and only one instruction is operated, so that the data which are respectively spanned in two different registers can be aligned and spliced into the third register, the operation time is shortened, and the data processing efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on the drawings without inventive labor.
FIG. 1 is a diagram illustrating data storage in a memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a first instruction according to an embodiment of the present invention;
FIG. 3 is a flowchart of an instruction execution method according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a structure of a first register or a second register according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first register and a second register of a 32-bit register in a small-end mode according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a first register and a second register of a 32-bit register in a big-end mode according to an embodiment of the present invention;
FIG. 7 is a block diagram of a processor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another processor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to increase the processing speed of data during the execution of program codes by a processor, a plurality of consecutive data often need to be fetched and processed at a time, but the data may be stored in a non-aligned position in a memory. For example, fig. 1 is a schematic diagram of data storage in a memory to which an embodiment of the present invention is applicable. As shown in fig. 1, data 1 to data 4 are stored in the memory. Where address P1 and address P3 represent aligned positions, and address P2 and address P4 represent unaligned positions. The processor needs to fetch data 2 and data 3 at once. At this time, data 1 and data 2 may be written into the register 1 and data 3 and data 4 may be written into the register 2 by a data read instruction. Data 2 and data 3 are stored in two different registers, separated by a stride. Subsequently, by performing an alignment operation and a concatenation operation on the data spanned in the register 1 and the register 2, the data 2 and the data 3 can be acquired. The embodiment of the present invention does not limit the type of the memory. Alternatively, the storage may include, but is not limited to, a memory, a hard disk, and an external storage. Optionally, memory may include, but is not limited to, a primary cache memory (cache) and a secondary cache memory.
In the prior art, different codes can be inserted into a software program according to different alignment positions to realize the alignment splicing operation. Specifically, logical displacement operation is performed on the data 1+ the data 2, logical displacement operation is performed on the data 3+ the data 4, and then the data 2 and the data 3 are spliced through bit or operation. Therefore, at least three processor instructions are required, which results in at least three processor cycles to complete, resulting in low data processing efficiency.
Based on the technical problem, the embodiment of the present invention provides an instruction execution method, which provides a new instruction (referred to as a first instruction), and the operation principle of the first instruction is shown in fig. 2. As shown in fig. 2, when the instruction fetched by the processor is the first instruction, the numbers of two read registers (which may be referred to as a first register and a second register, respectively) and the number of one write register (which may be referred to as a third register) may be obtained. The two read registers and the one write register may be any available register in a general register file in the processor. The two read registers respectively store a source operand (which may be referred to as a first source operand and a second source operand, or as operand 1 and operand 2), and one of the two read registers further stores alignment information. A write register is used to write the destination operand (also called operand 3). The alignment information is used for indicating the byte positions of the target operand in the first source operand and the second source operand, so that the target operand can be obtained from operands respectively stored in the two read registers according to the alignment information. Compared with the prior art that at least three processor instructions are needed, the instruction execution method provided by the embodiment of the invention has the advantages that the first instruction can align and splice data at any position in two read registers into the write register according to the alignment information stored in one of the read registers, the alignment splicing operation can be realized by operating one processor instruction, the processor operation cycle is shortened, and the data processing efficiency is improved.
It should be noted that, the embodiment of the present invention does not limit the high-level program language used by the program code executed by the processor and the implemented functions.
It should be noted that, the first instruction is not limited in name in the embodiment of the present invention, and for example, the first instruction may be referred to as a two-operand alignment instruction with a variable alignment position.
It should be noted that the scenario shown in fig. 1 is an applicable scenario of intercepting and aligning consecutive data from consecutive sequentially stored data, and this is not a limitation, but the present invention provides an instruction execution method. The instruction execution method provided by the embodiment of the invention can be applied to any scene in which data which are respectively spanned in two registers need to be combined into the same register, for example, an array with two starting positions which are not aligned is operated, or a character string with two starting positions which are not aligned is compared.
The following description is made with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
It should be noted that the terms "first", "second", "third", "fourth", etc. (if present) in the embodiments of the present invention are used for distinguishing similar objects, and do not necessarily describe a specific order or sequence. It will be appreciated that the data so used may be interchanged where appropriate. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
FIG. 3 is a flowchart of an instruction execution method according to an embodiment of the present invention. In the instruction execution method provided by this embodiment, the execution main body may be a processor. As shown in fig. 3, the instruction execution method provided in this embodiment may include:
s301, obtaining an instruction to be executed.
Generally, program code written in a high level programming language is compiled into instructions that can be stored in memory. The processor may fetch the instructions from the memory and execute them. In this embodiment, the instruction obtained by the processor may be referred to as an instruction to be executed. There are many types of instructions to be executed, and different types of instructions have corresponding execution flows.
Alternatively, the memory may be a memory. Optionally, the memory may include an instruction memory and a data memory. The instructions to be executed may be stored in an instruction memory.
S302, decoding the instruction to be executed.
Specifically, the type of instruction to be executed may be various, such as a memory access instruction, a compute instruction, and so on. By decoding the instruction to be executed, the type of instruction to be executed may be determined. In this embodiment, if the instruction to be executed is the first instruction, S303 is executed.
S303, if the instruction to be executed is determined to be the first instruction, acquiring the number of the first register, the number of the second register and the number of the third register.
The first register stores a first source operand, the second register stores a second source operand, the first register or the second register further stores alignment information, the third register is used for writing a target operand, and the alignment information is used for indicating the byte position of the target operand in the first source operand and the second source operand. The first instruction is to write a target operand to a third register.
Specifically, this embodiment provides an instruction type, which may be referred to as a first instruction, and is used to implement aligning and splicing data that is divided into two different registers into a third register according to alignment information additionally stored in one of the registers. The instruction type involves two read registers and one write register. The two read registers respectively store a source operand, one of the two read registers also stores alignment information, and one of the two write registers is used for writing in a target operand. For convenience of description, the two read registers may be referred to as a first register and a second register, respectively, the source operand stored in the first register may be referred to as a first source operand or operand 1, the source operand stored in the second register may be referred to as a second source operand or operand 2, the write register may be referred to as a third register, and the destination operand may be referred to as operand 3.
It should be noted that the name of the first instruction is not limited in this embodiment, and for example, the first instruction may be referred to as a two-operand alignment instruction with a variable alignment position.
In this step, after the instruction to be executed is decoded, if it is determined that the instruction to be executed is the first instruction, the number of the first register, the number of the second register, and the number of the third register are obtained, so that the first source operand stored in the first register, the second source operand stored in the second register, and the alignment information stored in the first register or the second register can be obtained.
Optionally, the instruction to be executed includes an operation code, and in S303, determining that the instruction to be executed is a first instruction may include:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
Generally, instructions differ in type and in opcode. The operation code corresponding to each instruction is not limited in this embodiment. For example, the opcode corresponding to the first instruction may be align. In this embodiment, when the instruction to be executed is decoded, the operation code included in the instruction to be executed may be obtained. And if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
S304, executing the instruction to be executed, and writing the target operand into the third register.
Specifically, since the alignment information indicates the byte positions of the target operand in the first source operand and in the second source operand, the data at some byte positions in the first source operand and the data at some byte positions in the second source operand can be aligned and spliced into the target operand through the alignment information, and the target operand is written into the third register according to the number of the third register.
Therefore, the instruction execution method provided by the embodiment provides a new instruction. After the instruction to be executed is obtained, if the instruction to be executed is determined to be the first instruction, the numbers of the two read registers and the number of the write register can be obtained according to the first instruction, the two source operands and the alignment information can be obtained according to the two read registers, partial data in the two source operands can be aligned and spliced into new data according to the alignment information, and the new data can be written into the write register number. The first instruction realizes that data at any position in two read registers are aligned and spliced into a write register according to alignment information stored in one of the read registers, and only one instruction is operated to realize that data which are respectively spanned in two different registers are aligned and spliced into a third register. Compared with the prior art in which the alignment splicing operation is realized through a software program, the instruction execution method provided by the embodiment only needs one processor operation cycle, shortens the operation time, improves the data processing efficiency, reduces the power consumption of the processor, avoids different codes generated by the software program according to different alignment positions, and reduces the complexity of software codes and the occupation of code space. Moreover, in this embodiment, the processor only needs two register file read ports when executing the instruction, and thus less hardware resources are consumed.
Optionally, before the instruction to be executed is acquired in S301, the method may further include:
the insert instruction is executed. Wherein the insert instruction is to write the alignment information in the first register or the second register.
The insert instruction is not limited in this embodiment, and may be an instruction for writing data into an arbitrary register.
Next, the position and length of the alignment information stored in the first register or the second register will be described.
Optionally, referring to fig. 4, fig. 4 is a schematic structural diagram of the first register or the second register according to an embodiment of the present invention. The first register or the second register may include an indication field for storing alignment information. In this embodiment, the length of the indication field and the position in the first register or the second register are not limited. The longer the length of the indication field is, the shorter the length of data stored in the first register or the second register is, and the longer the length of the indication field is, the shorter the length of data stored in the first register or the second register can be set as required. For example, the length of the indication field is 8 bits. Alternatively, the length of the indication field may be an integer multiple of a byte (8 bit). Optionally, the alignment information may occupy the entire length of the indication field, or occupy part of the length of the indication field.
Optionally, the position of the indication field in the first register or the second register is related to data storage formats of the first register and the second register, and the data storage formats include a big-end mode and a small-end mode.
The big-end mode means that the high byte of data is stored in the low address of the memory, and the low byte of data is stored in the high address of the memory. The little-endian mode refers to the high byte of data being stored at the high address of the memory and the low byte of data being stored at the low address of the memory. The present embodiment does not limit the names of the big-end mode and the small-end mode. For example, big-end mode is also referred to as big-tail mode, and little-end mode is also referred to as little-tail mode.
This is illustrated by way of example.
Optionally, in an example, fig. 5 is a schematic structural diagram of a first register and a second register of a 32-bit register in a small-end mode according to an embodiment of the present invention. As shown in fig. 5, in the small-end mode, the first register and the second register are bit 31-bit 0 from left to right, corresponding to byte 3-byte 0. Specifically, byte 0 corresponds to bits 7-0, byte 1 corresponds to bits 15-8, byte 2 corresponds to bits 23-16, and byte 3 corresponds to bits 31-24. Byte 0(bit 0-bit 7) of the second register is an indication field (not shown in the figure) in which alignment information is stored. For example, the first instruction provided in this embodiment may implement selecting, as the target operand, 4 adjacent bytes from byte 3 to byte 0 in the first register and 7 bytes in total from byte 3 to byte 1 in the second register.
Fig. 5 shows only one configuration of the first register and the second register in the small-side mode, and is not limited thereto. For example, in another configuration, the indication field may be located at byte 3(bit 24-bit 31) in the first register. For example, the first instruction provided in this embodiment may implement selecting, as the target operand, 4 adjacent bytes from byte 2 to byte 0 in the first register and 7 bytes from byte 3 to byte 0 in the second register.
Optionally, in another example, fig. 6 is a schematic structural diagram of the first register and the second register in the big-end mode of the 32-bit register according to the embodiment of the present invention. As shown in fig. 6, in the big-end mode, the first register and the second register are bit 31-bit 0 from left to right, corresponding to bytes 0-4. Specifically, byte 0 corresponds to bits 31-24, byte 1 corresponds to bits 23-16, byte 2 corresponds to bits 15-8, and byte 3 corresponds to bits 7-0. Byte 0(bit 31-bit 24) of the first register is an indication field (not shown), and alignment information is stored in the indication field. For example, the first instruction provided by this embodiment may implement selecting, as the target operand, 4 adjacent bytes from byte 1 to byte 3 in the first register and 7 bytes from byte 0 to byte 3 in the second register.
Fig. 6 shows only one configuration of the first register and the second register in the big-end mode, and is not limited.
Optionally, the bit length of the alignment information may be positively correlated with the bit lengths of the first register and the second register.
Specifically, the longer the bit length of the first register and the second register is, the longer the bit length of the alignment information is.
Optionally, the bit length of the first register and the second register may be B × N, the bit length of the alignment information is M, B is a positive integer, M is a positive integer smaller than or equal to B, and N is a positive integer and smaller than or equal to the M-th power of 2.
In this embodiment, the specific value of B, M, N is not limited. For example, B is 8 and N is equal to 2 raised to the power M. Assuming that M is 2 and M is a power of 4, N is 4, and the bit length of the first register and the second register is 8 × 4 to 32 bits. As another example, B is 8 and N is less than the power of 2 to the M. Assuming that M is 4 and M is a power of 16, N may be 8, and the bit length of the first register and the second register is 8 × 8 — 64 bits.
For example, referring to table 1, table 1 shows the position of the indication field, the bit length of the alignment information, and the value range in the architectures with different data storage formats and different register lengths.
TABLE 1
Optionally, in S304, executing the first instruction to write the target operand into the third register may include:
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
splicing the first target operand and/or the second target operand into a target operand;
the destination operand is written to the third register.
In particular, alignment information indicates the byte position of the target operand in the first source operand and in the second source operand, and implementations are possible as follows. One implementation is as follows: the destination operand includes some or all of the data in the first source operand. The other realization mode is as follows: the destination operand includes some or all of the data in the second source operand. Still another implementation is: the destination operand includes some or all of the data in the first source operand and includes some or all of the data in the second source operand. In this embodiment, for convenience of description, part or all of the data in the first source operand may be referred to as a first destination operand, and part or all of the data in the second source operand may be referred to as a second destination operand. Therefore, a first target operand in the first source operand and/or a second target operand in the second source operand may be determined according to the alignment information, so that the first target operand and/or the second target operand are spliced into a target operand and written into the third register.
It should be noted that the implementation manner of the alignment information is not limited in this embodiment. This is illustrated by way of example below.
Alternatively, in one implementation, a 32-bit register is taken as an example, see fig. 5 and the first row of table 1. In the small-end mode, selecting 4 adjacent bytes from 7 bytes as the target operand may include 4 ways, which are called alignment result 1-alignment result 4. In the alignment result 1, byte 3 to byte 0 of the first register may be selected as a target operand; in the alignment result 2, byte 2 to byte 0 of the first register and byte 3 of the second register may be selected as target operands; in the alignment result 3, byte 1 to byte 0 of the first register and byte 3 to byte 2 of the second register may be selected as target operands; in the alignment result 4, byte 0 of the first register and byte 3 to byte 1 of the second register may be selected as the target operands. The bit length of the alignment information can be 2 bits, the value range can be decimal numbers of 0-3, and the alignment information and the alignment result 1-4 correspond to each other one by one. The one-to-one correspondence relationship is not limited in this embodiment. For example, in a corresponding relationship, an alignment information value 0 corresponds to an alignment result 1, an alignment information value 1 corresponds to an alignment result 2, an alignment information value 2 corresponds to an alignment result 3, and an alignment information value 3 corresponds to an alignment result 4. In another corresponding relationship, the alignment information value 0 corresponds to the alignment result 4, the alignment information value 1 corresponds to the alignment node 3, the alignment information value 2 corresponds to the alignment result 2, and the alignment information value 3 corresponds to the alignment result 1.
Optionally, in another implementation, taking a 32-bit register as an example, in a big-end mode, 4 bytes are selected from 7 bytes as a target operand, and it is assumed that 8 ways are included, which may be referred to as an alignment result 1 to an alignment result 8. For example, the 8 ways may include the alignment result 1 to the alignment result 4 in fig. 6, and the alignment result 1 to the alignment result 4 in fig. 6 show that the adjacent 4 bytes are selected from the 7 bytes as the target operand. In this embodiment, the other 4 of the 8 modes are not limited. The bit length of the alignment information can be 3 bits, the value range can be 0 to 7 decimal numbers, and the alignment information corresponds to the 8 modes one by one respectively.
Optionally, determining a first destination operand in the first source operand and/or a second destination operand in the second source operand according to the alignment information includes:
and acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information. The preset alignment position is used for indicating the byte position of the first target operand in the first source operand and/or the byte position of the second target operand in the second source operand.
The first target operand and/or the second target operand are determined according to the target alignment position.
This is illustrated by way of example.
Referring to fig. 5, the preset multiple alignment positions may include an alignment result 1 to an alignment result 4, and the values of the alignment information may correspond to the alignment results 1 to 4 one to one. A target alignment position may be determined in the alignment result 1 to the alignment result 4 according to a value of the alignment information, and if the alignment result 4 is assumed, a first target operand and a second target operand may be determined according to the alignment result 4, specifically, the first target operand is byte 0 in the first register, and the second target operand is byte 3 to byte 1 in the second register.
Fig. 7 is a schematic structural diagram of a processor according to an embodiment of the present invention. As shown in fig. 7, the processor provided in this embodiment may include:
an instruction fetching unit 11, configured to obtain an instruction to be executed;
a decoding unit 12, configured to decode the instruction to be executed;
the processing unit 13 is configured to obtain a number of a first register, a number of a second register, and a number of a third register when the decoding unit determines that the instruction to be executed is the first instruction; wherein the first register stores a first source operand, the second register stores a second source operand, either the first register or the second register further stores alignment information, the third register is to be used to write a target operand, the alignment information is to indicate a byte position of the target operand in the first source operand and in the second source operand, the first instruction is to write the target operand to the third register;
the processing unit 13 is further configured to execute the first instruction, and write the target operand into the third register.
Optionally, the processing unit 13 is specifically configured to:
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
concatenating the first and/or second target operands into the target operand;
writing the target operand to the third register.
Optionally, the processing unit 13 is specifically configured to:
acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information; wherein the preset alignment position is used for indicating the byte position of the first target operand in the first source operand and/or the byte position of the second target operand in the second source operand;
determining the first target operand and/or the second target operand according to the target alignment position.
Optionally, the instruction to be executed includes an operation code, and the decoding unit 12 is specifically configured to:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
Optionally, the processing unit 13 is further configured to:
before the instruction fetch unit 11 obtains an instruction to be executed, an insert instruction is executed; wherein the insert instruction is to write the alignment information in the first register or the second register.
Optionally, the first register or the second register includes an indication field, and the indication field is used for storing the alignment information.
Optionally, the position of the indication field in the first register or the second register is related to data storage formats of the first register and the second register, where the data storage formats include a big-end mode and a small-end mode.
Optionally, the bit length of the alignment information is positively correlated to the bit lengths of the first register and the second register.
Optionally, the bit length of the first register and the bit length of the second register are B × N, the bit length of the alignment information is M, B is a positive integer, M is a positive integer smaller than or equal to B, and N is a positive integer and smaller than or equal to the M-th power of 2.
Optionally, the processing unit 13 may include an execution unit 131. The execution unit 131 is used for performing arithmetic operation.
Optionally, the processing unit 13 may further include a physical register 133. During execution of an instruction, source operands may be included in the instruction and need to be read from the physical register file 133. Other data related to the execution of instructions may also be stored in the physical register file. For example, the results of execution by execution unit 131 are written back to physical register file 133.
Optionally, the execution unit 131 may include at least one arithmetic unit. The at least one arithmetic unit may be of different types, e.g. a fixed point arithmetic unit, a floating point arithmetic unit, etc.
Optionally, the processor provided in this embodiment may be a single-transmission processor. The single-emission processor is used for taking out only one instruction from a memory in one clock cycle, decoding only one instruction, executing only one instruction and writing only one operation result.
The processor provided in this embodiment is used to execute the instruction execution method provided in the embodiments shown in fig. 3 to fig. 6, and the principle and technical effect are similar, and are not described herein again.
It should be noted that the present embodiment does not limit the type and implementation manner of the processor, and for example, the processor may be a microprocessor, a chip, or the like.
Fig. 8 is a schematic structural diagram of another processor according to an embodiment of the present invention. The processor provided in this embodiment may be a multi-transmit processor, compared to the processor provided in the embodiment shown in fig. 7. A multi-issue processor refers to a processor that can fetch multiple instructions from memory simultaneously and decode multiple instructions simultaneously in one clock cycle. As shown in fig. 8, the processor provided in this embodiment, on the basis of the processor shown in fig. 7, may further include: rename unit 134, transmit unit 135, and reorder unit 136.
Among other things, rename unit 134 is to rename the address of the instruction written back to physical register file 133.
A dispatch unit 135, configured to determine to which unit to issue an instruction for execution, for example, to an execution unit for execution, or to a fixed point arithmetic unit in an execution unit for execution, or to a floating point arithmetic unit in an execution unit for execution, and so on.
Reorder unit 136 is configured to mark data at the write-back address of the instruction in physical register file 133 as committed, in the order in which the instruction was fetched.
The processor provided in this embodiment is used to execute the instruction execution method provided in the embodiments shown in fig. 3 to fig. 6, and the principle and technical effect are similar, which are not described herein again.
The present invention also provides an electronic device, which may include: a processor and a memory. The processor is configured to call a program stored in the memory to execute the instruction execution method provided in the embodiments shown in fig. 3 to 6, and the principle and the technical effect are similar and will not be described herein again.
It should be noted that the present embodiment does not limit the type of the electronic device, and for example, the electronic device may be a computer, a notebook computer, a smart phone, a tablet computer, and the like.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (18)
1. An instruction execution method, comprising:
acquiring an instruction to be executed;
decoding the instruction to be executed;
if the instruction to be executed is determined to be a first instruction, acquiring the number of a first register, the number of a second register and the number of a third register; wherein the first register stores a first source operand, the second register stores a second source operand, either the first register or the second register further stores alignment information, the third register is to be used to write a target operand, the alignment information is to indicate a byte position of the target operand in the first source operand and in the second source operand, the first instruction is to write the target operand to the third register;
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
concatenating the first and/or second target operands into the target operand;
writing the target operand to the third register.
2. The method of claim 1, wherein said determining a first destination operand in the first source operand and/or a second destination operand in the second source operand according to the alignment information comprises:
acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information; wherein the predetermined alignment position is used to indicate a byte position of the first target operand in the first source operand and/or a byte position of the second target operand in the second source operand;
determining the first target operand and/or the second target operand according to the target alignment position.
3. The method of claim 1, wherein the instruction to be executed comprises an opcode, and wherein determining that the instruction to be executed is a first instruction comprises:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
4. The method of claim 1, wherein prior to fetching the instruction to be executed, further comprising:
executing the insert instruction; wherein the insert instruction is to write the alignment information in the first register or the second register.
5. The method of any of claims 1-4, wherein the first register or the second register includes an indication field, the indication field to store the alignment information.
6. The method of claim 5, wherein a location of the indication field in the first register or the second register is associated with a data storage format of the first register and the second register, the data storage format comprising a big-endian mode and a little-endian mode.
7. The method according to any of claims 1-4, wherein a bit length of the alignment information is positively correlated to a bit length of the first register and the second register.
8. The method according to claim 7, wherein the first register and the second register have a bit length of B x N, the alignment information has a bit length of M, B is a positive integer, M is a positive integer equal to or less than B, and N is a positive integer and equal to or less than 2 raised to the power of M.
9. A processor, comprising:
the instruction fetching unit is used for acquiring an instruction to be executed;
the decoding unit is used for decoding the instruction to be executed;
the processing unit is used for acquiring the number of a first register, the number of a second register and the number of a third register when the decoding unit determines that the instruction to be executed is a first instruction; wherein the first register stores a first source operand, the second register stores a second source operand, either the first register or the second register further stores alignment information, the third register is to be used to write a target operand, the alignment information is to indicate a byte position of the target operand in the first source operand and in the second source operand, the first instruction is to write the target operand to the third register;
the processing unit is further used for executing the first instruction and writing the target operand into the third register;
the processing unit is specifically configured to:
determining a first target operand in the first source operand and/or a second target operand in the second source operand according to the alignment information;
concatenating the first and/or second target operands into the target operand;
writing the target operand to the third register.
10. The processor according to claim 9, wherein the processing unit is specifically configured to:
acquiring a target alignment position corresponding to the alignment information from a plurality of preset alignment positions according to the alignment information; wherein the predetermined alignment position is used to indicate a byte position of the first target operand in the first source operand and/or a byte position of the second target operand in the second source operand;
determining the first target operand and/or the second target operand according to the target alignment position.
11. The processor of claim 9, wherein the instruction to be executed comprises an opcode, and wherein the decode unit is further configured to:
and if the operation code included in the instruction to be executed is the operation code corresponding to the first instruction, determining that the instruction to be executed is the first instruction.
12. The processor as recited in claim 9, wherein said processing unit is further configured to:
executing an insert instruction before the instruction fetch unit obtains an instruction to be executed; wherein the insert instruction is to write the alignment information in the first register or the second register.
13. The processor of any one of claims 9-12, wherein the first register or the second register comprises an indication field, the indication field to store the alignment information.
14. The processor of claim 13, wherein a location of the indication field in the first register or the second register is associated with a data storage format of the first register and the second register, the data storage format comprising a big-endian mode and a little-endian mode.
15. The processor of any of claims 9-12, wherein a bit length of the alignment information is positively correlated to a bit length of the first register and the second register.
16. The processor according to claim 15, wherein the first register and the second register have a bit length of B × N, wherein the bit length of the alignment information is M, wherein B is a positive integer, wherein M is a positive integer equal to or less than B, and wherein N is a positive integer and equal to or less than 2 raised to the power of M.
17. An electronic device, comprising: a processor and a memory;
the processor is configured to invoke a program stored in the memory to perform the method of any of claims 1-8.
18. A computer-readable storage medium, comprising: computer program stored thereon, characterized in that the program, when being executed by a processor, carries out the method of any one of claims 1-8.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049865A (en) * | 1997-12-18 | 2000-04-11 | Motorola, Inc. | Method and apparatus for implementing floating point projection instructions |
| CN104156195A (en) * | 2014-08-19 | 2014-11-19 | 中国航天科技集团公司第九研究院第七七一研究所 | System and method for integrating double-precision-extension 80-digit floating point processing unit in processor |
| CN107918546A (en) * | 2013-03-30 | 2018-04-17 | 英特尔公司 | The processor of part register access, method and system are realized using the full register access through mask |
| CN108463801A (en) * | 2016-01-22 | 2018-08-28 | Arm有限公司 | Identify the coded command of the first and second architectural registers number |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2540939B (en) * | 2015-07-31 | 2019-01-23 | Advanced Risc Mach Ltd | An apparatus and method for performing a splice operation |
| US10705839B2 (en) * | 2017-12-21 | 2020-07-07 | Intel Corporation | Apparatus and method for multiplying, summing, and accumulating sets of packed bytes |
| CN110377339B (en) * | 2019-08-17 | 2024-03-01 | 中昊芯英(杭州)科技有限公司 | Long-delay instruction processing apparatus, method, and device, and readable storage medium |
-
2020
- 2020-03-30 CN CN202010236471.8A patent/CN111443948B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049865A (en) * | 1997-12-18 | 2000-04-11 | Motorola, Inc. | Method and apparatus for implementing floating point projection instructions |
| CN107918546A (en) * | 2013-03-30 | 2018-04-17 | 英特尔公司 | The processor of part register access, method and system are realized using the full register access through mask |
| CN104156195A (en) * | 2014-08-19 | 2014-11-19 | 中国航天科技集团公司第九研究院第七七一研究所 | System and method for integrating double-precision-extension 80-digit floating point processing unit in processor |
| CN108463801A (en) * | 2016-01-22 | 2018-08-28 | Arm有限公司 | Identify the coded command of the first and second architectural registers number |
Non-Patent Citations (1)
| Title |
|---|
| Pentium指令集微操作设计;郭鹏;《中国优秀硕士学位论文全文数据库 信息科技辑》;20060715;I137-18 * |
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