CN111443891B - Variable-length merging and sorting implementation method for electric power internet of things data - Google Patents

Variable-length merging and sorting implementation method for electric power internet of things data Download PDF

Info

Publication number
CN111443891B
CN111443891B CN202010196564.2A CN202010196564A CN111443891B CN 111443891 B CN111443891 B CN 111443891B CN 202010196564 A CN202010196564 A CN 202010196564A CN 111443891 B CN111443891 B CN 111443891B
Authority
CN
China
Prior art keywords
fifo
data
queue
sorted
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010196564.2A
Other languages
Chinese (zh)
Other versions
CN111443891A (en
Inventor
官国飞
徐妍
宋庆武
蒋超
陈志明
蒋峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Fangtian Power Technology Co Ltd
Original Assignee
Jiangsu Fangtian Power Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Fangtian Power Technology Co Ltd filed Critical Jiangsu Fangtian Power Technology Co Ltd
Priority to CN202010196564.2A priority Critical patent/CN111443891B/en
Publication of CN111443891A publication Critical patent/CN111443891A/en
Application granted granted Critical
Publication of CN111443891B publication Critical patent/CN111443891B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a variable-length merging and sorting implementation method of electric power internet of things data, which comprises a queue A to be sorted, a queue B to be sorted, a comparator, a reading control module and a sorting result storage queue, wherein the queue A to be sorted and the queue B to be sorted respectively store data queues which are sorted according to a certain rule, data _ A is latched in data read out each time of the queue A to be sorted, data _ B is latched in data read out each time of the queue B to be sorted, the data _ A and the data _ B are sent into the comparator to be compared and a comparison result is obtained, if the number of the data _ A is more than or equal to that of the data _ B, the data _ A is written into the sorting result queue through a reading control logic, the data _ B is latched, the data of the queue A to be sorted are continuously read and sequentially latched with the queue B to be sorted to be sent into the comparator to be compared and the data _ B to obtain the comparison result, and repeating the process until the two queues to be sorted are merged into an ordered queue. The invention can meet the requirement of time sequence and the requirement of sequencing processing of mass data.

Description

Variable-length merging and sorting implementation method for electric power internet of things data
Technical Field
The invention relates to the field of electrical engineering and computer communication, in particular to a variable-length merging and sorting implementation method for electric power internet of things data.
Background
Sequencing algorithms have been studied in great detail in the scientific and technical field, and many mature sequencing algorithms exist, and in recent years, various sequencing-based methods have been proposed under different applications. Network-based sequencing generally uses a two-input switching comparator for sequencing, and employs a fixed-size sequencing network, which is divided into an input queue, a ping-pong sequencing network, and an output detection module. The sorting based on the linear array is based on the expandable linear array, the comparison insertion unit is adopted, each unit comprises a comparator, a multiplier and a control unit, and the expandable linear array comprises a series of units. The merging and sorting is an effective sorting algorithm established on merging operation, the merging operation is to merge two or more ordered queues into a new ordered list, the implementation method belongs to a sorting method based on a network, and the input queues of the existing merging and sorting method are fixed, cannot merge, compare and sort the queues with different lengths, and cannot meet the sorting requirement of the SQL sentences of the database of the power physical association data. In the prior art, merging is not optimized under the condition that merging sequencing queues are different in length.
Disclosure of Invention
The invention provides a method for realizing variable-length merging and sorting of electric power internet of things data, which aims to overcome the defects of the prior art.
The invention adopts the following technical scheme for solving the technical problems:
according to the method for realizing the variable-length merging and sorting of the electric power internet of things data, the method for realizing the variable-length merging and sorting of the electric power internet of things data is realized by adopting a sorting system, and the sorting system comprises a queue A to be sorted, a queue B to be sorted, a comparator, a reading control module and a sorting result storage queue.
The queue A to be sorted and the queue B to be sorted adopt a first data pre-reading mode, data queues which are sorted according to a certain rule are respectively stored in the queue A to be sorted and the queue B to be sorted, and the queue A to be sorted and the queue B to be sorted respectively output data _ A, data _ B to be sorted and a flag last _ A, last _ B indicating whether the data to be sorted is the last data or not;
the data read out each time by the queue A to be sorted is latched with data _ A, the data read out each time by the queue B to be sorted is latched with data _ B, the data _ A and the data _ B are sent into a comparator to be compared and a comparison result is obtained, if the number of the data _ A is larger than or equal to that of the data _ B, the data _ A is written into a queue of the sorting result through a reading control module, the data _ B is latched, the data of the queue A to be sorted is continuously read and sequentially compared with the data latched data _ B of the queue B to be sorted, the comparison result is obtained, the process is repeated until the two queues to be sorted are merged into an ordered queue and stored in a queue of the sorting result, and the last data of the queue of the sorting result is set as a data flag last _ flag; the reading control module respectively outputs a write enable signal result _ fifo _ wena, sorting result data result _ fifo _ data and a last data flag last _ flag of the sorting result queue.
As a further optimization scheme of the variable-length merging and sorting implementation method of the electric power internet of things data, K clock cycles are needed for the comparator to complete comparison of the data _ A and the data _ B to be sorted, and K is larger than or equal to 1.
As a further optimization scheme of the method for realizing variable-length merging and sorting of the power internet-of-things data, the queue a to be sorted and the queue B to be sorted output flag bits FIFO _ empty _ A, FIFO _ empty _ B which indicate whether the internal FIFO of the queue to be sorted is empty, the comparator outputs a comparison result a _ first, the read control module outputs a read enable signal FIFO _ rena _ A, FIFO _ rena _ B to the queue a to be sorted and the queue B to be sorted according to a data state signal FIFO _ empty _ A, last _ A, FIFO _ empty _ B, last _ B and an output result a _ first signal of the comparator, and the internal FIFO of the queue of the sorting result outputs a full queue of sorting result FIFO _ prog _ full to the read control module when the internal FIFO of the queue of the sorting result is full; setting fifo _ rena _ A logic and last _ A to a _ fifo _ finish, and setting fifo _ rena _ B logic and last _ B to B _ fifo _ finish; the read control module comprises the following steps:
3-1) waiting whether the flag bits FIFO _ empty _ A, FIFO _ empty _ B and result _ FIFO _ prog _ full in the queue to be sorted are invalid, if both the queue a to be sorted and the queue B to be sorted have data to be sorted, inputting the data _ a and the data _ B into a comparator, and jumping to the step 3-2);
3-2) detecting whether a _ fifo _ finish and b _ fifo _ finish are high level, and going to 3-3 if a _ fifo _ finish and b _ fifo _ finish are both low level); jumping to 3-4 if one of a _ fifo _ finish and b _ fifo _ finish is high); go to 3-5 if a _ fifo _ finish and b _ fifo _ finish are both high);
3-3) waiting for K clock beat delays, then detecting the level of the A _ first signal, if the level is high, setting fifo _ rena _ B to be high, setting fifo _ rena _ A to be low, and reading data _ B to be sorted next time in the queue B to be sorted; otherwise, setting fifo _ rena _ A to be high level, setting fifo _ rena _ B to be low level, and reading the next sorting data _ A of the queue A to be sorted; jumping to the step 3-2);
3-4) if a _ fifo _ finish is high and B _ fifo _ finish is low, fifo _ rena _ a is set low, go to step 3-6) if B _ fifo _ finish is high and a _ fifo _ finish is low, fifo _ rena _ B is set low, go to step 3-7);
3-5) judging whether A _ first is high level, if A _ first is high level, writing data _ B into a sequencing result queue, waiting for K clock delays, writing data _ A into the sequencing result queue, and simultaneously setting last _ flag; if A _ first is low level, writing data _ B into a sequencing result queue, waiting for K clock delays, writing data _ A into the sequencing result queue, simultaneously setting last _ flag, ending the merging sequencing, jumping to step 3-1), and repeating the process;
3-6) if B _ fifo _ finish is detected to be high level, setting fifo _ rena _ B as low level, simultaneously setting last _ flag, ending the merging and sorting, skipping to the step 1), and repeating the process; otherwise, fifo _ rena _ B is set to high level;
3-7) if detecting that a _ fifo _ finish is high level, setting fifo _ rena _ A to be low level, simultaneously setting last _ flag, ending the merging and sorting, jumping to the step 1), and repeating the process; otherwise, fifo _ rena _ a is set high.
The write enable signal result _ fifo _ wena signal of the sorting result storage queue is generated by logical OR of the read enable signal fifo _ rena _ A and the fifo _ rena _ B signal, if fifo _ rena _ A is high level, data _ A is selected as sorting result data result _ fifo _ wdata to be written into the sorting result storage queue, otherwise data _ B is selected.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
(1) the invention provides a method for realizing variable-length merging and sorting, which flexibly reads and controls the data comparison result of two queues to be sorted, realizes the merging of every two queues with any queue length and optimizes the method for realizing the merging algorithm of the electric power internet of things data.
(2) The method overcomes the defect of fixed length of an input queue of the traditional merging and sorting implementation method.
Drawings
Fig. 1 is a block diagram of a system architecture for merging and sorting.
FIG. 2 is a waveform diagram according to an embodiment.
FIG. 3 is a waveform diagram of the second embodiment.
FIG. 4 is a three waveform diagram of an embodiment.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the attached drawings:
in the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular internal procedures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Referring to fig. 1, the operation steps of the method for implementing variable-length merging and sorting of the power internet of things data according to the present invention are as follows:
if the flag bits FIFO _ empty _ A, FIFO _ empty _ B and result _ FIFO _ prog _ full waiting for the FIFO inside the queue to be sorted are all invalid, then both the queue a to be sorted and the queue B to be sorted have data to be sorted, set FIFO _ rena _ a logic and last _ a to a _ FIFO _ finish, and set FIFO _ rena _ B logic and last _ B to B _ FIFO _ finish. result _ fifo _ wena is generated by fifo _ rena _ a logic or fifo _ rena _ B, and if fifo _ rena _ a is high, data _ a is selected as sorting result data result _ fifo _ wdata to be written into the sorting result storage queue, otherwise data _ B is selected.
1) If flag bits FIFO _ empty _ A, FIFO _ empty _ B and result _ FIFO _ prog _ full waiting for whether the internal FIFO of the queue to be sorted is empty are invalid, the queue a to be sorted and the queue B to be sorted both have data to be sorted, and the data _ a and the data _ B are input into a comparator, and the step 2 is skipped;
2) detecting whether a _ fifo _ finish and b _ fifo _ finish are high, and going to 3 if a _ fifo _ finish and b _ fifo _ finish are both low); jumping to 4 if one of a _ fifo _ finish and b _ fifo _ finish is high); go to 5 if a _ fifo _ finish and b _ fifo _ finish are both high);
3) waiting for K clock beat delays, then detecting the level of the A _ first signal, if the level is high, setting fifo _ rena _ B to be high, setting fifo _ rena _ A to be low, and reading next sequencing data _ B of the queue B to be sequenced; otherwise, the fifo _ rena _ a is set to be high level, the fifo _ rena _ B is set to be low level, and the data _ a to be sorted next time in the queue a to be sorted is read. Jump to step 2).
4) If a _ fifo _ finish is high and B _ fifo _ finish is low, fifo _ rena _ a is set low, go to step 6) if B _ fifo _ finish is high and a _ fifo _ finish is low, fifo _ rena _ B is set low, go to step 7).
5) Judging whether A _ first is high level, writing data _ B into a sequencing result queue if A _ first is high level, waiting for K clock delays, writing data _ A into the sequencing result queue, and setting last _ flag; and if the A _ first is in a low level, writing the data _ B into a sequencing result queue, waiting for K clock delays, writing the data _ A into the sequencing result queue, simultaneously setting a last _ flag, finishing the merging and sequencing, jumping to the step 1), and repeating the process.
6) If B _ fifo _ finish is detected to be high level, fifo _ rena _ B is set to be low level, and last _ flag is set; ending the merging and sorting, jumping to the step 1), and repeating the process. Otherwise, fifo _ rena _ B is set high.
7) If a _ fifo _ finish is detected to be high level, fifo _ rena _ A is set to be low level, and last _ flag is set; ending the merging and sorting, jumping to the step 1), and repeating the process. Otherwise, fifo _ rena _ a is set high.
Example one
Refer to fig. 2. And carrying out descending order merging and sorting on the data volume 1 of the queue A (8) to be sorted and the data volume 1 of the queue B (9) to be sorted. Defining a _ first as high, data _ a < data _ B, otherwise data _ a > -data _ B.
1) When the FIFO flag bit FIFO _ empty _ A, FIFO _ empty _ B and the result _ FIFO _ prog _ full in the queue to be sorted are both invalid, the queue A and the queue B to be sorted both have data to be sorted, and the step 2 is skipped;
2) data _ a: 8, data _ B:9, inputting the signal into a comparator, waiting for 2 clock tick delays, setting fifo _ rena _ B to be high level and fifo _ rena _ a to be low level after 4 clock tick delays when detecting that the a _ first signal is high level, and setting fifo _ rena _ B to be low level when detecting that B _ fifo _ finish is high level after 1 clock delay. After 1 clock delay, result _ fifo _ wena is set high to write data _ B into the sorting result queue. Jump to step 3).
3) Waiting for 6 clock beat delays, setting fifo _ rena _ A to be high level, detecting that a _ fifo _ finish is high level through 1 clock delay, setting fifo _ rena _ A to be low level, setting result _ fifo _ rena to be high through 1 clock delay, writing data _ A into a sequencing result queue, and setting last _ flag to finish sequencing this time.
Example II
Refer to fig. 3. And carrying out descending order merging and sorting on the data volume 1 of the queue A (8) to be sorted and the data volume 2 of the queue B (9,8) to be sorted. Defining a _ first as high, data _ a < data _ B, otherwise data _ a > -data _ B. The queue A to be sorted and the queue B to be sorted store data queues which are sorted according to a certain rule respectively.
1) When the FIFO flag bit FIFO _ empty _ A, FIFO _ empty _ B and the result _ FIFO _ prog _ full in the queue to be sorted are both invalid, the queue A and the queue B to be sorted both have data to be sorted, and the step 2 is skipped;
2) data _ a: 8, data _ B: inputting 9 into a comparator, waiting for 2 clock tick delays, detecting that the A _ first signal is high level, setting fifo _ rena _ B to high level and fifo _ rena _ A to low level after 4 clock tick delays, and reading data _ B after 1 clock delay: 8 into the comparator, reset _ fifo _ wena is set high with 2 clock delays writing data _ B:9 into the sorted result queue. Jumping to step 3);
3) when detecting that a _ first is low, setting fifo _ rena _ a to high, and after 1 clock delay, detecting that a _ fifo _ finish is high, setting fifo _ rena _ a to low, and after 1 clock delay, setting result _ fifo _ rena to high, and setting data _ a: 8, writing the data into a sequencing result queue, and jumping to the step 4);
4) waiting for 1 clock delay to set fifo _ rena _ B to high level, detecting that B _ fifo _ finish is high level after 1 clock delay, setting fifo _ rena _ B to low level, setting result _ fifo _ rena to high level after 2 clock delays, and setting data _ B: and 8, writing the sequence data into a sequencing result queue, and juxtaposing last _ flag as a high level to finish the sequencing.
Example III
Refer to fig. 4. And carrying out descending order merging and sorting on the data volume 2 of the queue A (8,7) to be sorted and the data volume 2 of the queue B (9,8) to be sorted. Defining a _ first as high, data _ a < data _ B, otherwise data _ a > -data _ B. The queue A to be sorted and the queue B to be sorted store data queues which are sorted according to a certain rule respectively.
1) When the FIFO flag bit FIFO _ empty _ A, FIFO _ empty _ B and the result _ FIFO _ prog _ full in the queue to be sorted are both invalid, the queue A and the queue B to be sorted both have data to be sorted, and the step 2 is skipped;
2) data _ a: 8, data _ B: inputting 9 into a comparator, waiting for 2 clock tick delays, detecting that the A _ first signal is high level, setting fifo _ rena _ B to high level and fifo _ rena _ A to low level after 4 clock tick delays, and reading data _ B after 1 clock delay: 8 into the comparator, reset _ fifo _ wena is set high with 2 clock delays to write data _ B:9 into the sorted result queue. Jumping to step 3);
3) detecting that A _ first is low level, setting fifo _ rena _ A to high level, inputting data _ A:7 into a comparator, setting result _ fifo _ wena to high level after 2 clock delays, and setting data _ A: and 8, writing into an ordering result queue.
4) Waiting for 1 clock delay to detect that A _ first is high level, setting fifo _ rena _ B to be high level, detecting that B _ fifo _ finish is high level after 1 clock delay, setting fifo _ rena _ B to be low level, setting result _ fifo _ wena to be high level after 2 clock delays, and setting data _ B: 8 are written into the sorted result queue. Jumping to step 4);
5) setting fifo _ rena _ a to be high level, detecting that a _ fifo _ finish is high level after 1 clock delay, setting fifo _ rena _ a to be low level, setting result _ fifo _ wena to be high after 2 clock delays, and setting data _ a: and 7, writing the sequence data into a sequencing result queue, setting last _ flag as high level, and finishing the sequencing.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (2)

1. A variable-length merging and sorting implementation method for electric power Internet of things data is characterized in that the variable-length merging and sorting implementation method for the electric power Internet of things data is implemented by adopting a sorting system, wherein the sorting system comprises a queue A to be sorted, a queue B to be sorted, a comparator, a reading control module and a sorting result storage queue; wherein the content of the first and second substances,
the queue A to be sorted and the queue B to be sorted adopt a first data pre-reading mode, data queues which are sorted according to a certain rule are respectively stored in the queue A to be sorted and the queue B to be sorted, and the queue A to be sorted and the queue B to be sorted respectively output data _ A, data _ B to be sorted and a flag last _ A, last _ B indicating whether the data to be sorted is the last data or not;
the data read out each time of the queue A to be sorted is latched with data _ A, the data read out each time of the queue B to be sorted is latched with data _ B, the data _ A and the data _ B are sent into a comparator to be compared and a comparison result is obtained, if the number of the data _ A is larger than or equal to that of the data _ B, the data _ A is written into a queue of the sorting result through a reading control module, the data _ B is latched, the data of the queue A to be sorted are continuously read and sequentially compared with the data latched data _ B of the queue B to be sorted, the comparison result is obtained, the process is repeated until the two queues to be sorted are merged into an ordered queue and stored in a queue of the sorting result, and the last data of the queue of the sorting result is set as a data flag last _ flag; the reading control module respectively outputs a write enable signal result _ fifo _ wena, sorting result data result _ fifo _ data and a last data flag last _ flag of the sorting result queue;
the comparator is used for comparing the data to be sorted data _ A and data _ B, K clock cycles are needed, and K is more than or equal to 1;
the queue A to be sorted and the queue B to be sorted output flag bits FIFO _ empty _ A, FIFO _ empty _ B which mark whether the internal FIFO of the queue to be sorted is empty, the comparator outputs a comparison result A _ first, the reading control module outputs a read enable signal FIFO _ rena _ A, FIFO _ rena _ B to the queue A to be sorted and the queue B to be sorted according to a data state signal FIFO _ empty _ A, last _ A, FIFO _ empty _ B, last _ B and an output result A _ first signal of the comparator respectively, the internal FIFO of the queue to be sorted outputs a sorting result queue full signal result _ FIFO _ prog _ full to the reading control module when the internal FIFO of the queue to be sorted is full, the FIFO _ rena _ A logic and the last _ A are set as a _ FIFO _ finish, and the FIFO _ rena _ B logic and the last _ B are set as B _ FIFO _ height; the read control module comprises the following steps:
3-1) waiting whether the flag bits FIFO _ empty _ A, FIFO _ empty _ B and result _ FIFO _ prog _ full in the queue to be sorted are invalid, if both the queue a to be sorted and the queue B to be sorted have data to be sorted, inputting the data _ a and the data _ B into a comparator, and jumping to the step 3-2);
3-2) detecting whether a _ fifo _ finish and b _ fifo _ finish are high level, and going to 3-3 if a _ fifo _ finish and b _ fifo _ finish are both low level); jumping to 3-4 if one of a _ fifo _ finish and b _ fifo _ finish is high); go to 3-5 if a _ fifo _ finish and b _ fifo _ finish are both high);
3-3) waiting for K clock beat delays, then detecting the level of the A _ first signal, if the level is high, setting fifo _ rena _ B to be high, setting fifo _ rena _ A to be low, and reading the next sorting data _ B of the queue B to be sorted; jumping to the step 3-2);
3-4) if a _ fifo _ finish is high and B _ fifo _ finish is low, fifo _ rena _ a is set low, go to step 3-6) if B _ fifo _ finish is high and a _ fifo _ finish is low, fifo _ rena _ B is set low, go to step 3-7);
3-5) judging whether A _ first is high level, if A _ first is high level, writing data _ B into a sequencing result queue, waiting for K clock delays, writing data _ A into the sequencing result queue, and simultaneously setting last _ flag; if A _ first is low level, writing data _ B into a sequencing result queue, waiting for K clock delays, writing data _ A into the sequencing result queue, simultaneously setting last _ flag, ending the merging sequencing, jumping to step 3-1), and repeating the process;
3-6) if B _ fifo _ finish is detected to be high level, setting fifo _ rena _ B as low level, simultaneously setting last _ flag, ending the merging and sorting, skipping to the step 1), and repeating the process; otherwise, fifo _ rena _ B is set to high level;
3-7) if detecting that a _ fifo _ finish is high level, setting fifo _ rena _ A to be low level, setting last _ flag, ending the merging and sorting, skipping to the step 1), and repeating the process; otherwise, fifo _ rena _ a is set high.
2. The method as claimed in claim 1, wherein the write enable signal result _ fifo _ wena signal of the sorting result storage queue is generated by logical or of the read enable signal fifo _ rena _ a and the fifo _ rena _ B signal, and if fifo _ rena _ a is high, data _ a is selected as sorting result data result _ fifo _ wdata and written into the sorting result storage queue, otherwise data _ B is selected.
CN202010196564.2A 2020-03-19 2020-03-19 Variable-length merging and sorting implementation method for electric power internet of things data Active CN111443891B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010196564.2A CN111443891B (en) 2020-03-19 2020-03-19 Variable-length merging and sorting implementation method for electric power internet of things data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010196564.2A CN111443891B (en) 2020-03-19 2020-03-19 Variable-length merging and sorting implementation method for electric power internet of things data

Publications (2)

Publication Number Publication Date
CN111443891A CN111443891A (en) 2020-07-24
CN111443891B true CN111443891B (en) 2022-07-08

Family

ID=71629345

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010196564.2A Active CN111443891B (en) 2020-03-19 2020-03-19 Variable-length merging and sorting implementation method for electric power internet of things data

Country Status (1)

Country Link
CN (1) CN111443891B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117193A (en) * 2010-01-04 2011-07-06 杭州华三通信技术有限公司 Method for implementing pre-read FIFO and pre-read FIFO
CN102750131A (en) * 2012-06-07 2012-10-24 中国科学院计算机网络信息中心 Graphics processing unit (GPU) oriented bitonic merge sort method
CN103226464A (en) * 2013-03-29 2013-07-31 江苏复芯物联网科技有限公司 Merging sort structure
CN106775573A (en) * 2016-11-23 2017-05-31 北京电子工程总体研究所 A kind of potential target sort method based on FPGA

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117193A (en) * 2010-01-04 2011-07-06 杭州华三通信技术有限公司 Method for implementing pre-read FIFO and pre-read FIFO
CN102750131A (en) * 2012-06-07 2012-10-24 中国科学院计算机网络信息中心 Graphics processing unit (GPU) oriented bitonic merge sort method
CN103226464A (en) * 2013-03-29 2013-07-31 江苏复芯物联网科技有限公司 Merging sort structure
CN106775573A (en) * 2016-11-23 2017-05-31 北京电子工程总体研究所 A kind of potential target sort method based on FPGA

Also Published As

Publication number Publication date
CN111443891A (en) 2020-07-24

Similar Documents

Publication Publication Date Title
US9866218B2 (en) Boolean logic in a state machine lattice
KR101840905B1 (en) Counter operation in a state machine lattice
US20200117977A1 (en) Methods and devices for programming a state machine engine
US20180137416A1 (en) Methods and systems for data analysis in a state machine
CN101681249B (en) Fifo buffer
US6553448B1 (en) Method for unit distance encoding of asynchronous pointers for non-power-of-two sized buffers
US10789182B2 (en) System and method for individual addressing
US20140325494A1 (en) Methods and systems for detection in a state machine
US11120867B2 (en) Hardware compression with search string matching
JP2004538592A (en) Memory engine for data inspection and manipulation
US10402265B2 (en) Validation of a symbol response memory
US10146555B2 (en) Adaptive routing to avoid non-repairable memory and logic defects on automata processor
US20130031311A1 (en) Interface apparatus, calculation processing apparatus, interface generation apparatus, and circuit generation apparatus
US9570125B1 (en) Apparatuses and methods for shifting data during a masked write to a buffer
CN111443891B (en) Variable-length merging and sorting implementation method for electric power internet of things data
US6898722B2 (en) Parallel data transfer method and system of DDR divided data with associated transfer clock signal over three signal lines
CN111541617A (en) Data flow table processing method and device for high-speed large-scale concurrent data flow
US20120023273A1 (en) Command management device configured to store and manage received commands and storage apparatus with the same
CN114780151A (en) Data sorting system for realizing variable-scale quantity based on merging sorting algorithm
WO2016109571A1 (en) Devices for time division multiplexing of state machine engine signals
CN111722829A (en) Double-concurrent pre-reading high-performance merging and sorting method and application
JP5139335B2 (en) Data search device, data search method, and data search program
US5386211A (en) Method and apparatus for recording and reconstructing binary data in a compressed form
US6925464B2 (en) Method and system for performing inserts and lookups in memory
CN105843837B (en) Hardware efficient rabin fingerprinting

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant