CN111443756A - Clock disciplining method and system for computer and equipment with hardware triggering function - Google Patents

Clock disciplining method and system for computer and equipment with hardware triggering function Download PDF

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CN111443756A
CN111443756A CN202010244967.XA CN202010244967A CN111443756A CN 111443756 A CN111443756 A CN 111443756A CN 202010244967 A CN202010244967 A CN 202010244967A CN 111443756 A CN111443756 A CN 111443756A
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computer
clock
time stamp
oscillation signal
equipment
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CN111443756B (en
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郁文贤
裴凌
刘海春
张晗
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Shanghai Beidou Navigation Innovation Research Institute
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Shanghai Beidou Navigation Innovation Research Institute
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    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12Synchronisation of different clock signals provided by a plurality of clock generators

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Abstract

The invention discloses a clock taming method and a clock taming system for a computer and equipment with a hardware triggering function, wherein an oscillation signal module is respectively connected with the computer and the equipment; the oscillation signal module outputs an oscillation signal to trigger the equipment, and simultaneously sends a communication packet to inform the computer equipment of being triggered; device records triggered time stamp by its internal clock
Figure DDA0002433750510000011
Computer records time stamp of communication packet arrival by internal clock
Figure DDA0002433750510000012
Time stamp of the measured time
Figure DDA0002433750510000013
And
Figure DDA0002433750510000014
to perform linearityRegression to obtain the linear relation; calculating new time stamp from linear relation
Figure DDA0002433750510000015
Time stamp of corresponding computer clock
Figure DDA0002433750510000016
And a new time stamp
Figure DDA0002433750510000017
Time stamp of corresponding device clock
Figure DDA0002433750510000018
The invention has the beneficial effects that: a clock disciplining method and system are provided that are capable of scaling an internal clock of a test device with hardware triggers to an internal clock of a host computer of a sensor, thereby evaluating ranging accuracy and errors of the sensor in motion.

Description

Clock disciplining method and system for computer and equipment with hardware triggering function
Technical Field
The invention relates to the technical field of sensor testing, in particular to a clock taming method and a clock taming system for a computer and equipment with a hardware triggering function.
Background
In recent years, sensors have been widely used in various fields as important measuring tools, and in the field of sensor testing, particularly testing of distance measuring sensors such as binocular cameras, it is often necessary to evaluate the distance measuring performance of the sensors during movement to determine the distance measuring accuracy and errors of the sensors during movement. The position of the target object is measured by the distance measuring equipment; when the test is started, the sensor starts to move and starts to carry out real-time distance measurement on the target object, and the distance measuring equipment tracks the position of the sensor in real time, so that the real-time true distance between the sensor and the target object can be obtained. In order to evaluate the real-time distance measurement accuracy of the sensor, the real-time distance measurement result of the sensor needs to be compared with the true value of the distance to the target object at the corresponding time.
The ranging software and algorithm of the sensor usually run on the upper computer connected with the ranging software and algorithm, while dynamic ranging devices such as laser trackers can provide real-time ranging results with high frequency and high precision, some devices also provide a hardware triggering function, but do not have a clock synchronization function, and the internal clock usually starts to calculate according to the self starting time. Therefore, in order to evaluate the distance measurement accuracy and the error of the sensor in motion, a clock disciplining method capable of converting the internal clock of the distance measurement equipment with hardware trigger and the internal clock of the upper computer of the sensor is needed.
Disclosure of Invention
This section is for the purpose of summarizing some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. In this section, as well as in the abstract and the title of the invention of this application, simplifications or omissions may be made to avoid obscuring the purpose of the section, the abstract and the title, and such simplifications or omissions are not intended to limit the scope of the invention.
The present invention has been made in view of the above-mentioned conventional problems.
Therefore, one technical problem solved by the present invention is: the clock disciplining method for the computer and the equipment with the hardware triggering function can obtain the relation between the clock of the computer and the time shown by the clock of the equipment with the hardware triggering function, thereby solving the clock disciplining problem of the computer and the equipment with the hardware triggering function.
In order to solve the technical problems, the invention provides the following technical scheme: a clock disciplining method for a computer and equipment with a hardware triggering function comprises the steps that an oscillation signal module is respectively connected with the computer and the equipment; the oscillation signal module outputs an oscillation signal to trigger the equipment, and simultaneously sends a communication packet to inform the computer equipment of being triggered; device records triggered time stamp by its internal clock
Figure BDA0002433750490000021
Computer records time stamp of communication packet arrival by internal clock
Figure BDA0002433750490000022
Time stamp of the measured time
Figure BDA0002433750490000023
And
Figure BDA0002433750490000024
performing linear regression to obtain a linear relation; calculating new time stamp from linear relation
Figure BDA0002433750490000025
Time stamp of corresponding computer clock
Figure BDA0002433750490000026
And a new time stamp
Figure BDA0002433750490000027
Time stamp of corresponding device clock
Figure BDA0002433750490000028
As a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: the oscillation signal module is connected with a computer through a communication port; and is connected with the equipment through the signal input and output end.
As a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: the device stamps its ith triggered time as
Figure BDA0002433750490000029
N points in total; the computer records the arrival time stamp of the ith communication packet
Figure BDA00024337504900000210
N total points, N being at least 2.
As a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: the time stamp
Figure BDA00024337504900000211
And
Figure BDA00024337504900000212
the linear relationship of (a) satisfies the following formula,
tC=k·tE+α+
wherein t isCTime of the computer's internal clock, tEFor the time of the device internal clock, white noise which is expected to be zero and has a finite variance, k and α are the pending slope and intercept, respectively.
As a preferred scheme of the clock disciplining method for the computer and the equipment with the hardware triggering function, the invention is characterized in that the estimated values of the slope k and the intercept α
Figure BDA00024337504900000213
And
Figure BDA00024337504900000214
obtained by solving the optimized value by the following formula,
Figure BDA00024337504900000215
as a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: the above-mentioned
Figure BDA00024337504900000216
And
Figure BDA00024337504900000217
the relationship of (a) satisfies the following formula,
Figure BDA00024337504900000218
as a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: the above-mentioned
Figure BDA00024337504900000219
And
Figure BDA00024337504900000220
the relationship of (a) satisfies the following formula,
Figure BDA00024337504900000221
as a preferred solution of the clock disciplining method for the computer and the device with the hardware triggering function, the method comprises the following steps: said calculating a new timestamp from a linear relationship
Figure BDA00024337504900000222
And
Figure BDA00024337504900000223
when i is>N。
The invention solves another technical problem that: the clock disciplining system of the computer and the equipment with the hardware triggering function is provided, so that the method can be realized by depending on the system.
In order to solve the technical problems, the invention provides the following technical scheme: a clock taming system of a computer and equipment with a hardware triggering function comprises an oscillation signal module, a clock signal processing module and a clock signal processing module, wherein the oscillation signal module can output an oscillation signal with high precision and adjustable frequency; a computer, said computer internally containing a clock; and the equipment internally comprises a clock and can be triggered by the oscillation signal output by the oscillation signal module.
As a preferred solution of the clock disciplining system for the computer and the device with the hardware triggering function, the invention is characterized in that: the oscillation signal module comprises a communication port and a signal input/output end, the communication port is connected with a computer, and the signal input/output end is connected with equipment.
The invention has the beneficial effects that: a clock disciplining method and system are provided that are capable of scaling an internal clock of a test device with hardware triggers to an internal clock of a host computer of a sensor, thereby evaluating ranging accuracy and errors of the sensor in motion.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a schematic overall flowchart of a clock disciplining method for a computer and a device with a hardware triggering function according to a first embodiment of the present invention;
FIG. 2 is a graph illustrating the fitting results of tests performed according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of an overall structure of a computer and a clock disciplining system with a hardware triggering function device according to a second embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below, and it is apparent that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and it will be apparent to those of ordinary skill in the art that the present invention may be practiced without departing from the spirit and scope of the present invention and that the present invention is not limited to the specific embodiments disclosed below.
Furthermore, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
The present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially in general scale for convenience of illustration, and the drawings are only exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Meanwhile, in the description of the present invention, it should be noted that the terms "upper, lower, inner and outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and operate, and thus, cannot be construed as limiting the present invention. Furthermore, the terms first, second, or third are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The terms "mounted, connected and connected" in the present invention are to be understood broadly, unless otherwise explicitly specified or limited, for example: can be fixedly connected, detachably connected or integrally connected; they may be mechanically, electrically, or directly connected, or indirectly connected through intervening media, or may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
Referring to the schematic diagram of fig. 1, which is an overall flowchart of a clock disciplining method for a computer and a device with a hardware trigger function provided in this embodiment, in order to implement mutual conversion between an internal clock of a testing device and an internal clock of a host computer of a sensor, the present invention implements clock conversion by calculating a relationship between time stamps of the two.
Specifically, the clock disciplining method for a computer and a device with a hardware triggering function provided in this embodiment includes,
s1: the oscillation signal module 100 is connected to the computer 200 and the device 300, respectively. The oscillation signal module 100 may be a single chip, an FPGA, a DSP, or the like, and may output an oscillation signal.
Specifically, the oscillation signal module 100 is connected to the computer 200 through a communication port 101, and the communication port 101 may be a port for communication, such as a serial port, a CAN bus, a network, or the like; the signal input/output end 102 is connected to the device 300, and the signal input/output end 102 may be an I/O port on a single chip, can be used as a communication transmission port of the oscillation signal module 100 and the computer 200, and can also be used for outputting an oscillation signal.
S2: the oscillation signal module 100 outputs an oscillation signal to trigger the device 300 and simultaneously transmits a communication packet to inform the computer 200 that the device 300 is triggered.
S3: device 300 records triggered timestamps through its internal clock
Figure BDA0002433750490000051
The computer (200) records the time stamp of the arrival of the communication packet by its internal clock
Figure BDA0002433750490000052
Wherein the device 300 time stamps its ith triggered time as
Figure BDA0002433750490000053
N points in total; the computer 200 time stamps the arrival of the ith communication packet
Figure BDA0002433750490000054
N total points, N being at least 2. Increasing the value of N can improve the accuracy of the final result.
S4: time stamp of the measured time
Figure BDA0002433750490000055
And
Figure BDA0002433750490000056
and performing linear regression to obtain a linear relation.
Specifically, the measured N pairs of time stamps
Figure BDA0002433750490000057
And
Figure BDA0002433750490000058
performing linear regression, time stamping
Figure BDA0002433750490000059
And
Figure BDA00024337504900000510
the linear relationship of (a) satisfies the following formula,
tC=k·tE+α+
wherein t isCTime of the computer's internal clock, tEFor the time of the device's internal clock, white noise with a desired zero and finite variance, k and α are the pending slope and intercept, respectively, the estimates of slope k and intercept α
Figure BDA00024337504900000511
And is obtained by solving the optimized value by the following formula,
Figure BDA00024337504900000512
wherein, solving the optimized value means solving the minimum value of the above formula, and when the value of the formula is minimum, the corresponding k and α are respectively recorded as the value
Figure BDA00024337504900000513
And
Figure BDA00024337504900000514
s5: calculating new time stamp from linear relation
Figure BDA00024337504900000515
Time stamp of corresponding computer clock
Figure BDA00024337504900000516
And a new time stamp
Figure BDA00024337504900000517
Of corresponding device clocksTime stamp
Figure BDA00024337504900000518
Wherein the new time stamp is calculated from the linear relationship
Figure BDA00024337504900000519
And
Figure BDA00024337504900000520
when i is>N。
Specifically, the estimated value by the slope k and the intercept α
Figure BDA00024337504900000521
And
Figure BDA00024337504900000522
performing a calculation of
Figure BDA00024337504900000523
And
Figure BDA00024337504900000524
the relationship of (a) satisfies the following formula,
Figure BDA00024337504900000525
the above-mentioned
Figure BDA00024337504900000526
And
Figure BDA00024337504900000527
the relationship of (a) satisfies the following formula,
Figure BDA00024337504900000528
according to the two formulas, the correlation between the time shown by the computer clock and the time shown by the equipment clock can be obtained, and the clock disciplining process is completed.
Scene one:
because a large part of sensors such as a binocular camera do not have a hardware triggering function, the upper computer connected with the sensors is difficult to synchronize with a clock of equipment with the hardware triggering function. The present embodiment proposes a clock taming method for a computer and a device with a hardware trigger function, which aims to synchronize clocks of a sensor without a hardware trigger function, a host computer thereof, and a device with a hardware trigger function, such as a laser tracker.
In order to embody the advantages of the clock taming method improved by the embodiment, a distance measurement precision test of the binocular camera in a motion state is taken as an example, and a specific implementation mode and a result thereof are described and observed. The purpose of taking the measurement precision test of the binocular camera in the motion state as an example is to make the objects, features and advantages of the method described in the embodiment more understandable, but the method described in the embodiment may be presented in different forms and is not limited by the specific implementation manner in this example.
During testing, an STM32 single chip microcomputer is selected as an oscillation signal module 100, the STM32 single chip microcomputer is respectively connected with a laser tracker and a computer 200, the STM32 single chip microcomputer can output square wave signals, and when the square wave signals are converted from high level to low level, the STM32 simultaneously sends a byte data packet to the upper computer 200 through an RS232 serial port to inform the computer 200 that the laser tracker is triggered.
The computer 200 records the time stamp of the receipt of an STM32 packet, with the ith time stamp being
Figure BDA0002433750490000061
10000 points in total; the laser tracker is triggered by the falling edge to output measurement data with time stamp, and the time stamp of the ith data is
Figure BDA0002433750490000062
10000 points in total.
10000 pairs of time stamps
Figure BDA0002433750490000063
And
Figure BDA0002433750490000064
performing linear regression to make the time of the internal clock of the computer 200 and the time of the internal clock of the laser tracker in a linear relationship tC=k·tE+ α +, k and α are the pending slopes and intercepts, respectively, by solving the following optimization problem,
Figure BDA0002433750490000065
estimate of slope k and intercept α is determined
Figure BDA0002433750490000066
And
Figure BDA0002433750490000067
new time stamp for each data measured by laser tracker under test
Figure BDA0002433750490000068
Or new time stamp of upper computer clock
Figure BDA0002433750490000069
(where i > N) can be determined by estimating the slope k and intercept α
Figure BDA00024337504900000610
And
Figure BDA00024337504900000611
calculating timestamps of corresponding computer clocks
Figure BDA00024337504900000612
Or time stamp of corresponding device clock
Figure BDA00024337504900000613
Figure BDA00024337504900000614
Figure BDA00024337504900000615
The resulting fit is shown in FIG. 2 below, and the new 1000 sets of data are additionally used to verify the fit, i.e., calculated
Figure BDA0002433750490000071
The maximum value of the 1000 error values is about 4.6ms, and it can be seen that the clock disciplining method provided by the embodiment has better accuracy, and the method is effective and feasible.
Example 2
Referring to the schematic diagram of fig. 3, which is a schematic diagram illustrating an overall structure of a clock disciplining system of a computer and a device with a hardware trigger function according to this embodiment, the clock disciplining method of the computer and the device with the hardware trigger function in the foregoing embodiment can be implemented by relying on the system. The system comprises an oscillation signal module 100, a computer 200 and a device 300, wherein the oscillation signal module 100 can output an oscillation signal with high precision and adjustable frequency; the computer 200 internally contains a clock; the device 300 includes a clock therein, which can be triggered by the oscillation signal output from the oscillation signal module 100.
Specifically, the oscillation signal module 100 includes a communication port 101 and a signal input/output terminal 102, the communication port 101 is connected to the computer 200, and the signal input/output terminal 102 is connected to the device 300. The oscillation signal module 100 may be a module having a high-precision oscillation signal output capability, such as a single chip microcomputer, a DSP, or an FPGA, and capable of communicating with the computer 200 and the device 300; the communication port 101 may be a serial port, a network port, a CAN port or the like on the single chip microcomputer for communication, and the signal input/output terminal 102 may be a port of an I/O port or the like on the single chip microcomputer.
The computer 200 internally comprises a clock which can be connected with the oscillation signal connecting module 100 and the equipment 300; the device 300 may be a sensor that also contains a clock internally.
The operation flow of the system is as follows:
the method comprises the following steps: connecting the test sensor with a computer 200, and connecting the oscillation signal module 100 with the computer 200;
step two: the oscillation signal module 100 triggers the device 300 by outputting an oscillation signal, and transmits a communication packet to the computer 200;
step three: internal clock of device 300 records triggered timestamps
Figure BDA0002433750490000072
The internal clock of the computer 200 records the time stamp of the arrival of the communication packet
Figure BDA0002433750490000073
Step four: calculating timestamps
Figure BDA0002433750490000074
And
Figure BDA0002433750490000075
the linear relationship of (a);
step five: calculating new time stamp from linear relation
Figure BDA0002433750490000076
Time stamp of corresponding computer clock
Figure BDA0002433750490000077
And a new time stamp
Figure BDA0002433750490000078
Time stamp of corresponding device clock
Figure BDA0002433750490000079
And finishing the clock taming process.
It should be recognized that embodiments of the present invention can be realized and implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with the computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner, according to the methods and figures described in the detailed description. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or combinations thereof. The computer program includes a plurality of instructions executable by one or more processors.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein. A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display.
As used in this application, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being: a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of example, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
It should be noted that the above-mentioned embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.

Claims (10)

1. A clock disciplining method for a computer and a device with a hardware triggering function is characterized in that: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
the oscillation signal module (100) is respectively connected with the computer (200) and the equipment (300);
the oscillation signal module (100) outputs an oscillation signal to trigger the equipment (300), and simultaneously sends a communication packet to inform the computer (200) that the equipment (300) is triggered;
the device (300) records the triggered time stamp by its internal clock
Figure FDA0002433750480000011
The computer (200) records the time stamp of the arrival of the communication packet by its internal clock
Figure FDA0002433750480000012
Time stamp of the measured time
Figure FDA0002433750480000013
And
Figure FDA0002433750480000014
performing linear regression to obtain a linear relation;
calculating new time stamp from linear relation
Figure FDA0002433750480000015
Time stamp of corresponding computer clock
Figure FDA0002433750480000016
And a new time stamp
Figure FDA0002433750480000017
Time stamp of corresponding device clock
Figure FDA0002433750480000018
2. The clock disciplining method for a computer and a device with a hardware trigger function as claimed in claim 1, wherein: the oscillation signal module (100) is connected with a computer (200) through a communication port (101); is connected with the equipment (300) through the signal input and output end (102).
3. The clock disciplining method for a computer and a device with a hardware trigger function as claimed in claim 2, wherein: the device (300) time-stamps its ith triggered time as
Figure FDA0002433750480000019
N points in total; the computer (200) time stamps the arrival of the ith communication packet
Figure FDA00024337504800000110
N total points, N being at least 2.
4. The clock disciplining method for a computer and a device with a hardware trigger function as claimed in claim 3, wherein: the time stamp
Figure FDA00024337504800000111
And
Figure FDA00024337504800000112
the linear relationship of (a) satisfies the following formula,
tC=k·tE+α+
wherein t isCTime of the computer's internal clock, tEFor the time of the device internal clock, white noise which is expected to be zero and has a finite variance, k and α are the pending slope and intercept, respectively.
5. The clock disciplining method for computers and devices with hardware triggering functions as claimed in claim 4, wherein the estimated values of slope k and intercept α
Figure FDA00024337504800000113
And
Figure FDA00024337504800000114
obtained by solving the optimized value by the following formula,
Figure FDA00024337504800000115
6. the clock disciplining method for a computer and a device with a hardware trigger function as claimed in claim 5, wherein: the above-mentioned
Figure FDA00024337504800000116
And
Figure FDA00024337504800000117
the relationship of (a) satisfies the following formula,
Figure FDA00024337504800000118
7. the clock disciplining method for a computer and a device with a hardware trigger function as claimed in claim 6, wherein: the above-mentioned
Figure FDA00024337504800000119
And
Figure FDA00024337504800000120
the relationship of (a) satisfies the following formula,
Figure FDA0002433750480000021
8. the computer and clock taming party with hardware triggering function device as claimed in claim 6 or 7The method is characterized in that: said calculating a new timestamp from a linear relationship
Figure FDA0002433750480000022
And
Figure FDA0002433750480000023
when i is>N。
9. A clock taming system of a computer and a device with a hardware triggering function is characterized in that: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
an oscillation signal module (100), wherein the oscillation signal module (100) can output an oscillation signal with high precision and adjustable frequency;
a computer (200), said computer (200) internally containing a clock;
a device (300), said device (300) comprising internally a clock, capable of being triggered by an oscillating signal output by an oscillating signal module (100).
10. A clock taming system of a computer and a device with a hardware triggering function is characterized in that: the oscillating signal module (100) comprises a communication port (101) and a signal input/output terminal (102),
the communication port (101) is connected with a computer (200), and the signal input/output end (102) is connected with equipment (300).
CN202010244967.XA 2020-03-31 2020-03-31 Clock disciplining method and system for computer and equipment with hardware triggering function Active CN111443756B (en)

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