CN111443132A - Ultrasonic emission control circuit and ultrasonic imaging system - Google Patents
Ultrasonic emission control circuit and ultrasonic imaging system Download PDFInfo
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- G—PHYSICS
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/22—Details, e.g. general constructional or apparatus details
- G01N29/24—Probes
- G01N29/2406—Electrostatic or capacitive probes, e.g. electret or cMUT-probes
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/08—Detecting organic movements or changes, e.g. tumours, cysts, swellings
- A61B8/0833—Detecting organic movements or changes, e.g. tumours, cysts, swellings involving detecting or locating foreign bodies or organic structures
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/08—Detecting organic movements or changes, e.g. tumours, cysts, swellings
- A61B8/0866—Detecting organic movements or changes, e.g. tumours, cysts, swellings involving foetal diagnosis; pre-natal or peri-natal diagnosis of the baby
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- G01N29/04—Analysing solids
- G01N29/06—Visualisation of the interior, e.g. acoustic microscopy
- G01N29/0654—Imaging
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- G01N29/34—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor
- G01N29/341—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor with time characteristics
- G01N29/343—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor with time characteristics pulse waves, e.g. particular sequence of pulses, bursts
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- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/34—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor
- G01N29/346—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor with amplitude characteristics, e.g. modulated signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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Abstract
The invention discloses an ultrasonic emission control circuit and an ultrasonic imaging system, comprising: the control circuit comprises a first control circuit, a plurality of second control circuits and a third control circuit. The first control circuit stores a weighting coefficient in advance, and the signal flow among the first control circuit, the second control circuit and the third control circuit is used, so that the bias voltage signal provided for the ultrasonic probe can be adjusted according to the weighting coefficient, the intensities of ultrasonic waves emitted by all parts of the ultrasonic probe are different, amplitude apodization of an ultrasonic emission sound field is realized, and the difficulty in post-data processing is reduced.
Description
Technical Field
The invention relates to the technical field of ultrasonic detection, in particular to an ultrasonic emission control circuit and an ultrasonic imaging system.
Background
The ultrasonic imaging technology is widely applied to the fields of industry, medicine and the like. In practical application, the ultrasonic imaging method is often used to judge the position, size and shape of the viscera, determine the range and physical properties of the lesion, provide anatomical maps of some glandular tissues, and identify the normality and abnormality of the fetus. And, can also be used to inspect materials and workpieces.
Disclosure of Invention
The embodiment of the invention provides an ultrasonic emission control circuit and an ultrasonic imaging system, which can adjust the intensity of ultrasonic waves emitted by each part of an ultrasonic probe.
Accordingly, an embodiment of the present invention provides an ultrasound emission control circuit, including: a first control circuit, a plurality of second control circuits, and a third control circuit; wherein: the first control circuit is electrically connected with the plurality of second control circuits, and the plurality of second control circuits are electrically connected with the third control circuit;
the first control circuit is configured to generate a plurality of first control signals according to a pre-stored weighting coefficient and supply the plurality of first control signals to the plurality of second control circuits; wherein one of the second control circuits correspondingly receives one of the first control signals;
each of the second control circuits is configured to generate a second control signal from the received first control signal and provide the second control signal to the third control circuit;
the third control circuit is configured to generate a bias voltage signal corresponding to each of the second control signals one to one from each of the received second control signals and supply the bias voltage signal to the ultrasonic probe.
Optionally, the second control circuit comprises a digital-to-analog converter and an adjustable high voltage module; wherein:
the digital-to-analog converter is configured to generate an intermediate control signal according to a first control signal provided by the first control circuit and provide the intermediate control signal to the adjustable high voltage module;
the adjustable high voltage module is configured to generate the second control signal from the intermediate control signal and provide the second control signal to the third control circuit.
Optionally, the second control circuit further comprises a channel selection module; the ultrasonic probe comprises a plurality of array elements, and one array element group comprises at least two array elements;
the channel selection module is configured to provide the bias voltage generated by the third control circuit to different array elements in a plurality of drive phases.
Optionally, the ultrasonic emission control circuit further comprises a pulse circuit;
the first control circuit is further configured to generate a pulse control signal and provide the pulse control signal to the pulse circuit;
the pulse circuit is configured to generate a drive pulse signal in accordance with a pulse control signal supplied from the first control circuit and supply the drive pulse signal to the ultrasonic probe.
Optionally, the ultrasonic emission control circuit further includes a first power supply module, and the first power supply module is configured to generate a voltage for supplying power to the first control circuit, the second control circuit, and the third control circuit according to a power supply voltage.
Correspondingly, an embodiment of the present invention further provides an ultrasound imaging system, including: an ultrasonic probe, and any of the ultrasonic emission control circuits described above.
Optionally, the ultrasound imaging system further comprises: a power supply module; the power supply module is used for receiving the voltage of the power supply end and generating power supply voltage according to the voltage of the power supply end.
Optionally, the supply voltage includes a first sub-supply voltage and a plurality of second sub-supply voltages, and the power module specifically includes:
a first voltage conversion module configured to receive a voltage of a power source terminal and generate an intermediate voltage according to the voltage of the power source terminal;
a first power supply module configured to receive the intermediate voltage and generate the first sub-supply voltage from the intermediate voltage;
a second power module configured to receive the intermediate voltage and generate the plurality of second sub-supply voltages from the intermediate voltage.
Optionally, the method further comprises: an ultrasonic receiving circuit; the ultrasonic wave receiving circuit is configured to receive an ultrasonic wave reflected by an object.
Optionally, the ultrasonic probe is a capacitive micromachined ultrasonic transducer.
The invention has the following beneficial effects:
the embodiment of the invention provides an ultrasonic emission control circuit and an ultrasonic imaging system, which comprise: the control circuit comprises a first control circuit, a plurality of second control circuits and a third control circuit. The first control circuit stores a weighting coefficient in advance, and the signal flow among the first control circuit, the second control circuit and the third control circuit is used, so that the bias voltage signal provided for the ultrasonic probe can be adjusted according to the weighting coefficient, the intensities of ultrasonic waves emitted by all parts of the ultrasonic probe are different, amplitude apodization of an ultrasonic emission sound field is realized, and the difficulty in post-data processing is reduced.
Drawings
Fig. 1 is a schematic structural diagram of an ultrasonic emission control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another ultrasonic emission control circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an adjustable high-voltage module according to an embodiment of the present invention;
fig. 5 is a schematic view of an ultrasonic probe according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In ultrasonic imaging, in order to improve the imaging quality, an amplitude apodization method may be generally employed. However, in the ultrasonic imaging system using the piezoelectric ceramics as the ultrasonic probe in the related art, since it is complicated to perform the apodization of the transmission amplitude by controlling the transmission sound field, the amplitude apodization is generally performed when the ultrasonic waves are received and data processing is performed.
An ultrasonic emission control circuit provided in an embodiment of the present invention, as shown in fig. 1, includes: a first control circuit 10, a plurality of second control circuits 20, and a third control circuit 30; wherein: the first control circuit 10 is electrically connected to the plurality of second control circuits 20, and the plurality of second control circuits 20 is electrically connected to the third control circuit 30;
the first control circuit 10 is configured to generate a plurality of first control signals according to weighting coefficients stored in advance, and supply the plurality of first control signals to the plurality of second control circuits 20; wherein, a second control circuit 20 correspondingly receives a first control signal;
each second control circuit 20 is configured to generate a second control signal from the received first control signal and supply the second control signal to the third control circuit 30;
the third control circuit 30 is configured to generate bias voltage signals corresponding one-to-one to the respective second control signals from the received respective second control signals, and supply the bias voltage signals to the ultrasonic probe 40.
According to the ultrasonic wave emission control circuit provided by the embodiment of the invention, the weighting coefficient is prestored in the first control circuit, and the bias voltage signal provided for the ultrasonic wave probe can be adjusted according to the weighting coefficient through the signal flow among the first control circuit, the second control circuit and the third control circuit, so that the intensities of ultrasonic waves emitted by all parts of the ultrasonic wave probe are different, amplitude apodization of an ultrasonic wave emission sound field is realized, and the difficulty in later-stage data processing is reduced.
In specific implementation, the weighting coefficients pre-stored in the first control circuit 10 may be calculated according to an amplitude apodization function, and the commonly used amplitude apodization functions include a Hanning window function, a Hamming window function, and a Blackman window function.
In a specific implementation, the first control circuit 10 may be a Field Programmable Gate Array (FPGA), and the third control circuit 30 may be a transmission control chip. The emission control chip may generate the bias voltage signal according to the second control signal, and the specific structure thereof may be substantially the same as that in the related art, which is not described herein.
In specific implementation, in the embodiment of the present invention, as shown in fig. 2, the second control circuit 20 may include a digital-to-analog converter 21 and an adjustable high voltage module 22; wherein:
the digital-to-analog converter 21 is configured to generate an intermediate control signal according to the first control signal provided by the first control circuit 10 and provide the intermediate control signal to the adjustable high voltage module 22;
the adjustable high voltage module 22 is configured to generate a second control signal from the intermediate control signal and provide the second control signal to the third control circuit 30.
In a specific implementation, as shown in fig. 3, the digital-to-analog converter 21 may include a first chip U1, first to eighth digital-to-analog resistors Rda1 to Rda8, and a capacitor C, wherein the first chip U1 has 20 pins, a first pin DB7 is electrically connected to the first digital-to-analog input DAC _ D7, a second pin DB6 is electrically connected to the second digital-to-analog input DAC _ D6, a third pin DB5 is electrically connected to the third digital-to-analog input DAC _ D5, a fourth pin DB4 is electrically connected to the fourth digital-to-analog input DAC _ D4, a fifth pin DB3 is electrically connected to the fifth digital-to-analog input DAC _ D3, a sixth pin DB2 is electrically connected to the sixth digital-to-analog input DAC _ D2, a seventh pin DB1 is electrically connected to the seventh digital-to DAC 1, an eighth pin DB0 is electrically connected to the eighth digital-to DAC _ D0, a ninth pin CS is electrically connected to the ninth digital-to the ninth digital input DAC CS, a tenth pin DB0 is electrically connected to the thirteenth pin DB0, a fourteenth pin DB0 is electrically connected to the fourteenth pin DB 72, a fourteenth pin DB0 is electrically connected to the fourteenth digital-to the fourteenth digital input DAC n pin gnd terminal, a fourteenth pin rd pin 0, a fourteenth pin rd of the DAC 0, a fourteenth digital-DAC 0, a fourteenth pin rd pin is electrically connected to the DAC n pin 0, a fourteenth pin rd pin 36.
A first terminal of the first digital-to-analog resistor Rda1 is electrically connected to the first power voltage terminal VCC, and a second terminal of the first digital-to-analog resistor Rda1 is electrically connected to the ninth pin CS.
A first terminal of the second digital-mode resistor Rda2 is electrically connected to the first power voltage terminal VCC, and a second terminal of the second digital-mode resistor Rda2 is electrically connected to the tenth pin WR.
A second terminal of the third digital-to-analog resistor Rda3 is electrically connected to the digital-to-analog output DAC _ OUT.
A first terminal of the fourth digital-to-analog resistor Rda4 is electrically connected to the reference voltage terminal VREF, and a second terminal of the fourth digital-to-analog resistor Rda4 is electrically connected to the sixteenth pin REFIN.
A first terminal of the sixth digital-to-analog resistor Rda6 is electrically connected to the thirteenth pin L DAC, and a second terminal of the sixth digital-to-analog resistor Rda6 is electrically connected to the ground terminal.
A first end of the seventh digital-to-analog resistor Rda7 is electrically connected to the first power voltage terminal VCC, and a second end of the seventh digital-to-analog resistor Rda7 is electrically connected to the fourteenth pin C L R.
A first end of the eighth digital-to-analog resistor Rda8 is electrically connected to the first power voltage VCC, and a second end of the eighth digital-to-analog resistor Rda8 is electrically connected to the twelfth pin PD.
A first terminal of the capacitor C is electrically connected to the twentieth pin DGND, and a second terminal of the capacitor C is electrically connected to the digital-to-analog output terminal DAC _ OUT.
Specifically, the signal voltage of the first power voltage terminal VCC may be 3.3V; the first digital-to-analog resistor Rda1, the second digital-to-analog resistor Rda2, the sixth digital-to-analog resistor Rda6, the seventh digital-to-analog resistor Rda7, and the eighth digital-to-analog resistor Rda8 may be resistors of 4.7K Ω; the capacitance of the capacitor C may be 0.1 microfarads. Of course, the digital-to-analog converter 21 may have other structures known to those skilled in the art, and is not limited herein.
It should be noted that the signals loaded on the first DAC _ D7 to the fourteenth DAC _ C L R are all provided by the first control circuit 10 to control the DAC 21 to provide the intermediate control signal to the adjustable high voltage module 22 through the DAC _ OUT, in practical implementation, the voltage of the intermediate control signal output by the DAC 21 may be a variable voltage of 0 to 2V.
In a specific implementation, as shown in fig. 4, the adjustable high voltage module 22 may include a second chip U2, a first resistor R1 to a ninth resistor R9, a first capacitor C1 to a twelfth capacitor C12, a first inductor L1, a second inductor L2, a third inductor L3, a first zener diode D1, a second zener diode D2, and a transistor q, wherein the second chip U2 has 11 pins, and the 11 pins include a first pin VC, a second pin FBX, a third pin SS, a fourth pin RT, a fifth pin SYNC, a sixth pin SENSE, a seventh pin GATE, an eighth pin INTVCC, a ninth pin SHDN, a tenth pin VIN, and an eleventh pin L PAD.
The first end of the first capacitor C1 is electrically connected to the first pin VC, and the second end of the first capacitor C1 is electrically connected to the third pin SS.
A first end of the first resistor R1 is electrically connected to the first pin VC, a second end of the first resistor R1 is electrically connected to a first end of the second capacitor C2, a second end of the second capacitor C2 is electrically connected to a first end of the third capacitor C3, and a second end of the third capacitor C3 is electrically connected to the third pin SS.
A first terminal of the second resistor R2 is electrically connected to the fourth pin RT, and a second terminal of the second resistor R2 is electrically connected to a first terminal of the third capacitor C3.
A first end of the third resistor R3 is electrically connected to the fifth pin SYNC, and a second end of the third resistor R3 is electrically connected to the ground GND.
A first end of the fourth resistor R4 is electrically connected to the ninth pin SHDN, and a second end of the fourth resistor R4 is electrically connected to the ground GND.
A first end of the fifth resistor R5 is electrically connected to the ninth pin SHDN, and a second end of the fifth resistor R5 is electrically connected to the tenth pin VIN.
A first terminal of the fourth capacitor C4 is electrically connected to the eighth pin INTVCC, and a second terminal of the fourth capacitor C4 is electrically connected to the ground GND.
A first terminal of the first inductor L1 is electrically connected to the first input signal terminal Vin1, a second terminal of the first inductor L1 is electrically connected to the first terminal of the transistor Q, and the first input signal terminal Vin1 is electrically connected to the tenth pin Vin.
A control terminal of the transistor Q is electrically connected to the seventh pin GATE, and a second terminal of the transistor Q is electrically connected to the sixth pin SENSE.
A first end of the sixth resistor R6 is electrically connected to the sixth pin SENSE, and a second end of the sixth resistor R6 is electrically connected to the ground GND.
The first terminal of the fifth capacitor C5 is electrically connected to the first input signal terminal Vin1, and the second terminal of the fifth capacitor C5 is electrically connected to the ground GND.
A first terminal of the sixth capacitor C6 is electrically connected to the first terminal of the transistor Q, and a second terminal of the sixth capacitor C6 is electrically connected to the first terminal of the first zener diode D1.
A first terminal of the seventh capacitor C7 is electrically connected to the first terminal of the transistor Q, and a second terminal of the seventh capacitor C7 is electrically connected to the first terminal of the second zener diode D2.
The first terminal of the eighth capacitor C8 is electrically connected to the first input signal terminal Vin1, and the second terminal of the eighth capacitor C8 is electrically connected to the ground GND.
A first terminal of the first zener diode D1 is electrically connected to the first terminal of the second inductor L2, a second terminal of the first zener diode D1 is electrically connected to the second output signal terminal Vout2, and a second terminal of the second inductor L2 is electrically connected to the ground GND.
The first terminal of the seventh resistor R7 is electrically connected to the second pin FBX, and the second terminal of the seventh resistor R7 is electrically connected to the second output signal terminal Vout 2.
The first terminal of the eighth resistor R8 is electrically connected to the second input signal terminal Vin2, and the second terminal of the eighth resistor R8 is electrically connected to the second pin FBX.
The first terminal of the ninth resistor R9 is electrically connected to the second pin FBX, and the second terminal of the ninth resistor R9 is electrically connected to ground.
A first terminal of the second zener diode D2 is electrically connected to the first terminal of the third inductor L3, and a second terminal of the second zener diode D2 is electrically connected to the ground GND.
The second terminal of the third inductor L3 is electrically connected to the first output signal terminal Vout 1.
A first terminal of the ninth capacitor C9 is electrically connected to the first output signal terminal Vout1, and a second terminal of the ninth capacitor C9 is electrically connected to the ground GND.
A first terminal of the tenth capacitor C10 is electrically connected to the first output signal terminal Vout1, and a second terminal of the tenth capacitor C10 is electrically connected to the ground GND.
A first end of the eleventh capacitor C11 is electrically connected to the second output signal terminal Vout2, and a first end of the eleventh capacitor C11 is electrically connected to the ground GND.
A first terminal of the twelfth capacitor C12 is electrically connected to the second output signal terminal Vout2, and a second terminal of the twelfth capacitor C12 is electrically connected to the ground GND.
The eleventh pin L PAD is electrically connected to the ground GND.
It should be noted that the adjustable high voltage module 22 shown in fig. 4 has two output terminals, i.e. the first output signal terminal Vout1 and the second output signal terminal Vout2, through which the adjustable high voltage module 22 provides the second control signal to the third control circuit 30. The second control signal may include two voltage signals, a positive voltage signal and a negative voltage signal, which are respectively outputted through the two output terminals. As shown in fig. 4, in the adjustable high voltage module 22, the second input signal terminal Vin2 is configured to receive the intermediate control signal output by the digital-to-analog converter 21 through the digital-to-analog output terminal DAC _ OUT.
In a specific implementation, the voltage of the second control signal may be a variable voltage of ± 30V to ± 100V.
In practical implementation, in the embodiment of the present invention, the second control circuit 20 may further include a channel selection module; the ultrasonic probe 40 includes a plurality of array elements, and one array element group includes at least two array elements;
the channel selection module is configured to provide the bias voltage generated by the third control circuit 30 to different sets of the array elements in a plurality of drive phases.
In a specific implementation, the third control circuit 30 outputs the bias voltage through a plurality of bias voltage elements, and the channel selection module may electrically connect the third control circuit 30 with a plurality of array element groups included in the ultrasound probe 40, specifically, one bias voltage element is electrically connected with an array element in one array element group under the control of the channel selection module, so as to provide one bias voltage to the array element in one array element group. The specific structure of the channel selection module may be substantially the same as that in the related art, and is not described herein again.
In practical implementation, in the embodiment of the present invention, the ultrasonic emission control circuit may further include a pulse circuit; the first control circuit 10 is further configured to generate a pulse control signal and supply the pulse control signal to the pulse circuit; the pulse circuit is configured to generate a drive pulse signal in accordance with the pulse control signal supplied from the first control circuit 10 and supply the drive pulse signal to the ultrasonic probe 40. The ultrasonic probe 40 transmits ultrasonic waves through each array element group in accordance with the received drive pulse signal and bias voltage.
In practical implementation, in the embodiment of the present invention, the ultrasonic wave emission control circuit may further include a first power supply module, and the first power supply module is configured to generate a voltage for supplying power to the first control circuit 10, the second control circuit 20, and the third control circuit 30 according to the power supply voltage.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The operation of the ultrasonic emission control circuit provided in the embodiment of the present invention will be described below by taking the ultrasonic emission control circuit shown in fig. 2, the digital-to-analog converter 21 shown in fig. 3, the adjustable high voltage module 22 shown in fig. 4, and the ultrasonic probe 40 shown in fig. 5 as examples. The first control circuit 10 is a field programmable gate array, and for the ultrasonic probe 40 including 8 array elements, weighting coefficients calculated by using a Hanning window function as an amplitude apodization function are 0.08, 0.25, 0.64, 0.95, 0.64, 0.25, and 0.08. After the integer number, the weighting coefficients 1, 3, 8, and 24 can be obtained.
The first control circuit 10 generates four first control signals according to the pre-stored weighting factors 1, 3, 8, 24 and supplies the four first control signals to the digital-to-analog converters 21 of the four second control circuits 20 through the first digital-to-analog input DAC _ D7 to the fourteenth digital-to-analog input DAC _ C L R of the digital-to-analog converter 21, wherein the first control signal generated according to the weighting factor 1 is referred to as a first control signal M1, the first control signal generated according to the weighting factor 3 is referred to as a first control signal M3, the first control signal generated according to the weighting factor 8 is referred to as a first control signal M8, and the first control signal generated according to the weighting factor 24 is referred to as a first control signal M24.
The digital-to-analog converters 21 respectively generate intermediate control signals according to the received first control signals, and provide the intermediate control signals to the adjustable high voltage module 22 in the same second control circuit 20 through the digital-to-analog output terminal DAC _ OUT. The intermediate control signal generated from the first control signal M1 is referred to as an intermediate control signal N1, the intermediate control signal generated from the first control signal M3 is referred to as an intermediate control signal N3, the intermediate control signal generated from the first control signal M8 is referred to as an intermediate control signal N8, and the intermediate control signal generated from the first control signal M24 is referred to as an intermediate control signal N24.
Each of the tunable high voltage modules 22 receives the intermediate control signal through the second input signal terminal Vin2, generates a second control signal according to the intermediate control signal, and provides the second control signal to the third control circuit 30. The second control signal generated from the intermediate control signal N1 is referred to as a second control signal P1, the second control signal generated from the intermediate control signal N3 is referred to as a second control signal P3, the second control signal generated from the intermediate control signal N8 is referred to as a second control signal P8, and the second control signal generated from the intermediate control signal N24 is referred to as a second control signal P24.
The third control circuit 30 receives all the second control signals and generates a bias voltage signal according to each second control signal, and the channel selection module electrically connects the third control circuit 30 with the ultrasonic probe 40 to provide the bias voltage signal to the array elements in the corresponding array element group. Here, the bias voltage signal generated according to the second control signal P1 is referred to as a bias voltage signal Q1, the bias voltage signal generated according to the second control signal P3 is referred to as a bias voltage signal Q3, the bias voltage signal generated according to the second control signal P8 is referred to as a bias voltage signal Q8, and the bias voltage signal generated according to the second control signal P24 is referred to as a bias voltage signal Q24.
The multiple array elements included in the ultrasonic probe 40 shown in fig. 5 are divided into a middle array element and multiple side array elements, the ultrasonic probe 40 shown in fig. 5 includes 8 array elements, which are sequentially a first array element a1 to an eighth array element A8 from top to bottom, then a fourth array element a4 and a fifth array element a5 are used as a middle array element, a third array element A3 and a sixth array element a6 are used as a first side array element, a second array element a2 and a seventh array element a7 are used as a second side array element, and a first array element a1 and an eighth array element A8 are used as a third side array element. The third control circuit 30 provides a bias voltage signal Q24 to the middle array element, a bias voltage signal Q8 to the first side array element, a bias voltage signal Q3 to the second side array element, and a bias voltage signal Q1 to the third side array element under the control of the channel selection module, so that the array elements of the ultrasonic probe 40 generate ultrasonic waves of different intensities.
Specifically, when the sound pressure reflects the intensity of the ultrasonic wave, the middle portion of the ultrasonic probe 40 may be caused to emit an ultrasonic wave with a high sound pressure, and the side portion of the ultrasonic probe 40 may be caused to emit an ultrasonic wave with a low sound pressure, and the sound pressure ratios of the ultrasonic waves emitted from the middle array group, the first side array group, the second side array group, and the third side array group may be: 24:8:3:1, i.e. transmit amplitude apodization is achieved by transmitting the sound field.
Based on the same inventive concept, the embodiment of the invention also provides an ultrasonic imaging system, which comprises the ultrasonic probe and any one of the ultrasonic emission control circuits.
In practical implementation, in an embodiment of the present invention, the ultrasound imaging system further includes: a power supply module; the power supply module is used for receiving the voltage of the power supply end and generating a power supply voltage according to the voltage of the power supply end. And the power supply module provides the supply voltage to the first power supply module.
In a specific implementation, in an embodiment of the present invention, the supply voltage may include a first sub-supply voltage and a plurality of second sub-supply voltages, and the power module may specifically include:
a first voltage conversion module configured to receive the voltage of the power source terminal and generate an intermediate voltage according to the voltage of the power source terminal;
a first power supply module configured to receive the intermediate voltage and generate a first sub-supply voltage from the intermediate voltage;
a second power supply module configured to receive the intermediate voltage and generate a plurality of second sub-supply voltages from the intermediate voltage.
In a specific implementation, the intermediate voltage generated by the first voltage conversion module may be ± 15V; the first power supply module may generate a first sub power supply voltage according to the voltage of ± 15V, and the first power supply module may generate a voltage for supplying power to the third control circuit according to the received first sub power supply voltage; the plurality of first sub power supply voltages generated by the second power supply module according to the ± 15V voltage may include a 10V voltage, a 5V voltage, and a 3.3V voltage, and the second power supply module may generate a voltage for supplying power to the first control circuit and the second control circuit according to the received plurality of second sub power supply voltages.
In practical implementation, in an embodiment of the present invention, the ultrasound imaging system further includes: an ultrasonic receiving circuit; the ultrasonic wave receiving circuit is configured to receive an ultrasonic wave reflected by an object. The specific structure and operation principle of the ultrasonic receiving circuit may be the same as those in the related art, and are not described herein again.
In specific implementation, in the embodiment of the present invention, the ultrasonic probe is a Capacitive Micromachined Ultrasonic Transducer (CMUT).
The embodiment of the invention provides an ultrasonic emission control circuit and an ultrasonic imaging system, which comprise: the control circuit comprises a first control circuit, a plurality of second control circuits and a third control circuit. The first control circuit stores a weighting coefficient in advance, and the signal flow among the first control circuit, the second control circuit and the third control circuit is used, so that the bias voltage signal provided for the ultrasonic probe can be adjusted according to the weighting coefficient, the intensities of ultrasonic waves emitted by all parts of the ultrasonic probe are different, amplitude apodization of an ultrasonic emission sound field is realized, and the difficulty in post-data processing is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An ultrasonic wave emission control circuit, comprising: a first control circuit, a plurality of second control circuits, and a third control circuit; wherein: the first control circuit is electrically connected with the plurality of second control circuits, and the plurality of second control circuits are electrically connected with the third control circuit;
the first control circuit is configured to generate a plurality of first control signals according to a pre-stored weighting coefficient and supply the plurality of first control signals to the plurality of second control circuits; wherein one of the second control circuits correspondingly receives one of the first control signals;
each of the second control circuits is configured to generate a second control signal from the received first control signal and provide the second control signal to the third control circuit;
the third control circuit is configured to generate a bias voltage signal corresponding to each of the second control signals one to one from each of the received second control signals and supply the bias voltage signal to the ultrasonic probe.
2. The ultrasonic transmission control circuit of claim 1, wherein the second control circuit comprises a digital-to-analog converter and an adjustable high voltage module; wherein:
the digital-to-analog converter is configured to generate an intermediate control signal according to a first control signal provided by the first control circuit and provide the intermediate control signal to the adjustable high voltage module;
the adjustable high voltage module is configured to generate the second control signal from the intermediate control signal and provide the second control signal to the third control circuit.
3. The ultrasonic transmission control circuit according to claim 2, wherein the second control circuit further comprises a channel selection module; the ultrasonic probe comprises a plurality of array elements, and one array element group comprises at least two array elements;
the channel selection module is configured to provide the bias voltage generated by the third control circuit to different array elements in a plurality of drive phases.
4. The ultrasonic wave transmission control circuit according to claim 1, wherein the ultrasonic wave transmission control circuit further comprises a pulse circuit;
the first control circuit is further configured to generate a pulse control signal and provide the pulse control signal to the pulse circuit;
the pulse circuit is configured to generate a drive pulse signal in accordance with a pulse control signal supplied from the first control circuit and supply the drive pulse signal to the ultrasonic probe.
5. The ultrasound transmission control circuit according to any one of claims 1 to 4, further comprising a first power supply module for generating a voltage for supplying power to the first control circuit, the second control circuit, and the third control circuit according to a supply voltage.
6. An ultrasound imaging system, comprising: an ultrasonic probe, and an ultrasonic emission control circuit according to any one of claims 1 to 5.
7. The ultrasound imaging system of claim 6, further comprising: a power supply module; the power supply module is used for receiving the voltage of the power supply end and generating power supply voltage according to the voltage of the power supply end.
8. The ultrasound imaging system of claim 7, wherein the supply voltage comprises a first sub-supply voltage and a plurality of second sub-supply voltages, the power module specifically comprising:
a first voltage conversion module configured to receive a voltage of a power source terminal and generate an intermediate voltage according to the voltage of the power source terminal;
a first power supply module configured to receive the intermediate voltage and generate the first sub-supply voltage from the intermediate voltage;
a second power module configured to receive the intermediate voltage and generate the plurality of second sub-supply voltages from the intermediate voltage.
9. The ultrasonic imaging system of any one of claims 6-8, further comprising: an ultrasonic receiving circuit; the ultrasonic wave receiving circuit is configured to receive an ultrasonic wave reflected by an object.
10. An ultrasound imaging system according to any of claims 6-8, wherein the ultrasound probe is a capacitive micromachined ultrasound transducer.
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| CN113872626A (en) * | 2021-09-29 | 2021-12-31 | 京东方科技集团股份有限公司 | Ultrasonic wave receiving structure and method, ultrasonic probe and ultrasonic equipment |
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