CN111435154A - Electric leakage detection circuit, electric leakage detection device and electric leakage detection method for flash memory - Google Patents
Electric leakage detection circuit, electric leakage detection device and electric leakage detection method for flash memory Download PDFInfo
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Abstract
The invention discloses a leakage detection circuit, a leakage detection device of a flash memory and a leakage detection method, wherein the leakage detection circuit comprises: the circuit comprises a first current mirror unit, a second current mirror unit, a reference current generating unit, a third current mirror unit and a comparing unit; the input end of the first current mirror unit is used as the input end of the leakage detection circuit, and the output end of the first current mirror unit is electrically connected with the input end of the second current mirror unit; the output end of the second current mirror unit is electrically connected with the input end of the third current mirror unit; the input end of the reference current generating unit is electrically connected with the first power supply, and the output end of the reference current generating unit is electrically connected with the input end of the third current mirror unit; the output end of the third current mirror unit is electrically connected with the first input end of the comparison unit; and the second input end of the comparison unit is used for inputting a reference signal, and the output end of the comparison unit is used as the output end of the electric leakage detection circuit. The leakage detection of the circuit to be detected is conveniently and efficiently realized.
Description
Technical Field
The present invention relates to leakage detection technologies, and in particular, to a leakage detection circuit, a leakage detection device for a flash memory, and a leakage detection method.
Background
With the rapid development of technologies such as semiconductors and the like, the method has a very important role in detecting leakage current in some precision equipment such as a flash memory, and bad blocks in the flash memory can be timely marked through leakage detection so as to prevent data from being written into the bad blocks.
As the size of the flash memory chip is smaller and smaller, and the intervals between the corresponding word lines and the word lines and between the word lines and the substrate are smaller, the prior art cannot accurately detect the leakage between the word lines and the sub-lines and between the word lines and the substrate.
Disclosure of Invention
The invention provides a leakage detection circuit, a leakage detection device of a flash memory and a leakage detection method, which are used for realizing accurate detection of leakage current of precision equipment.
In a first aspect, an embodiment of the present invention provides an electrical leakage detection circuit, where the electrical leakage detection circuit includes: the circuit comprises a first current mirror unit, a second current mirror unit, a reference current generating unit, a third current mirror unit and a comparing unit;
the input end of the first current mirror unit is used as the input end of the leakage detection circuit, the output end of the first current mirror unit is electrically connected with the input end of the second current mirror unit, and the voltage end of the first current mirror unit is used for inputting bias voltage;
the output end of the second current mirror unit is electrically connected with the input end of the third current mirror unit, and the voltage end of the second current mirror unit is used for inputting bias voltage;
the input end of the reference current generating unit is electrically connected with a first power supply, and the output end of the reference current generating unit is electrically connected with the input end of the third current mirror unit;
the output end of the third current mirror unit is electrically connected with the first input end of the comparison unit, and the voltage end of the third current mirror unit is used for inputting bias voltage;
and the second input end of the comparison unit is used for inputting a reference signal, and the output end of the comparison unit is used as the output end of the electric leakage detection circuit.
Optionally, the method further includes: and the input end of the public current generating unit is electrically connected with a second power supply, and the output end of the public current generating unit is electrically connected with the input end of the first current mirror unit.
Optionally, the first current mirror unit adopts a PMOS cascode current mirror, the second current mirror unit adopts an NMOS basic current mirror, and the third current mirror adopts a PMOS basic current mirror.
Optionally, the reference current generating unit includes a first transistor, a control electrode of the first transistor is used as an input end of the reference current generating unit, a first electrode of the first transistor is used as an output end of the reference current generating unit, and a second electrode of the first transistor is grounded.
Optionally, the common current generating unit includes a second transistor, a control electrode of the second transistor is used as an input end of the common current generating unit, a first electrode of the second transistor is used as an output end of the common current generating unit, and a second electrode of the second transistor is grounded.
Optionally, the comparing unit includes a resistor, an integrating capacitor, and a comparator, a first end of the resistor is used as a first input end of the comparing unit, and a second end of the resistor is grounded;
a first input end of the comparator is electrically connected with a first end of the resistor, a second input end of the comparator is used as a second input end of the comparison unit, and an output end of the comparator is used as an output end of the comparison unit;
the reference signal is a reference voltage;
the first end of the integrating capacitor is electrically connected with the first end of the resistor, and the second end of the integrating capacitor is grounded.
In a second aspect, an embodiment of the present invention further provides a leakage detection device for a flash memory, including any one of the leakage detection circuit and the flash memory;
the voltage end of the first current mirror is electrically connected with the pump voltage output end of the flash memory, and the input end of the electric leakage detection circuit is electrically connected with the decoding circuit of the flash memory.
In a third aspect, an embodiment of the present invention further provides a leakage detection method based on the above leakage detection device for a flash memory, where the leakage detection method includes:
disconnecting a word line selection switch in the flash memory, setting a voltage value of a first power supply and a parameter value of a reference signal, and recording the time required by the output end of the comparison unit to turn over as first time;
and selecting one word line of the flash memory, applying a first level to the selected word line, applying a second level to a word line adjacent to the selected word line in the flash memory, and recording the time required by the output signal of the output end of the comparison unit to turn over as second time.
Optionally, recording that the time required for the output signal of the output end of the comparison unit to flip is the second time, further includes:
if the first time is longer than the second time, marking the word line as a normal word line;
and if the first time is not more than the second time, marking the word line as an abnormal word line.
Optionally, if a block of the flash memory includes an abnormal word line, the block is marked as a bad block.
According to the leakage detection circuit, the leakage detection circuit comprising the first current mirror unit, the second current mirror unit, the reference current generation unit, the third current mirror unit and the comparison unit is adopted, the output signal turning time of the comparison unit is used as a detection standard, and the leakage detection of the circuit to be detected is simply and efficiently realized.
Drawings
Fig. 1 is a schematic structural diagram of a leakage detection circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another leakage detection circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit structure diagram of a leakage detection circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of another leakage detection circuit according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of another leakage detection circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit structure diagram of a leakage detection device of a flash memory according to an embodiment of the present invention;
fig. 7 is a flowchart of a leakage detection method according to an embodiment of the present invention;
fig. 8 is a flowchart of another leakage detection method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Examples
Fig. 1 is a schematic structural diagram of a leakage detection circuit according to an embodiment of the present invention, and referring to fig. 1, the leakage detection circuit includes: a first current mirror unit 101, a second current mirror unit 102, a reference current generating unit 103, a third current mirror unit 104, and a comparing unit 105;
the input end of the first current mirror unit 101 serves as the input end IN of the leakage detection circuit, the output end of the first current mirror unit 101 is electrically connected with the input end of the second current mirror unit 102, and the voltage end VPEO of the first current mirror unit 101 is used for inputting a bias voltage;
the output end of the second current mirror unit 102 is electrically connected to the input end of the third current mirror unit 104, and the voltage end VCC1 of the second current mirror unit 102 is used for inputting a bias voltage;
the input end of the reference current generating unit 103 is electrically connected with the first power supply VR, and the output end of the reference current generating unit 103 is electrically connected with the input end of the third current mirror unit 104;
the output end of the third current mirror unit 104 is electrically connected to the first input end of the comparison unit 105, and the voltage end VCC2 of the third current mirror unit 103 is used for inputting a bias voltage;
the second input terminal of the comparing unit 105 is used for inputting the reference signal VREF L K, and the output terminal of the comparing unit 105 is used as the output terminal OUT of the leakage detecting circuit.
Specifically, the voltage terminal VPEO of the first current mirror unit 101, the voltage terminal VCC1 of the second current mirror unit 102 and the voltage terminal VCC2 of the third current mirror unit 104 may be connected to a positive voltage or ground according to the type of the current mirror, for example, the voltage terminal VPEO of the first current mirror unit 101 may be connected to a positive voltage, the voltage terminal VCC1 of the second current mirror unit 102 may be connected to a ground, and the voltage terminal VCC2 of the third current mirror unit 103 may be connected to a positive voltage.
After the first time is determined, the first power supply VR is turned off, that is, there is no output current at the output terminal of the reference current generating unit 103 at this time, the input terminal IN of the leakage detecting circuit is connected to the circuit to be detected, if the circuit to be detected has a leakage current, the leakage current is input to the first input terminal of the comparing unit 105 after being sequentially mirrored or gained by the first current mirror unit 101, the second current mirror unit 102 and the third current mirror unit 104, at this time, the comparing unit 105 integrates the input current at the first input terminal and compares the integrated input current with the reference signal, and when the integrated input current at the first input terminal of the comparing unit 105 is greater than the parameter value of the reference signal at the second input terminal of the comparing unit 105, the output signal at the output terminal of the comparing unit 105 is inverted, for example, from a low level to a high. Recording the time required for the output signal from the input end IN of the leakage detection circuit to the circuit to be detected to the output end of the comparison unit 105 to turn over as second time; and comparing the second time with the first time, and if the second time is not more than the first time, indicating that the leakage current of the circuit to be detected is greater than a standard value, and reminding a user that the circuit to be detected has a leakage fault. If the second time is longer than the first time, the leakage current of the circuit to be detected belongs to a normal range. It can be understood that, if there is no leakage current IN the circuit to be detected, the second time may be infinite, and to avoid the cost increase due to the excessively long detection time, the input terminal IN of the leakage detection circuit may be connected to the circuit to be detected, and if the output signal of the output terminal of the comparison unit 105 is still not inverted after the first time, it may be determined that the leakage current of the circuit to be detected belongs to the normal range.
According to the technical scheme of the embodiment, the leakage detection circuit comprising the first current mirror unit, the second current mirror unit, the reference current generation unit, the third current mirror unit and the comparison unit is adopted, the output signal turning time of the comparison unit is used as a detection standard, and the leakage detection of the circuit to be detected is simply and efficiently realized.
Optionally, referring to fig. 2, fig. 2 is a schematic structural diagram of another leakage detection circuit according to an embodiment of the present invention, where the leakage detection circuit further includes a common current generation unit 201, an input end of the common current generation unit 201 is electrically connected to a second power VCC3, and an output end of the common current generation unit 201 is electrically connected to an input end of the first current mirror unit 101.
Specifically, for some circuits with strict requirements on leakage current, for example, in a flash memory, the extremely small leakage current may have a serious influence on the flash memory, and in order to improve the detection sensitivity of the leakage detection circuit, the common current generation unit 201 may be arranged to superimpose the leakage current of the circuit to be detected on the output current of the common current generation unit 201, so that the leakage current with a relatively small current value may still be detected by the leakage detection circuit. The second power VCC3 may be identical to the first power VR, that is, may be connected to the input terminals of the reference current generating unit 103 and the common current generating unit 201 through the same power supply, respectively, so as to save space of the leakage detecting circuit. Before the input terminal IN of the leakage detection circuit is connected to the circuit to be detected, the input terminal of the first current mirror unit 101 only has the output current of the common current generating unit 201, the output current of the common current generating unit 201 is sequentially input to the third current mirror unit 104 after passing through the mirror images or gains of the first current mirror unit 101 and the second current mirror unit 102, and the output current of the reference current generating unit 103 is also input to the input terminal of the third current mirror unit 104, that is, the current input to the input terminal of the third current mirror unit 104 is the superposition of the two, and is input to the first input terminal of the comparing unit 105 after passing through the mirror images or gains of the third current mirror unit 104. After the input terminal IN of the leakage detection circuit is connected to the circuit to be detected, if there is leakage current IN the circuit to be detected, the leakage current is superimposed on the output current of the common current generation unit 201 and then input to the input terminal of the first current mirror unit 101, and then input to the first input terminal of the comparison unit 105 after being sequentially mirrored or gained by the first current mirror unit 101, the second current mirror unit 102, and the third current mirror unit 104. It is understood that the first time and the second time are obtained in the same manner as described above, and are not described herein again. And comparing the second time with the first time to determine the tiny leakage current of the circuit to be detected.
According to the technical scheme, the leakage detection circuit comprising the common current generation unit is adopted, when the leakage current of the circuit to be detected is small, the leakage detection circuit can still detect the leakage current, and the application range of the leakage detection circuit is widened.
Optionally, referring to fig. 3, fig. 3 is a schematic circuit structure diagram of a leakage detection circuit according to an embodiment of the present invention, where the first current mirror unit 101 adopts a PMOS cascode current mirror, the second current mirror unit 102 adopts an NMOS basic current mirror, and the third current mirror adopts a PMOS basic current mirror.
Specifically, the circuit structure of the PMOS cascode current mirror, the NMOS basic current mirror and the PMOS basic current mirror is well known to those skilled in the art, wherein the first current mirror unit includes four PMOS transistors P1, P2, P3 and P4, the second current mirror unit includes two NMOS transistors P5 and P6, the third current mirror unit includes two PMOS transistors P8 and P9, the voltage end VPEO of the first current mirror unit 101 inputs a positive voltage, the voltage end of the second current mirror unit 102 is grounded, and the voltage end VCC2 of the third current mirror unit 104 is connected to the positive voltage. The current mirror has the functions of image or gain and isolation, and avoids the influence on the detection result caused by the interference of a circuit to be detected. And the current mirror formed by the MOS tube is easier to integrate with the existing semiconductor equipment in a chip and is easy to manufacture.
Alternatively, with continued reference to fig. 3, the reference current generating unit 103 includes a first transistor P7, a control electrode of the first transistor P7 is used as an input terminal of the reference current generating unit 103, a first electrode of the first transistor P7 is used as an output terminal of the reference current generating unit 103, and a second electrode of the first transistor P7 is grounded.
Specifically, the control electrode of the first transistor P7 is electrically connected to the first power supply VR, and the voltage value of the first power supply VR is set, so that different currents, i.e. different detection criteria, are generated between the first electrode and the second electrode of the first transistor P7, and the first transistor P7 is suitable for different detection environments. And the first transistor P7 can adopt NMOS transistor, which is easy to manufacture and integrate.
Alternatively, referring to fig. 4, fig. 4 is a schematic circuit structure diagram of another leakage detection circuit according to an embodiment of the present invention, wherein the common current generating unit 201 includes a second transistor P10, a control electrode of the second transistor P10 is used as an input terminal of the common current generating unit 201, a first electrode of the second transistor P10 is used as an output terminal of the common current generating unit 201, and a second electrode of the second transistor P10 is grounded.
Specifically, a control electrode of the second transistor P10 is electrically connected to a second power source VCC3, wherein the second power source may be the same as the first power source, and the second transistor P10 may have a different model from the first transistor to generate different output currents under the same input voltage. And the second transistor P10 can adopt an NMOS transistor, which is easy to manufacture and integrate.
Optionally, referring to fig. 5, fig. 5 is a schematic circuit structure diagram of another leakage detection circuit according to an embodiment of the present invention, where the comparing unit 105 includes a resistor R, a comparator 1052 and an integrating capacitor C, a first end of the resistor R is used as a first input end of the comparing unit 105, and a second end of the resistor R is grounded;
a first input terminal of the comparator 1052 is electrically connected to the first terminal of the resistor 1051, a second input terminal of the comparator 1052 serves as a second input terminal of the comparing unit 105, and an output terminal of the comparator 1052 serves as an output terminal of the comparing unit 105;
the reference signal is a reference voltage;
the first end of the integrating capacitor C is electrically connected with the first end of the resistor R, and the second end of the integrating capacitor C is grounded.
Specifically, the resistor R is configured to convert an output current at the output end of the third current mirror unit 104 into a voltage, and the integrating capacitor C is configured to integrate the voltage across the resistor R, that is, to accumulate the output current at the output end of the third current mirror unit 104, when a leakage current of a circuit to be detected is large, the output current at the output end of the corresponding third current mirror unit 104 is also large, at this time, the charge accumulation of the integrating capacitor C is fast, the voltage change at the first input end of the corresponding comparator 1052 is fast, and the reference signal is a reference voltage. Therefore, whether the leakage current of the circuit to be detected exceeds the standard can be judged.
According to the technical scheme of the embodiment, the leakage detection circuit comprising the resistor, the integrating capacitor and the comparator is adopted, so that the leakage current is converted into the voltage, is integrated and then is compared with the reference voltage, the time required by the signal turnover at the output end of the comparator is determined, and the leakage detection circuit is easier to realize.
Optionally, referring to fig. 6, fig. 6 is a schematic circuit structure diagram of a leakage detection device of a flash memory according to an embodiment of the present invention, where the leakage detection device of the flash memory includes any one of the leakage detection circuits and the flash memory;
the voltage end VPEO of the first current mirror unit 101 is electrically connected to the pump voltage output end of the flash memory, and the input end IN of the leakage detection circuit is electrically connected to the decoding circuit 302 of the flash memory.
It is understood that the flash memory includes a pump voltage generating device 301 and a corresponding peripheral circuit 303, the pump voltage generating device 301 may include a charge pump 3011, the peripheral circuit 302 may include a peripheral comparator 3031, the decoding circuit 302 may be understood as a row decoding circuit of the flash memory, and its specific circuit structure is known to those skilled in the art, the voltage terminal of the first current mirror unit 101 is electrically connected to the pump voltage output terminal of the flash memory, so as to improve the utilization rate of the flash memory components and reduce the cost, the leakage current of the circuit to be detected may be the leakage current between the word line and the word line or between the word line and the substrate, before the detection, the word line selecting switches in the row decoding circuit are all turned off, i.e., B L Kn, B L Kn-1, B L Kn-2 and B L Kn-3 are all turned off, i.e., the voltage value of the first power supply VR, the voltage value of the second power supply VCC3 and the reference signal L K are set to determine that the first time, the first leakage current level of the first word line is equal to the first word line and the second leakage current level is equal to the second word line gm, and if the second leakage current gm is equal to the first leakage current gm, the first leakage voltage gm, the first leakage current is equal to the second leakage level.
According to the technical scheme, the leakage detection device comprising the leakage detection circuit and the flash memory can be used for timely detecting the bad block in the flash memory, so that a user can avoid writing data into the bad block or timely transmitting the data in the bad block to other normal blocks, and data loss is avoided.
Alternatively, referring to fig. 7, fig. 7 is a flowchart of a leakage detection method according to an embodiment of the present invention, including,
Specifically, turning off the word line selection switches in the flash memory includes turning off all the word line selection switches in the flash memory, and the first time is the time required from the time when the first power supply is applied to the reference current generation unit to the time when the output signal of the output end of the comparison unit is inverted.
Specifically, the second time is a time required from the time when the first level is applied to the selected word line and the second level is applied to the word line adjacent to the selected word line in the flash memory to the time when the output signal of the output terminal of the comparison unit is inverted.
Alternatively, referring to fig. 8, fig. 8 is a flowchart of another leakage detection method according to an embodiment of the present invention, including,
Specifically, after the selected word line is marked as a normal word line, other word lines in the same block are detected, and when the marked word line is an abnormal word line, other word lines in the same block may not be detected.
Optionally, if a block of the flash memory includes an abnormal word line, the block is marked as a bad block.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An electrical leakage detection circuit, comprising: the circuit comprises a first current mirror unit, a second current mirror unit, a reference current generating unit, a third current mirror unit and a comparing unit;
the input end of the first current mirror unit is used as the input end of the leakage detection circuit, the output end of the first current mirror unit is electrically connected with the input end of the second current mirror unit, and the voltage end of the first current mirror unit is used for inputting bias voltage;
the output end of the second current mirror unit is electrically connected with the input end of the third current mirror unit, and the voltage end of the second current mirror unit is used for inputting bias voltage;
the input end of the reference current generating unit is electrically connected with a first power supply, and the output end of the reference current generating unit is electrically connected with the input end of the third current mirror unit;
the output end of the third current mirror unit is electrically connected with the first input end of the comparison unit, and the voltage end of the third current mirror unit is used for inputting bias voltage;
and the second input end of the comparison unit is used for inputting a reference signal, and the output end of the comparison unit is used as the output end of the electric leakage detection circuit.
2. The electrical leakage detection circuit according to claim 1, further comprising: and the input end of the public current generating unit is electrically connected with a second power supply, and the output end of the public current generating unit is electrically connected with the input end of the first current mirror unit.
3. The leakage detection circuit of claim 1, wherein the first current mirror unit is a PMOS cascode current mirror, the second current mirror unit is an NMOS basic current mirror, and the third current mirror is a PMOS basic current mirror.
4. The leakage detection circuit of claim 2, wherein the reference current generation unit comprises a first transistor, a control electrode of the first transistor is used as an input terminal of the reference current generation unit, a first electrode of the first transistor is used as an output terminal of the reference current generation unit, and a second electrode of the first transistor is grounded.
5. The leakage detection circuit according to claim 2, wherein the common current generation unit includes a second transistor, a control electrode of the second transistor serves as an input terminal of the common current generation unit, a first electrode of the second transistor serves as an output terminal of the common current generation unit, and a second electrode of the second transistor is grounded.
6. The leakage detection circuit according to claim 1, wherein the comparison unit comprises a resistor, an integrating capacitor and a comparator, a first end of the resistor is used as a first input end of the comparison unit, and a second end of the resistor is grounded;
a first input end of the comparator is electrically connected with a first end of the resistor, a second input end of the comparator is used as a second input end of the comparison unit, and an output end of the comparator is used as an output end of the comparison unit;
the reference signal is a reference voltage;
the first end of the integrating capacitor is electrically connected with the first end of the resistor, and the second end of the integrating capacitor is grounded.
7. A flash memory leakage detection device comprising the leakage detection circuit of any one of claims 1 to 6 and a flash memory;
the voltage end of the first current mirror is electrically connected with the pump voltage output end of the flash memory, and the input end of the electric leakage detection circuit is electrically connected with the decoding circuit of the flash memory.
8. A leakage detection method based on the leakage detection device of the flash memory of claim 7, wherein the leakage detection method comprises:
disconnecting a word line selection switch in the flash memory, setting a voltage value of a first power supply and a parameter value of a reference signal, and recording the time required by the output end of the comparison unit to turn over as first time;
and selecting one word line of the flash memory, applying a first level to the selected word line, applying a second level to a word line adjacent to the selected word line in the flash memory, and recording the time required by the output signal of the output end of the comparison unit to turn over as second time.
9. The electrical leakage detection method of claim 8, wherein recording the time required for the output signal at the output of the comparison unit to flip after the second time further comprises:
if the first time is longer than the second time, marking the word line as a normal word line;
and if the first time is not more than the second time, marking the word line as an abnormal word line.
10. The leakage detection method according to claim 9, wherein if the block of the flash memory contains an abnormal word line, the block is marked as a bad block.
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| US5889702A (en) * | 1997-03-11 | 1999-03-30 | Sgs-Thomson Microelectronics, S.A. | Read circuit for memory adapted to the measurement of leakage currents |
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