CN111432296B

CN111432296B - Dual-mode network communication device of shared memory

Info

Publication number: CN111432296B
Application number: CN201910020549.XA
Authority: CN
Inventors: 蔡明宗; 蔡秋云; 彭建濂; 徐辅擎
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-01-09
Filing date: 2019-01-09
Publication date: 2022-04-19
Anticipated expiration: 2039-01-09
Also published as: CN111432296A

Abstract

The invention discloses a dual-mode network communication device sharing a memory, which comprises a first memory, an OTT module and a PON module. The first memory is divided into an OTT area and a PON area, the OTT module is used for obtaining OTT service and comprises an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit and a memory slave controller. The PON module comprises a PON processor and a second memory main controller. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request from the PON processor, to access the OTT area or the PON area of the first memory through the first memory host controller, and to determine a priority order of the first access request and the second access request according to operation states of the OTT module and the PON module.

Description

Dual-mode network communication device of shared memory

Technical Field

The present invention relates to a network communication device, and more particularly, to a dual-mode network communication device with a shared memory.

Background

The existing Over The Top (OTT) audio/video equipment needs to be combined with a router, a switch or a Passive Optical Network (PON), so that The multifunctional set-Top box is achieved, and The equipment can also be used as home audio/video communication integration equipment. In other words, if the user's home provides PON, the OTT device and the PON device are integrated, so that the network and the OTT service can be accessed simultaneously.

The conventional OTT and PON integration apparatuses each employ two separate sets of System On Chips (SOC), each operating a corresponding operating System, and each independently using a flash storage device. In other industries, a proprietary interface other than the flash booting interface (NFBI) is used to borrow the built-in flash memory of the processor, however, both are required to support the operation of the proprietary interface.

The prior OTT device and PON device mostly adopt Embedded multimedia memory Card (eMMC) or NAND flash memory, and therefore, two flash memory control chips are required. If the OTT device and the PON device use chips manufactured by the same company and develop proprietary interfaces, they are incompatible with the flash memory control chips on the market and cannot achieve the same speed. Furthermore, once the OTT device is powered off, it may cause the PON device to be unusable, and runs counter to the feature that the PON device is generally used to be always on for continuous networking.

Therefore, how to complete the integration of PON and OTT in a simple manner by improving the circuit design to overcome the above-mentioned drawbacks has become one of the important issues to be solved by the industry.

Disclosure of Invention

The present invention provides a dual-mode network communication device sharing a memory, which can interface with an OTT module by extending the original memory interface of a PON module, and can achieve a mechanism of sharing a flash memory without supporting a special memory interface by both the OTT module and the IC of the PON module.

In order to solve the above technical problem, one technical solution of the present invention is to provide a dual-mode network communication device with a shared memory, which includes a first memory, an OTT module, and a PON module. The first memory is divided into an on-cloud (OTT) area and a Passive Optical Network (PON) area, and the on-cloud (OTT) module is used for obtaining an OTT service and comprises an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit and a memory slave controller. The memory arbitration circuit is coupled to the OTT processor, and the first memory host controller is coupled to the memory arbitration circuit and coupled to the first memory through a first memory interface. The bridge circuit is coupled to the memory arbitration circuit, and the memory slave controller is coupled to the bridge circuit. The Passive Optical Network (PON) module is connected to a fiber network and comprises a PON processor and a second memory main controller. The second memory master controller is coupled to the PON processor and coupled to the memory slave controller through a second memory interface. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request from the PON processor, access the OTT area or the PON area of the memory through the first memory host controller, and determine a priority order of the first access request and the second access request according to operation states of the OTT module and the PON module.

One of the benefits of the present invention is that the dual-mode network communication device sharing a memory provided by the present invention can be interfaced with the OTT module by extending the original memory interface of the PON module, and does not require the ICs of the OTT module and the PON module to support a special memory interface, thereby achieving a mechanism of sharing a flash memory.

One of the benefits of the present invention is that, in the dual-mode network communication device sharing a memory provided by the present invention, by setting the memory controller, the memory arbitration circuit, the bridge circuit, and the memory slave controller in the OTT module in the uninterruptible power region, when the OTT processor enters the power saving mode, such as the sleep mode or the low power mode, the PON module can still access the flash memory normally.

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.

Drawings

FIG. 1 is a block diagram of a dual-mode network communication device sharing a memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a dual-mode network communication device sharing a memory according to a second embodiment of the present invention.

FIG. 3 is another block diagram of a dual-mode network communication device sharing a memory according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a dual-mode network communication device sharing a memory according to a third embodiment of the present invention.

Detailed Description

The following description is provided for the implementation of the "shared memory dual mode network communication device" in the present disclosure by specific embodiments, and those skilled in the art can understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The drawings of the present invention are for illustrative purposes only and are not intended to be drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or from one signal to another signal. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.

[ first embodiment ]

Fig. 1 is a block diagram of a dual-mode network communication device sharing a memory according to a first embodiment of the present invention. A first embodiment of the present invention provides a dual-mode network communication device 1 with shared memory, which includes a first memory 10, an OTT module 12, a PON module 14, and a power management module 16. The first memory 10 is divided into an on-the-cloud (OTT) area 100 and a Passive Optical Network (PON) area 102 for use by the OTT module 12 and the PON module 14, respectively. The OTT module 12 may be used in a television set-top box or an OTT television box, and is connected to the cloud server to obtain OTT services, so that a user can watch digital television programs. On the other hand, a Passive Optical Network (PON) module can be used to provide a fiber-to-the-home technology to users, which is currently most noticed by the telecommunication companies, and has the advantages of construction flexibility and construction cost. A typical PON system uses a wavelength division multiplexing technique to transmit uplink and downlink traffic. The downlink traffic is transmitted to each ONU in a broadcast manner, and in the uplink direction, TDMA (Time-Division Multiple-Access) or WDMA (Wave-Division Multiple-Access) is used as a Multiple Access mechanism for the ONU at the user end.

In detail, the main purpose of the present invention is to save the material cost required by the hardware of the electronic product, and in the existing industry, the PON and OTT both use their respective flash memories, the PON uses NAND flash memories with small serial/parallel transmission specifications, and the PON currently has a capacity of about 128MB or 256MB SLC NAND flash memories and a price of $1.x $ 2.x $. On the other hand, the conventional OTT module mostly uses large-capacity eMMC or MLC NAND flash memory, and currently, the capacity is mainly 8 GB. However, the requirement of the OTT on the operating system, such as the Android system, is much smaller than the adopted capacity, and there is a considerable amount of flash memory space available. Therefore, the flash memory is divided into the OTT area 100 and the PON area 102, so that a part of the operation space required by the OTT end is reserved for the PON end, thereby saving the memory setup cost of the PON end.

To further explain, in the embodiment, the OTT module 12 includes an OTT processor 120, a memory arbitration circuit 122, a first memory master controller 124, a bridge circuit 126, and a memory slave controller 128. The memory arbitration circuit 122 is coupled to the OTT processor 120, and the first memory host controller 124 is coupled to the memory arbitration circuit 122 and coupled to the first memory 10 through the first memory interface 13. The bridge circuit 126 is coupled to the memory arbitration circuit 122, and the memory slave controller 128 is coupled to the bridge circuit 128.

A Passive Optical Network (PON) module 14, operable to connect to a fiber optic network, includes a PON processor 142 and a second memory master controller 144. The second memory master controller 144 is coupled to the PON processor 142 and is coupled to the memory slave controller 128 through the second memory interface 15.

For example, the first memory master controller 124, the memory slave controller 128 and the second memory master controller 144 may be used as a bus circuit controller for managing and planning the transmission speed from the first memory 10 to the OTT processor 120 and the PON processor 142, which may be a single chip or integrated into a large chip related thereto, such as a microprocessor and a memory controller built in a north bridge.

The configuration of the memory arbitration circuit 122, the bridge circuit 126 and the memory slave controller 128 is mainly used to simulate a flash memory suitable for the interface according to the second memory interface 15, so that the original memory interface of the PON module 14 can be used to interface with the OTT module 12, and it is not necessary that the ICs of the OTT module 12 and the PON module 14 support a special memory interface.

The memory arbitration circuit 122 may be configured to respond to a first access request from the OTT processor 120 or a second access request from the PON processor 14 to access the OTT area 100 or the PON area 102 of the first memory 10 through the first memory host controller 124. In addition, if the first access request of the OTT processor 120 or the second access request of the PON processor 14 are generated simultaneously, the memory arbitration circuit 122 may further determine the priority of the first access request and the second access request according to the operation states of the OTT module 12 and the PON module 14. The OTT module can be connected with the PON module by prolonging the original memory interface of the PON module, and a mechanism of sharing a flash memory can be achieved without supporting a special memory interface by ICs of the OTT module and the PON module.

Furthermore, in order to meet the feature that the PON module needs to be kept normally open for continuous networking, the memory-sharing dual-mode network communication device 1 further includes a power management module 16, which is connected to the OTT module 12 and the PON module 14, respectively, in addition to providing power for both operations, the power management module 16 further provides an uninterruptible power region ON and a power saving region PSV in the OTT module 12, wherein the OTT processor 120 is disposed in the power saving region PSV, and the first memory main controller 124, the memory arbitration circuit 122, the bridge circuit 126 and the memory slave controller 128 are in the uninterruptible power region ON, so that when the OTT processor 120 enters the power saving mode, the first memory main controller 124, the memory arbitration circuit 122, the bridge circuit 126 and the memory slave controller 128 still maintain normal operations, and the PON module 14 can access the PON region 102 in the first memory 10.

Therefore, by arranging the memory controller, the memory arbitration circuit, the bridge circuit and the memory slave controller in the OTT module in the uninterruptible power region, the PON module can still normally access the flash memory when the OTT processor enters a power saving mode, such as a sleep mode or a low power mode.

However, since the first memory interface 13 and the second memory interface 15 may be the same or different, different bridge circuits 126 are required for both cases, as will be described in detail below.

[ second embodiment ]

Fig. 2 is a block diagram of a dual-mode network communication device sharing a memory according to a second embodiment of the present invention. A second embodiment of the present invention provides a dual-mode network communication device 1a with a shared memory, which includes an eMMC memory 10a, an OTT module 12, and a PON module 14. In this embodiment, similar elements are denoted by similar reference numerals and are not described again. The OTT module 12 includes an OTT processor 120, a memory arbitration circuit 122, an eMMC master controller 124a, a NAND/eMMC bridge circuit 126a, and a NAND slave controller 128 a. The memory arbitration circuit 122 is coupled to the OTT processor 120, and the eMMC host controller 124a is coupled to the memory arbitration circuit 122 and coupled to the eMMC memory 10 through the eMMC interface 13. The NAND/eMMC bridge circuit 126a is coupled to the memory arbitration circuit 122, and the NAND slave controller 128a is coupled to the NAND/eMMC bridge circuit 126 a.

The PON module 14 includes a PON processor 142 and a first NAND host controller 144 a. The first NAND master controller 144a is coupled to the PON processor 142 and is coupled to the NAND slave controller 128a through the first SPI/parallel NAND interface 15 a.

In this embodiment, regarding the main architecture of the first embodiment, it is the case that the first memory interface is different from the second memory interface, and therefore, when the memory arbitration circuit 122 makes the PON module 14 accessible to the PON region in response to the second access request from the PON module 14, the bridge circuit is configured to convert the address and data signals accessing the first memory between the first signal specification applicable to the first memory interface and the second signal specification applicable to the second memory interface. In this embodiment, the NAND/eMMC bridge circuit 126a is required to convert NAND addresses and data from the PON module 12 into eMMC addresses and data, so that the eMMC host controller 124a can access the eMMC memory 10a through the eMMC interface 13a according to the eMMC addresses and data from the PON module 12.

Similarly, when the eMMC master controller 124a transmits eMMC addresses and data to the PON module 14 through the memory arbitration circuit 122, the NAND/eMMC bridge circuit 126a needs to convert the eMMC addresses and data into NAND addresses and data for the PON module 12, and the NAND slave controller 128a can transmit the NAND addresses and data to the PON module 12 through the first SPI/parallel NAND interface 15a to complete the access of the PON module 12 to the eMMC memory 10 a.

Reference is further made to fig. 3, which is another block diagram of the dual-mode network communication device sharing memory according to the second embodiment of the present invention, and is used to illustrate examples of the memory arbitration circuit 122a and the bridge circuit 126 a. As shown, the bridge circuit 126a includes a multiplexer 126a1, a second memory 126a2, a data bus 126a3 and an acknowledge signal line WL. The multiplexer 126a1 is coupled to the NAND slave controller 128a, the second memory 126a2 is coupled to the multiplexer 126a1, the data bus 126a3 is coupled to the multiplexer 126a1, the NAND slave controller 128a, and the eMMC master controller 124a, an acknowledge signal line WL is coupled to the memory arbitration circuit 122a, the eMMC master controller 124a, and the NAND slave controller 128 a. The second Memory 126a2 can be a Random Access Memory (ram), such as a Static Random-Access Memory (SRAM), a Dynamic Random-Access Memory (DRAM), etc. The second memory 126a2 is used for storing descriptors (descriptors) required by the PON module 14 when executing programs.

On the other hand, the memory arbitration circuit 122a of the present embodiment includes a signal (Semaphore) module 122a1, the signal module 122a1 may be a register storing a plurality of parameters for determining the priority of the first access request and the second access request according to the operation status of the OTT module 12 and the PON module, and the signal module 122a1 is configured to receive the acknowledge signal Valid from the NAND slave controller 128a when the PON processor 142 transmits the second access request, and determine whether to respond to the acknowledge signal Valid to allow the PON module 14 to access the PON region 102 according to the operation status of the OTT module 12 and the PON module 14.

For the PON module, the program flow includes an erasing phase, a program loading phase, a program executing phase and a state obtaining phase. During the erase phase, the PON module 14 issues an erase command, the NAND slave controller 128a notifies the same via the Valid signal, until the PON module 14 writes data into the second memory 126a2 via the multiplexer 126a1 via the NAND slave controller 128a during the program loading phase.

During the program execution phase, the NAND slave controller 128a writes the descriptor into the second memory 126a2, and when the NAND slave controller 128a receives the program execution command from the PON module 14, it sends a confirmation signal Valid to the eMMC master controller 124a and the signal module 122a1 of the memory arbitration circuit 122 a. The eMMC host controller 124a then determines whether the procedure can be performed via the flag module 122a 1. Specifically, the eMMC main controller 124a may determine whether the procedure can be executed according to the operation states of the OTT module 12 and the PON module 14, for example, when the system is just started up, the system determines that the network connection capability of the PON needs to be provided preferentially, the PON module 14 is activated preferentially, and issues a procedure execution command, so the eMMC main controller 124a determines to execute the initialization procedure of the PON module 14 first through the flag module 122a 1. The signal module 122a1 can be implemented by hardware, firmware or software, but is not limited thereto, and a plurality of parameters for determining the basis of the above determination can also be stored in the signal module 122a1 as a register.

After the eMMC host controller 124a determines that the process is executable via the flag module 122a1, the eMMC host controller 124a retrieves the descriptor from the second memory 126a2, e.g., via the memory/data bus interface sram if and the data signal dbus, to execute the process. The eMMC master controller 124a then writes the data from the second memory 126a2 to the eMMC memory 10a, and when the program execution is complete, the eMMC master controller 124a sends a complete signal done to the NAND slave controller 128 a. Here, if a program execution error occurs or an error occurs while data is being retrieved from the second memory 126a2, the eMMC master controller 124a sends an error signal err to the NAND slave controller 128a, for example, sending a high level pulse as the error signal err.

Further, in the status obtaining phase, the PON module 14 may confirm whether the program executing phase is completed, and therefore, the eMMC host controller 124a replies the current status to the PON module 14 with a data signal dbus until the PON module 14 confirms that the status is ready, and further transmits a new command.

In addition, the PON read flow from the PON module 14 to the eMMC memory 128 may include a page read phase, a status acquisition phase, and a cache read phase. Here, the page read phase is primarily used to let the PON module 14 inform the eMMC host controller 124a to transfer data from the eMMC memory 10a to the second memory 126a 2. Similarly to the program execution phase, the PON module 14 issues a page read command, and the NAND slave controller 128a writes the descriptor into the second memory 126a2 accordingly, and issues a confirmation signal Valid to the eMMC master controller 124a and the flag module 122a1 of the memory arbitration circuit 122 a. Then, the eMMC host controller 124a determines whether the reading operation can be performed through the flag module 122a1, and when the eMMC host controller 124a determines that the reading operation of the PON module 14 can be performed through the flag module 122a1, the eMMC host controller 124a obtains the descriptor from the second memory 126a2, for example, through the memory/data bus conversion interface sram if and the data signal dbus, so as to perform the reading operation. Next, the eMMC master controller 124a writes the data from the second memory 126a2 to the eMMC memory 10a and sends a done signal done to the NAND slave controller 128 a. Here, if a read error occurs, or an error occurs when the eMMC master controller 124a acquires data from the second memory 126a2, an error signal err is issued to the NAND slave controller 128 a.

Further, in the state obtaining phase, the eMMC host controller 124a replies the current state to the PON module 14 with a data signal dbus, and further transmits a new command until the PON module 14 confirms that the state is ready. The cache read phase is mainly used to allow the PON module 14 to notify the NAND slave controller 128a to transmit data to the PON module 14. When the PON module 14 issues a cache read command, the NAND slave controller 128a fetches data from the second memory 126a2 and transmits the fetched data to the PON module 14.

In addition, during the reset phase of the PON module 14, the PON module 14 may transmit a reset signal to the eMMC master controller 124a through the NAND slave controller 128a to perform a soft restart procedure.

As described above, the register 122a1 stores parameters for determining the priority of the first access request and the second access request according to the operation status of the OTT module 12 and the PON module, such as an addr _ offset parameter for determining the ratio of the PON area 102 and the OTT area 100, which defines a Block address offset (Block address offset for command queue mode) of the command queue mode, a count parameter for determining the size of a plurality of page addresses corresponding to the PON module, a pri parameter for determining the priority of the command queue mode, a len parameter for determining the transmission length, a 4-bit cache read command, and a 4-bit program execution command. The command queue is a queue for enabling command execution in priority order or delay order, and the 4-bit cache read command and the 4-bit program execution command are transmitted with 4 bits as data signal dbus between the eMMC master controller 124a and the NAND slave controller 128a, so that two more signals are required compared to 2 bits.

Thus, when the PON module 14 and the OTT module 12 are to be integrated, the OTT module having the eMMC interface can be interfaced by extending the original SPI/parallel NAND interface of the PON module 14, and a mechanism of sharing the flash memory is achieved without supporting a special memory interface by the ICs of the OTT module and the PON module.

[ third embodiment ]

Fig. 4 is a block diagram of a dual-mode network communication device sharing a memory according to a third embodiment of the present invention. The third embodiment of the present invention provides a dual-mode network communication device 1b with shared memory, which includes an MLC NAND memory 10b, an OTT module 12, and a PON module 14. In this embodiment, similar elements are denoted by similar reference numerals and are not described again. The OTT module 12 includes an OTT processor 120, a memory arbitration circuit 122, a second NAND master controller 124b, a bypass bridge circuit 126b, and a NAND slave controller 128 a. The memory arbitration circuit 122 is coupled to the OTT processor 120, and the second NAND host controller 124b is coupled to the memory arbitration circuit 122 and is coupled to the MLC NAND memory 10b through the second SPI/parallel NAND interface 13 b. The bypass bridge circuit 126b is coupled to the memory arbitration circuit 122, and the NAND slave controller 128a is coupled to the NAND/eMMC bridge circuit 126 a.

In this embodiment, regarding the main architecture of the first embodiment, it is the case that the first memory interface is the same as the second memory interface, therefore, when the memory arbitration circuit 122 makes the PON module 14 accessible to the PON region in response to the second access request from the PON module 14, the bridge circuit does not need to convert the address and data signals accessing the first memory between the first signal specification applicable to the first memory interface and the second signal specification applicable to the second memory interface, and thus can directly serve as the bypass bridge circuit 126b providing the transmission path. In the present embodiment, since the memory interfaces are the same, the second NAND host controller 124b can directly access the MLC NAND memory 10b via the second SPI/parallel NAND interface 13b according to the NAND addresses and data from the PON module 12.

Similarly, when the second NAND master controller 124b transmits NAND addresses and data to the PON module 14 through the memory arbitration circuit 122, the NAND addresses and data transmitted to the PON module 12 can be directly transmitted to the NAND slave controller 128a without conversion, and the NAND slave controller 128a can transmit the NAND addresses and data transmitted to the PON module 12 through the first SPI/parallel NAND interface 15a to complete the access of the PON module 12 to the eMMC memory 10 a.

Thus, when the PON module 14 and the OTT module 12 are to be integrated, the PON module 14 can be connected to the OTT module having the SPI/parallel NAND interface by extending the original SPI/parallel NAND interface of the PON module, and a mechanism of sharing the flash memory is achieved without supporting a special memory interface by the ICs of the OTT module and the PON module.

[ advantageous effects of the embodiments ]

The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, so that the invention is not limited by the disclosure of the specification and drawings.

[ notation ] to show

The dual-mode network communication device of the shared memory comprises: 1. 1a, 1b

A first memory: 10

An eMMC memory: 10a of

MLC NAND memory: 10b

On-cloud (OTT) zone: 100

Passive Optical Network (PON) area: 102

An OTT module: 12

An OTT processor: 120

A memory arbitration circuit: 122. 122a of the first and second substrates

A signal module: 122a1

The first memory host controller: 124

eMMC master controller: 124a of the first embodiment

A second NAND master controller: 124b

A bridge circuit: 126

NAND/eMMC bridge circuit: 126a

A multiplexer: 126a1

A second memory: 126a2

Data bus: 126a3

A bypass bridge circuit: 126b

A memory slave controller: 128

A NAND slave controller: 128a

A first memory interface: 13

An eMMC interface: 13a of

Second SPI/parallel NAND interface: 13b

A PON module: 14

A PON processor: 142

The second memory host controller: 144

The first NAND master controller: 144a of the first embodiment

A second memory interface: 15

First SPI/parallel NAND interface: 15a of

A power management module: 16

An acknowledgement signal line: WL

A completion signal: done

Error signal: err (r)

Acknowledgement signal: valid

Data signal: dbus

Memory/data bus conversion interface: sram if

A non-power-off region: ON

The electricity-saving area: PSV.

Claims

1. A dual-mode network communication device sharing a memory comprises:

a first memory divided into an on-the-cloud (OTT) region and a Passive Optical Network (PON) region;

an on-cloud module for obtaining an on-cloud service, the on-cloud module comprising:

a processor on the cloud;

a memory arbitration circuit coupled to the on-cloud processor;

a first memory master controller coupled to the memory arbitration circuit and coupled to the first memory through a first memory interface;

a bridge circuit coupled to the memory arbitration circuit; and

a memory slave controller coupled to the bridge circuit;

a Passive Optical Network (PON) module connected to a fiber optic network, the PON module comprising:

a passive optical network processor; and

a second memory master controller coupled to the passive optical network processor and coupled to the memory slave controller through a second memory interface,

the memory arbitration circuit is configured to respond to a first access request from the on-cloud processor or a second access request from the passive optical network processor, access the on-cloud area or the passive optical network area of the first memory through the first memory main controller, and determine a priority order of the first access request and the second access request according to operation states of the on-cloud module and the passive optical network module.

2. The dual-mode network communication device with shared memory as claimed in claim 1, wherein the first memory interface is different from the second memory interface.

3. The device of claim 2, wherein the memory arbitration circuit is configured to switch address and data signals for accessing the first memory between a first signal specification applicable to the first memory interface and a second signal specification applicable to the second memory interface in response to the second access request.

4. The dual-mode network communication device with shared memory of claim 3, wherein the second memory master controller is a first NAND master controller, the memory slave controller is a NAND slave controller, and the first memory master controller is an eMMC master controller.

5. The dual-mode network communication device of claim 4, wherein the first memory is an eMMC memory, the first memory interface is an eMMC interface, and the second memory interface is an SPI interface.

6. The dual-mode network communication device with shared memory as claimed in claim 5, wherein the bridge circuit comprises:

a multiplexer coupled to the NAND slave controller;

a second memory coupled to the multiplexer;

a data bus coupled to the multiplexer, the NAND slave controller, and the eMMC master controller;

an acknowledge signal line coupled to the memory arbitration circuit, the eMMC host controller, and the NAND slave controller.

7. The dual-mode network communication device of claim 6, wherein the memory arbitration circuit comprises a signal module, the signal module is configured to receive an acknowledgement signal from the NAND slave controller when the passive optical network processor transmits the second access request, and determine whether to allow the passive optical network module to access the passive optical network area in response to the acknowledgement signal according to the operation status of the on-cloud module and the passive optical network module.

8. The apparatus of claim 7, wherein the signaling module further comprises a register storing a plurality of parameters for determining the priority of the first access request and the second access request according to the operation status of the on-cloud module and the passive optical network module.

9. The dual-mode network communication device with shared memory as claimed in claim 5, wherein the memory arbitration circuit further comprises a register storing a plurality of parameters for dividing the first memory into the on-cloud area and the passive optical network area.

10. The dual-mode network communication device with shared memory as claimed in claim 1, wherein the first memory interface is the same as the second memory interface.