CN111431540B - Neural network model-based FPGA configuration file arithmetic compression and decompression method - Google Patents

Neural network model-based FPGA configuration file arithmetic compression and decompression method Download PDF

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CN111431540B
CN111431540B CN202010251333.7A CN202010251333A CN111431540B CN 111431540 B CN111431540 B CN 111431540B CN 202010251333 A CN202010251333 A CN 202010251333A CN 111431540 B CN111431540 B CN 111431540B
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CN111431540A (en
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伍卫国
康益菲
王今雨
冯雅琦
赵东方
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Xian Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06N3/02—Neural networks
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
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    • G06N3/045—Combinations of networks
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
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    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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Abstract

The invention discloses an arithmetic compression and decompression method for an FPGA (field programmable gate array) configuration file based on a neural network model, which is characterized in that a content sequence of the FPGA configuration file is defined, and conditional probability distribution of any symbol under the condition that the former k items of data are determined is taken as the probability of a corresponding symbol in the arithmetic coding process; estimating the probability of each symbol in the FPGA configuration file by adopting a neural network model; arithmetic coding is adopted, and the established neural network is used for carrying out arithmetic coding compression on each symbol probability of the predicted FPGA configuration file; and decompressing the FPGA configuration file. The invention uses the neural network model to carry out probability estimation of the configuration file sequence data, and uses the estimation result to compress and decompress the FPGA configuration file, thereby solving the problem of overlong time consumption in the FPGA configuration process.

Description

Neural network model-based FPGA configuration file arithmetic compression and decompression method
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to an FPGA configuration file arithmetic compression and decompression method based on a neural network model.
Background
Because of its high performance and flexibility, a Field Programmable Gate Array (FPGA) chip has gained more and more attention and acceptance in the Field of hardware acceleration of a neural network in recent years, and especially has wide application in the fields of automobile automatic driving, stock high-frequency trading, internet of things computing and the like which have high requirements for real-time performance.
Artificial intelligence and deep learning develop rapidly, in order to deal with increasingly complex neural network models, the integration level of an FPGA chip is continuously improved, the number of available resources on the chip is continuously increased, and the configuration file of the FPGA chip is enlarged while the performance of the chip is improved. At present, after local compiling is completed, a configuration file is transmitted to an FPGA cloud platform through a network to perform cloud configuration, so that related functions are realized.
Due to the fact that configuration files are too large and limited by the bandwidth of a public network, the cloud configuration of the FPGA consumes long time, the configuration speed of the FPGA cloud platform is too low, and the operation efficiency of the application is affected.
Therefore, how to efficiently compress the configuration file and reduce the size of the file to be transmitted is one of effective solutions to solve the problem of long time consumption for configuration.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an FPGA configuration file arithmetic compression and decompression method based on a neural network model to improve the compression rate of the configuration file, thereby effectively solving the problem of long time consumption in the configuration process.
The invention adopts the following technical scheme:
an FPGA configuration file arithmetic compression and decompression method based on a neural network model comprises the following steps:
s1, defining the content sequence of the FPGA configuration file, and taking the conditional probability distribution of any symbol under the condition of determining the front k items of data as the probability of the corresponding symbol in the arithmetic coding process;
s2, estimating the probability of each symbol in the FPGA configuration file by adopting a neural network model;
s3, arithmetic coding and compressing the symbolic probabilities of the FPGA configuration file predicted in the step S1 by using the neural network established in the step S2 by adopting arithmetic coding;
s4, decompressing the FPGA configuration file of the step S3.
Concretely, the stepsIn S1, binary code stream S of FPGA configuration fileNThe following were used:
SN＝{S1,S2,...,SN}
Si∈Ds,i＝1,2,...,N
wherein S isiFor one symbol in the sequence, the profile content sequence has a total of N symbols, Ds is the dictionary of symbols.
Specifically, step S2 specifically includes:
s201, constructing a neural network model by adopting an LSTM layer, and defining an input vector and an output vector of the neural network model;
s202, establishing a training set according to the input vector and the output vector of the neural network model defined in the step S201, training the neural network, optimizing the neural network by using a cross entropy loss function, and then estimating the probability of each symbol in the FPGA configuration file.
Further, in step S201, the neural network model receives an input vector as:
xi＝{Si-1,Si-2,...,Si-k}
the neural network model outputs an SiConditional probability distribution q (S) ofi|Si-1,...,Si-k) Comprises the following steps:
q(Si|Si-1,...,Si-k)＝{q1,q2,...,qm}
wherein S isiIs a symbol in the sequence, qjIs a symbol SiJ is the probability of the j-th term value in the symbol dictionary Ds, and j is 1, 2.
Furthermore, the neural network model comprises two LSTM layers and a full connection layer, wherein each of the two LSTM layers comprises 128 neurons; the full connection layer is provided with 2 neurons; the activation function of the fully connected layer is softmax.
Further, in step S202, the probability of each symbol in the FPGA configuration file is defined as: q (S)i) Go through the configuration file SNJudging whether each item of data of the sequence is the first k items of data, and if so, judging whether the data is the first k items of dataThen, using uniform probability distribution, specifically:
Figure BDA0002435592680000031
where M is the size of the symbol dictionary Ds, i ═ 1,2,3, …, k. To SiPerforming arithmetic coding compression; when i is>k, the previously defined neural network model is called to obtain the current data SiThe first k items of data (S)i-k,Si-k+1,...,Si-1) As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i)。
Further, the cross entropy loss function is:
Figure BDA0002435592680000032
according to the information theory, when the distribution p is coded using the distribution q, the average code length is:
H(p,q)＝-∑p(x)log(q(x))
when the number of training samples tends to infinity, the cross entropy loss function specifically includes:
Figure BDA0002435592680000033
where p (x) is the probability density function of distribution p and q (x) is the probability density function of distribution q.
Specifically, in step S3, the arithmetic coding compression process is:
traverse configuration file SNJudging whether each item of data of the sequence is front k items of data, if so, using uniform probability distribution, and if so, judging whether each item of data of the sequence is front k items of data>k, calling the defined neural network model to obtain current data SiThe first k items of data Si-k,Si-k+1,...,Si-1As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i) Using estimated probability distribution pairs SiPerforming arithmetic coding compression; the above operations are circulated until the configuration file is finished; compiling the final arithmeticThe code result is used as the compression result of the FPGA configuration file.
Specifically, the uniform probability distribution is as follows:
Figure BDA0002435592680000041
where M is the size of the symbol dictionary Ds, i is 1,2,3, …, k, for SiAnd performing arithmetic coding compression.
Specifically, in step S4, the decompression process includes:
circularly traversing each bit of the compressed data from the highest bit to judge whether the data is the front k items of data, if the data is the front k items of data, using uniform probability distribution, and when the data is the front k items of data, i>When k, calling the defined neural network, taking the first k items of data of the current bit data as the input data of the neural network, and obtaining the estimated probability distribution q (S) of the current bit datai) Using the estimated probability distribution q (S)i) To SiPerforming arithmetic coding decompression; the above operations are circulated until the configuration file is finished; and taking the final arithmetic coding decompression result as an original FPGA configuration file.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention relates to an arithmetic compression and decompression method of an FPGA configuration file based on a neural network model, which compresses a sequence file of the FPGA configuration file by adopting arithmetic coding; and the LSTM neural network is used as a probability of predicting each symbol, improving the accuracy of the symbol probability used in arithmetic coding, thereby improving the compression rate.
Furthermore, the FPGA configuration file is defined as a sequence file, and the conditional probability distribution of any symbol under the determination of the first k items of data is used as the probability of the symbol in the arithmetic coding process. The accuracy of the prediction probability is improved, the encoding length is reduced, and the compression rate is improved.
Furthermore, the invention predicts the probability of each symbol by a neural network, and can improve the accuracy of the predicted probability compared with static and some adaptive arithmetic coding.
Further, the purpose of using the LSTM neural network is that for sequence data, the LSTM may take into account the effect of previous input content on the current input content, and is more suitable for sequence data. The purpose of adopting the network structure is to obtain better prediction results.
Furthermore, the probability of each symbol in the FPGA configuration file which is accurately estimated is a precondition for obtaining an excellent arithmetic coding result.
Further, the arithmetic coding is used for the purpose that it is a kind of source coding and also an optimal coding. The optimal coding means that theoretically, if the information source symbol and the symbol probability thereof are determined, the average coding length of arithmetic coding is gradually increased to the average symbol entropy, namely the optimal compression ratio is approached theoretically.
Furthermore, the purpose of decompression is to restore the configuration file content without loss, so that the target chip can be loaded and operated after being electrified, and the corresponding circuit function is completed.
In summary, the invention uses the neural network model to perform probability estimation of the configuration file sequence data, and uses the estimation result to compress and decompress the FPGA configuration file, thereby solving the problem of long time consumption in the FPGA configuration process.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a diagram of a neural network model for an LSTM layer architecture;
FIG. 2 is a compression flow diagram of the present invention;
fig. 3 is a decompression flow chart according to the present invention.
Detailed Description
The invention relates to an arithmetic compression and decompression method for an FPGA (field programmable gate array) configuration file based on a neural network model, which comprises the following steps of:
adopting an FPGA configuration file compression strategy of arithmetic coding;
arithmetic coding is one of source coding, which is an optimal coding; the optimal coding means that theoretically, if the information source symbol and the symbol probability thereof are determined, the average coding length of arithmetic coding is gradually increased to the average symbol entropy, namely the optimal compression ratio is approached to the theoretical; however, the data content in the FPGA configuration file is unpredictable, and the data is related to the data before and after the data, and cannot be regarded as a memoryless source.
Simply regarding the frequency of each symbol in the data as the probability of each symbol, and arithmetic compression using it cannot achieve the optimal compression rate; according to the information theory, the distribution p is coded by adopting the distribution q, the average coding length of the distribution p is increased compared with the optimal coding of the distribution p by adopting the distribution p, the average coding length is specifically represented by relative entropy D (p | | q), the meaning is the difference between the distribution p coded by the distribution q and the optimal coding of the distribution p by adopting the distribution p, and specifically:
Figure BDA0002435592680000061
where p (x) is the probability density function of distribution p and q (x) is the probability density function of distribution q.
Therefore, if the configuration file is compressed by using arithmetic coding, the probability of whether each symbol item in the configuration file can be accurately estimated directly influences the performance of the arithmetic coding.
S1, defining content sequence of FPGA configuration file
The FPGA configuration file is a binary file and comprises a plurality of binary code streams consisting of 0 and 1, wherein the most important part is description of all available resources on an FPGA chip which needs to be configured, and the generation process comprises the following steps:
in the FPGA program development process, computer aided design tools such as: ISE, VIVADO and the like use coding rules, sequentially convert available resources of the chip into binary streams according to the positions of the available resources on the chip in a mode of 'instruction + data', store the binary streams in a configuration file, transmit the configuration file to a flash on a target FPGA (field programmable gate array), load the file after being powered on and started up, and sequentially configure the resources in the chip according to information provided by the file, thereby realizing related application.
As can be seen from the above, the part of the configuration file describing the chip resources is sequence data; moreover, due to the requirement of FPGA layout and wiring, the adjacent resources in the spatial position can be commonly used for realizing one device or module, so that the appearance probability of each symbol for describing the resources is related to the adjacent symbols.
Thus, the profile content sequence is defined as follows:
SN＝{S1,S2,...,SN}
Si∈Ds,i＝1,2,...,N
wherein S isiFor one symbol in the sequence, the profile content sequence has a total of N symbols, Ds is the dictionary of symbols.
Since the occurrence probability of a symbol in a sequence is related to the symbol before the symbol, the conditional probability distribution of an arbitrary symbol under the determination of the first k items of data is taken as the probability of the symbol in the arithmetic coding process; namely: symbol Si1,2, N has a conditional probability distribution of q (S)i|Si-1,...,Si-k)。
S2, estimating symbol probabilities in the FPGA configuration file by adopting a neural network model;
s201, defining input and output of a neural network model;
for the symbol SiN, the neural network model accepts an input vector as:
xi＝{Si-1,Si-2,...,Si-k}
i.e. k symbols before the ith symbol.
The neural network model outputs an SiConditional probability distribution q (S) ofi|Si-1,...,Si-k) Comprises the following steps:
q(Si|Si-1,...,Si-k)＝{q1,q2,...,qm}
wherein q isjIs a symbol SiJ is the probability of the j-th term value in the symbol dictionary Ds, and j is 1, 2.
S202, training a neural network to learn a required mode;
the neural network training needs a training set, the training set comprises input vectors and output vectors which are in one-to-one correspondence, and the method specifically comprises the following steps:
the i-th input vector is defined as xi(ii) a The ith term output vector is defined as the one-hot encoding of the ith symbol in the symbol sequence as:
yi＝{0,0,...,1,0,...,0}
wherein, yiThere are M components.
For any component j, if and only if the sign Si1 is taken when the j-th term is the same as the Ds term, and the remaining components are 0.
Loss function for neural networks using cross-entropy loss function
Figure BDA0002435592680000081
According to the information theory, when the distribution p is coded using the distribution q, the average code length is:
H(p,q)＝-∑p(x)log(q(x))
where p (x) is the probability density function of distribution p and q (x) is the probability density function of distribution q.
When the number of training samples is large enough, the cross entropy loss function is specifically:
Figure BDA0002435592680000082
therefore, neural network optimization using a cross entropy loss function can reduce the compressed file size.
Defining the probability of each symbol in the FPGA configuration file as follows: q (S)i) The specific acquisition method comprises the following steps: traverse configuration file SNJudging whether each item of data of the sequence is front k items of data, and if so, using uniform probability distribution
Figure BDA0002435592680000083
Where M is the size of the symbol dictionary Ds, i ═ 1,2,3, …, k. To, forSiAnd performing arithmetic coding compression. When i is>k, the previously defined neural network model is called to obtain the current data SiThe first k items of data (S)i-k,Si-k+1,...,Si-1) As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i)。
S3, carrying out arithmetic coding compression on the FPGA configuration file by using a neural network;
referring to fig. 2, the arithmetic coding compression process is:
traverse configuration file SNJudging whether each item of data of the sequence is front k items of data, if so, using uniform probability distribution, and if so, when i is>k, the previously defined neural network model is called to obtain the current data SiThe first k items of data (S)i-k,Si-k+1,...,Si-1) As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i) Using the estimated probability distribution pair SiPerforming arithmetic coding compression; the above operations are circulated until the configuration file is finished; and the final arithmetic coding result is a compression result of the FPGA configuration file.
The uniform probability distribution is as follows:
Figure BDA0002435592680000091
where M is the size of the symbol dictionary Ds, i is 1,2,3, …, k, for SiAnd performing arithmetic coding compression.
S4, carrying out decompression strategy on the FPGA configuration file of the step S3;
referring to fig. 3, after the compressed sequence data is transmitted to the FPGA cloud server, a special decompression unit disposed at the server management node performs a decompression operation, where the specific decompression process is as follows:
circularly traversing each bit of the compressed data from the highest bit to judge whether the data is the front k items of data, if the data is the front k items of data, using uniform probability distribution, and when the data is the front k items of data, i>k, the previously defined neural network is called to obtain the current bitThe first k items of data are used as input data of a neural network to obtain an estimated probability distribution q (S) of the current bit datai) Using the estimated probability distribution pair SiPerforming arithmetic coding decompression; the above operations are circulated until the configuration file is finished; and the final arithmetic coding decompression result is the original FPGA configuration file.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
Taking V5_ crossbar. bit test data realized by Xilinx Virtex-V development board in standard test set of computer department of university of Irlangen-New England Germany as an example, the configuration file 8179byte specifically comprises:
s1, adopting the FPGA profile compression strategy of arithmetic coding, defining the symbol as bit (bit), so Ds ═ 0,1, SNI.e. a binary code stream of the configuration file, k is set to 64;
and S2, estimating symbol probabilities in the FPGA configuration file by adopting the neural network model, and constructing the neural network model by adopting an LSTM layer because the value of the symbol is correlated with the previous symbol value. The model is composed of 2 LSTM layers and a full connection layer, and the structure of the model is shown in figure 1, wherein the LSTM layer 1 and the LSTM layer 2 are respectively provided with 128 neurons; the full connection layer is provided with 2 neurons; the full connection layer activation function is softmax; optimizing the neural network model by an Adam optimizer;
s3, traversing configuration file SNJudging whether each item of data of the sequence is front k items of data, if so, using uniform probability distribution, and if so, when i is>k, the previously defined neural network model is called to obtain the current data SiThe first k items of data (S)i-k,Si-k+1,...,Si-1) As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i) Using the estimated probability distribution pair SiPerforming arithmetic coding compression; the above operations are circulated until the configuration file is finished; the final arithmetic coding result is a compression result of the FPGA configuration file;
s4, circularly traversing each bit of the compressed data from the highest bit, judging whether the data is the front k items of data, if the data is the front k items of data, using uniform probability distribution, and when i is the front k items of data>When k, calling the previously defined neural network, and taking the first k items of data of the current bit data as the input data of the neural network to obtain the estimated probability distribution q (S) of the current bit datai) Using the estimated probability distribution pair SiPerforming arithmetic coding decompression; the above operations are circulated until the configuration file is finished; the final arithmetic coding decompression result is an original FPGA configuration file;
the uniform probability distribution is as follows:
Figure BDA0002435592680000111
where M is the size of the symbol dictionary Ds, i is 1,2,3, …, k, for SiPerforming arithmetic coding decompression; since symbols are defined as bits, M is 2 and k is 64. So for SNThe first 64 data items, using a uniform probability distribution, are as follows:
q(Si)＝0.5
wherein i is 1,2,3, …, 64.
Using the compression method of the present invention, set k to 64, the compressed profile size was 3672 bytes, and the compression rate was 44.89%.
In summary, the invention provides a neural network model-based FPGA configuration file arithmetic compression and decompression method, and aims at the problems that an FPGA configuration file is too large and time consumption required for one-time configuration is high.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (9)

1. An FPGA configuration file arithmetic compression and decompression method based on a neural network model is characterized by comprising the following steps:
s1, defining the content sequence of the FPGA configuration file, and taking the conditional probability distribution of any symbol under the condition of determining the front k items of data as the probability of the corresponding symbol in the arithmetic coding process;
s2, estimating the probability of each symbol in the FPGA configuration file by adopting a neural network model;
s3, arithmetic coding and compressing each symbol probability of the FPGA configuration file predicted in the step S1 by adopting arithmetic coding and using the neural network established in the step S2, wherein the arithmetic coding and compressing process comprises the following steps:
traverse configuration file SNJudging whether each item of data of the sequence is front k items of data, if so, using uniform probability distribution, and if so, judging whether each item of data of the sequence is front k items of data>k, calling the defined neural network model to obtain current data SiThe first k items of data Si-k,Si-k+1,...,Si-1As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i) Using estimated probability distribution pairs SiPerforming arithmetic coding compression; cycling through configuration files SNEach item of data of the sequence until the end of the configuration file; will eventuallyThe arithmetic coding result of (3) is used as the compression result of the FPGA configuration file;
s4, decompressing the FPGA configuration file of the step S3.
2. The neural network model-based FPGA configuration file arithmetic compression and decompression method as claimed in claim 1, wherein in step S1, the binary code stream S of the FPGA configuration fileNThe following were used:
SN＝{S1,S2,...,SN}
Si∈Ds,i＝1,2,...,N
wherein S isiFor one symbol in the sequence, the profile content sequence has a total of N symbols, Ds is the dictionary of symbols.
3. The neural network model-based FPGA configuration file arithmetic compression and decompression method according to claim 1, wherein step S2 specifically comprises:
s201, constructing a neural network model by adopting an LSTM layer, and defining an input vector and an output vector of the neural network model;
s202, establishing a training set according to the input vector and the output vector of the neural network model defined in the step S201, training the neural network, optimizing the neural network by using a cross entropy loss function, and then estimating the probability of each symbol in the FPGA configuration file.
4. The method according to claim 3, wherein in step S201, the neural network model receives an input vector as follows:
xi＝{Si-1,Si-2,...,Si-k}
the neural network model outputs an SiConditional probability distribution q (S) ofi|Si-1,...,Si-k) Comprises the following steps:
q(Si|Si-1,...,Si-k)＝{q1,q2,...,qm}
wherein S isiIs a symbol in the sequence, qjIs a symbol SiJ is the probability of the j-th term value in the symbol dictionary Ds, and j is 1, 2.
5. The neural network model-based FPGA configuration file arithmetic compression and decompression method of claim 4, wherein the neural network model comprises two LSTM layers and a fully connected layer, the two LSTM layers each having 128 neurons; the full connection layer is provided with 2 neurons; the activation function of the fully connected layer is softmax.
6. The neural network model-based FPGA configuration file arithmetic compression and decompression method as claimed in claim 3, wherein in step S202, the probability of each symbol in the FPGA configuration file is defined as: q (S)i) Go through the configuration file SNJudging whether each item of data of the sequence is front k items of data, if so, using uniform probability distribution, specifically:
Figure FDA0003191767080000021
where M is the size of the symbol dictionary Ds, i is 1,2,3, …, k, for SiPerforming arithmetic coding compression; when i is>k, the previously defined neural network model is called to obtain the current data SiThe first k items of data (S)i-k,Si-k+1,...,Si-1) As input data for the neural network model, S is obtainediIs estimated to be a probability distribution q (S)i)。
7. The neural network model-based FPGA configuration file arithmetic compression and decompression method of claim 6, wherein the cross entropy loss function is:
Figure FDA0003191767080000022
according to the information theory, when the distribution p is coded using the distribution q, the average coding isThe code length is:
H(p,q)＝-∑p(x)log(q(x))
when the number of training samples tends to infinity, the cross entropy loss function specifically includes:
Figure FDA0003191767080000031
where p (x) is the probability density function of distribution p and q (x) is the probability density function of distribution q.
8. The neural network model-based FPGA configuration file arithmetic compression and decompression method as claimed in claim 1, wherein in step S3, the uniform probability distribution is as follows:
Figure FDA0003191767080000032
where M is the size of the symbol dictionary Ds, i is 1,2,3, …, k, for SiAnd performing arithmetic coding compression.
9. The neural network model-based FPGA configuration file arithmetic compression and decompression method according to claim 1, wherein in step S4, the decompression process is:
circularly traversing each bit of the compressed data from the highest bit to judge whether the data is the front k items of data, if the data is the front k items of data, using uniform probability distribution, and when the data is the front k items of data, i>When k, calling the defined neural network, taking the first k items of data of the current bit data as the input data of the neural network, and obtaining the estimated probability distribution q (S) of the current bit datai) Using the estimated probability distribution q (S)i) To SiPerforming arithmetic coding decompression; until the configuration file is finished; and taking the final arithmetic coding decompression result as an original FPGA configuration file.
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