CN111429861B

CN111429861B - Digital 16-tube silicon-based liquid crystal display chip pixel circuit and driving method thereof

Info

Publication number: CN111429861B
Application number: CN202010338235.7A
Authority: CN
Inventors: 代永平
Original assignee: Nankai University
Current assignee: Nankai University
Priority date: 2020-04-26
Filing date: 2020-04-26
Publication date: 2021-02-02
Anticipated expiration: 2040-04-26
Also published as: CN111429861A

Abstract

The invention provides a digital 16-tube silicon-based liquid crystal display chip pixel circuit and a driving method thereof, relates to the field of silicon-based display system integrated circuit application of microelectronic science and technology, and comprises a1 st latch, a2 nd latch, a level inversion gate and a level conversion gate which are mainly composed of 16 MOS transistors, and an electrical series structure is formed. The MOS tubes only work in a switching state and accord with the digital circuit specification, so that the manufacturing process difficulty of an MOS device is greatly reduced, and the problem of electric leakage caused by using a capacitor is avoided; the driving method can divide the action time of each bit of digital data into a positive electric field and a negative electric field, thereby realizing the alternating current driving of the liquid crystal material and ensuring that the power supply voltage supply value of the pixel circuit is not lower than the working voltage of the liquid crystal material.

Description

Digital 16-tube silicon-based liquid crystal display chip pixel circuit and driving method thereof

Technical Field

The invention belongs to the field of silicon-based display system integrated circuit application of microelectronic science and technology, and particularly relates to the field of digital silicon-based liquid crystal display chip pixel circuits.

Background

The manufacturing technique of the monocrystalline silicon plane device is respectively fused with active or passive Display techniques such as Liquid Crystal Display (LCD) technique, Organic Light-Emitting Diode (OLED) technique and the like to generate various silicon-based displays, for example, a silicon-based-Liquid Crystal-glass sandwich structure device technique combined with the Liquid Crystal Display technique, the technique is used for manufacturing a novel reflective LCD Display device, firstly, a silicon substrate containing an active addressing matrix chip is manufactured on a monocrystalline silicon chip by using a Metal Oxide Semiconductor (MOS) process, then, a Metal layer with a smooth surface is plated to serve as a driving electrode and a reflecting mirror surface, finally, the silicon substrate is attached to a glass substrate containing a transparent electrode, a Liquid Crystal material is filled in the middle to form a reflective Liquid Crystal screen, and the output level of each pixel electrode in the active addressing matrix on the silicon substrate is modulated, thereby controlling the intensity (gray scale) of the reflected light amplitude by the liquid crystal material to realize image display. (Chris Chinnock, "microdisplay and Manufacturing Infrastructure matrix at SID 2000" [ Information Display, 9/2000, P18).

In general, a pixel cell circuit of a Chip active addressing matrix is composed of 1N-channel Metal Oxide Semiconductor (NMOS) transistor and 1 capacitor connected in series (r.ishii, s.katayama, h.oka, s.yamazaki, s.lino "u.efron, i.david, v.silicon nikov, b.ap ter" a CMOS/LCOS Image driver Chip FOR rt Smart Applications "[ IEEE TRANSACTIONS CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY ], volume 14, phase 2, month 2004, P269), wherein the gate of the NMOS transistor is connected to a row scanner addressing signal output terminal. However, when a single NMOS transistor transmits a high level, not only the threshold voltage loss occurs, but also the transient characteristics of the transmission process are not ideal (chen gui el et al, CMOS integrated circuit design, seian university press, 1999.9, P110).

Disclosure of Invention

In order to meet the requirement that a driven liquid crystal material works in an alternating current state, a conventional silicon-based liquid crystal display chip pixel circuit needs to set one half of power supply voltage as a fixed public level, namely the public level value is not smaller than the maximum linear working voltage value of the liquid crystal material, so that the power supply voltage supply value is not lower than twice of the working voltage of the liquid crystal material, and the high-voltage mode brings the problems of high power consumption, high process difficulty of a high-voltage MOS device and the like. The silicon-based active addressing matrix pixel unit circuit formed by 16 MOS transistors (16T for short) provided by the invention has the advantages that the MOS transistors only work in a switching state and accord with the digital circuit specification, so that the manufacturing process difficulty of an MOS device is greatly reduced, and the problem of electric leakage caused by using a capacitor is avoided; in addition, the pixel circuit driving method provided by the invention can equally divide the action time of each bit of digital data into a positive electric field and a negative electric field, thereby realizing the alternating current driving of the liquid crystal material and ensuring that the power supply voltage supply value of the pixel circuit is not lower than the working voltage of the liquid crystal material.

The technical scheme of the invention is as follows:

a digital 16-tube silicon-based liquid crystal display chip pixel circuit mainly comprises a 1-NMOS tube, a 2-PMOS tube, a 3-NMOS tube, a 3-PMOS tube, a 4-NMOS tube, a 5-PMOS tube, a 6-NMOS tube, a 6-PMOS tube, a 7-NMOS tube, a 7-PMOS tube, an 8-NMOS tube, a 9-NMOS tube, a 10-PMOS tube and a 10-NMOS tube, and particularly comprises the 1-NMOS tube, the 2-PMOS tube, the 3-NMOS tube, the 3-PMOS tube, the 4-NMOS tube, the 5-PMOS tube, the 6-NMOS tube, the 6-PMOS tube, the 7-NMOS tube, the 7-PMOS tube, the 8-NMOS tube, The 9 th-NMOS tube adopts a low-voltage MOS tube structure with the working voltage not more than 2.0V, and the 10 th-PMOS tube and the 10 th-NMOS tube adopt high-voltage MOS tube structures with the working voltage not less than 2.0V;

wherein the 1 st NMOS tube, the 2 nd PMOS tube, the 3 rd NMOS tube, the 3 rd PMOS tube, the 4 th NMOS tube, the 1 st connecting line and the 2 nd connecting line form a1 st latch;

the 8 th NMOS tube, the 6 th PMOS tube, the 7 th NMOS tube, the 7 th PMOS tube, the 9 th NMOS tube, the 3 rd connecting wire and the 4 th connecting wire form a2 nd latch;

the 5 th PMOS tube and the 5 th NMOS tube form a level inversion gate together with the 3 rd connecting line, the 4 th connecting line and the 5 th connecting line, and the 5 th PMOS tube and the 5 th NMOS tube respectively transmit an electric signal on the 3 rd connecting line and an electric signal on the 4 th connecting line to the 5 th connecting line alternately;

the 10 th NMOS tube and the 10 th PMOS tube form a level conversion gate together with a reverse control line, a 5 th connecting line, a pixel unit output electrode, a simulation low level line and a simulation high level line, and the 10 th NMOS tube and the 10 th PMOS tube are controlled by signals on the reverse control line to respectively and alternately transmit a fixed level on the simulation low level line and a fixed level on the simulation high level line to the pixel unit output electrode;

and the 1 st latch, the 2 nd latch, the level inversion gate and the level conversion gate form an electrical series structure,

the pixel circuit of the digital silicon-based liquid crystal display chip is also provided with: addressing lines, inversion control lines, digital power lines, digital ground lines, positive phase lines, negative phase lines, Vcom synchronous signal lines, output control lines, reset control lines, analog high-level lines, analog low-level lines and pixel unit output electrodes are electrically connected with the 16 MOS transistors respectively, and the fixed level value on the analog low-level lines is not higher than that on the analog high-level lines;

the invention discloses a pixel circuit driving method of a digital silicon-based liquid crystal display chip, which comprises the following steps:

in at least any two adjacent, front and rear signal periods of the pulse wave signal Vcom transmitted on the common electrode, the first step mainly involves the 1 st latch: sampling a pair of inverted levels on the positive phase line and the negative line bit line into the 1 st latch in a previous signal cycle; the second step mainly involves the 2 nd latch, the level inversion gate, the level conversion gate: the level stored by the 1 st latch is sampled and stored in the 2 nd latch in the first half signal period of the next signal period, and meanwhile, a pair of inverted electric signal waveforms stored by the 2 nd latch are intercepted alternately by controlling the level inversion gate and synthesized into an electric signal to be output to the level conversion gate; the third step mainly involves the 2 nd latch, the level inversion gate, the level conversion gate: in the second half signal period of the next signal period, storing the level sampling on the Vcom synchronous signal line into the 2 nd latch, and simultaneously, controlling the level inversion gate to alternately intercept a pair of inverted electrical signal waveforms stored in the 2 nd latch and synthesize an electrical signal to output to the level conversion gate, and finally controlling to select a fixed low level on the analog low level line to output to the pixel unit output electrode or select a fixed high level on the analog high level line to output to the pixel unit output electrode, so as to achieve the purpose of alternately inputting a fixed level on the analog low level line and a fixed level on the analog high level line to the pixel unit output electrode;

the driving method further includes: while the second and third operations are performed in the next signal cycle, the first operation can be performed in the 1 st latch, that is: while the level on the data bit line is sampled and stored into the 1 st latch again, the second step, the third step and the first step in the 1 st latch are repeated in the 2 nd latch, the level inversion gate and the level conversion gate, respectively, in the signal period immediately following the signal period, and this continues, and corresponding to a plurality of consecutive signal periods of the pulse wave signal Vcom transmitted on the common electrode, the electric signal can be outputted continuously at the pixel unit output electrode.

The invention has the beneficial effects that:

compared with the prior art, the invention has four advantages. Firstly, a digital pixel unit circuit composed of 16 MOS transistors and a driving method thereof are provided, which are completely matched with the chip production process of the conventional MOS semiconductor digital logic circuit; secondly, a level inversion gate structure is configured in the same pixel unit circuit, so that each bit of digital data stored in the pixel unit circuit can alternately control the output result of the pixel circuit in positive phase and reverse phase within the storage time; thirdly, a level conversion gate structure is configured in the same pixel unit circuit, so that the high and low levels output from the pixel unit output electrode can modify the level value; and fourthly, the 14 MOS tubes in the same pixel unit circuit can adopt transistors with lower working voltage, so that the space size of the pixel unit circuit is greatly reduced.

Drawings

FIG. 1 is a schematic diagram of a pixel circuit of a digital LCOS display chip composed of 16 MOS transistors;

wherein: 1: addressing line, 2: inversion control line, 3: positive phase line, 4: 1-NMOS tube, 5: 1 st-NMOS gate, 6: digital ground, 7: 2 nd-NMOS gate, 8: analog low-level line, 9: 2 nd-NMOS transistor, 10: 2 nd-NMOS source, 11: 2 nd-NMOS drain, 12: 3-NMOS drain, 13: 3-NMOS source, 14: 3 rd-NMOS gate, 15: 3-NMOS transistor, 16: 4-NMOS source, 17: 4-NMOS transistor, 18: 4 th-NMOS gate, 19: 4-NMOS drain, 20: negative phase line, 21: 5 th-PMOS gate, 22: 5-PMOS tube, 23: 5 th-PMOS source, 24: 5-PMOS drain, 25: 6 th-NMOS gate, 26: 6 th-NMOS source, 27: 6 th-NMOS transistor, 28: 6 th-NMOS drain, 29: 7 th-NMOS drain, 30: 7 th-NMOS source, 31: 7 th-NMOS transistor, 32: 7 th-NMOS gate, 33: 5-NMOS drain, 34: 5-NMOS source, 35: 5-NMOS transistor, 36: 5 th-NMOS gate, 37: level inverting gate, 38: vcom synchronization signal line, 39: 5 th connecting line, 40: 10 th-NMOS gate, 41: 10-NMOS transistor, 42: 10-NMOS source, 43: 10-NMOS drain, 44: pixel cell output electrode, 45: 10 th-PMOS drain, 46: 10 th-PMOS source, 47: 10 th-PMOS gate, 48: 10 th-PMOS transistor, 49: level shift gate, 50: 9-NMOS drain, 51: 9 th-NMOS gate, 52: 9-NMOS transistor, 53: 9-NMOS source, 54: 4 th connection line, 55: 7 th-PMOS gate, 56: 7 th-PMOS tube, 57: 7 th-PMOS drain, 58: 7 th-PMOS source, 59: 6 th-PMOS drain, 60: 6 th-PMOS source, 61: 6 th-PMOS gate, 62: 6 th-PMOS tube, 63: no. 3 connecting line, 64: 8 th-NMOS source, 65: 8 th-NMOS gate, 66: 8 th-NMOS transistor, 67: 8 th-NMOS drain, 68: latch 2, 69: latch 1, 70: 2 nd connecting line, 71: 3 rd-PMOS gate, 72: 3 rd-PMOS tube, 73: 3 rd-PMOS source, 74: 3-PMOS drain, 75: 2 nd-PMOS drain, 76: 2 nd-PMOS source, 77: 2 nd-PMOS tube, 78: 2 nd-PMOS gate, 79: 1 st connecting line, 80: 1 st-NMOS source, 81: analog high-level line, 82: 1 st-NMOS drain, 83: digital power supply line, 84: reset control line, 85: and outputting the control line.

Fig. 2 is a waveform diagram of one of the 1 st latch 69 application scenarios, where:

sg _ n: a pulse wave signal transmitted on the addressing line 1;

da _ i: a pulse wave signal transmitted on the positive phase line 3;

daB _ i: a pulse wave signal transmitted on the negative phase line 20;

la 1: the 1 st connecting line 79 is used for transmitting pulse wave signals;

laB 1: the pulse wave signal transmitted on the 2 nd connecting line 70;

fig. 3 is a waveform diagram of one of the 2 nd latch 68 application scenarios, wherein:

laB 1: the pulse wave signal transmitted on the 2 nd connecting line 70;

ssh: the pulse wave signal transmitted on the output control line;

and (4) Svc: a pulse wave signal transmitted on the Vcom synchronization signal line 38;

sre: the pulse wave signal is transmitted on the reset control line;

la 2: the pulse wave signal transmitted on the 4 th connection line 54;

laB 2: the pulse wave signal transmitted on the 3 rd connecting line 63;

fig. 4 is a waveform diagram of one of the application scenarios of the level-inversion gate 37, in which:

and (C) Sc: the pulse wave signal transmitted on the inversion control line 2

la 2: the pulse wave signal transmitted on the 4 th connection line 54

laB 2: the pulse wave signal transmitted on the 3 rd connecting line 63

Vcpe: pulse wave signal transmitted on the 5 th connection line 39

Fig. 5 is a waveform diagram of one of the application scenarios of the level-shifting gate 49, in which:

vcpe: pulse wave signal transmitted on the 5 th connection line 39

VH: a fixed high level provided on the analog high level line

VL: a fixed low level provided on the analog low level line 8

Vpe: the pulse wave signal transmitted on the pixel unit output electrode 44

FIG. 6 is a schematic diagram of waveforms of one application scenario of the pixel circuit and the driving method thereof

VH: a fixed high level provided on the analog high level line

VL: a fixed low level provided on the analog low level line

Vpe: the pulse wave signal transmitted on the pixel unit output electrode 44

V1: high level of pulse wave signal transmitted on the common electrode

V0: low level of pulse wave signal transmitted on the common electrode

Vcom: pulse wave signal transmitted on the common electrode

Detailed Description

The technology of the present invention is further described in detail with reference to the accompanying drawing 1:

the invention relates to a digital 16-tube silicon-based liquid crystal display chip pixel circuit which mainly comprises a 1-NMOS tube 4, a 2-NMOS tube 9, a 2-PMOS tube 77, a 3-NMOS tube 15, a 3-PMOS tube 72, a 4-NMOS tube 17, a 5-NMOS tube 35, a 5-PMOS tube 22, a 6-NMOS tube 27, a 6-PMOS tube 62, a 7-NMOS tube 31, a 7-PMOS tube 56, an 8-NMOS tube 66, a 9-NMOS tube 52, a 10-PMOS tube 48 and a 10-NMOS tube 41, and particularly comprises the 1-NMOS tube 4, the 2-NMOS tube 9, the 2-NMOS tube 77, the 3-NMOS tube 15, the 3-PMOS tube 72, the 4-NMOS tube 17, the 5-NMOS tube 35, the 5-PMOS tube 22, the 6-NMOS tube 27, the 3-NMOS tube 27, The 6 th-PMOS tube 62, the 7 th-NMOS tube 31, the 7 th-PMOS tube 56, the 8 th-NMOS tube 66 and the 9 th-NMOS tube 52 adopt low-voltage MOS tube structures with working voltage not more than 2.0V, and the 10 th-PMOS tube 48 and the 10 th-NMOS tube 41 adopt high-voltage MOS tube structures with working voltage not less than 2.0V.

The pixel circuit of the digital silicon-based liquid crystal display chip is also provided with: addressing line 1, inversion control line 2, digital power supply line 83, digital ground line 6, positive phase line 3, negative phase line 20, Vcom synchronization signal line 38, output control line 85, reset control line 84, simulation high level line 81, simulation low level line 8, pixel unit output electrode 44 constitute the electricity with 16 MOS transistors respectively and are connected, just fixed level value on the simulation low level line 8 is not higher than fixed level value on the simulation high level line 81.

The 1 st-NMOS transistor 4, the 2 nd-NMOS transistor 9, the 2 nd-PMOS transistor 77, the 3 rd-NMOS transistor 15, the 3 rd-PMOS transistor 72, the 4 th-NMOS transistor 17, the 1 st connection line 79 and the 2 nd connection line 70 form a1 st latch 69, wherein the 2 nd-NMOS transistor 9 and the 2 nd-PMOS transistor 77 form an inverter structure and transmit the electric signal on the 1 st connection line 79 in an inverted manner to the 2 nd connection line 70, and the 3 rd-NMOS transistor 15 and the 3 rd-PMOS transistor 72 form an inverter structure and transmit the electric signal on the 2 nd connection line 70 in an inverted manner to the 1 st connection line 79;

wherein the 8 th NMOS transistor 66, the 6 th NMOS transistor 27, the 6 th PMOS transistor 62, the 7 th NMOS transistor 31, the 7 th PMOS transistor 56, the 9 th NMOS transistor 52, the 3 rd connection line 63 and the 4 th connection line 54 form a2 nd latch 68, wherein the 6 th NMOS transistor 27 and the 6 th PMOS transistor 62 form an inverter structure and transmit the electric signal on the 3 rd connection line 63 to the 4 th connection line 54 in reverse phase, and the 7 th NMOS transistor 31 and the 7 th PMOS transistor 56 form an inverter structure and transmit the electric signal on the 4 th connection line 54 to the 3 rd connection line 63 in reverse phase;

the 5-PMOS tube 22 and the 5-NMOS tube 35, the 3 rd connection line 63, the 4 th connection line 54 and the 5 th connection line 39 form a level inversion gate 37, and the 5-PMOS tube 22 and the 5-NMOS tube 35 respectively transmit the electric signal on the 3 rd connection line 63 and the electric signal on the 4 th connection line 54 to the 5 th connection line 39 alternately;

wherein the 10-NMOS transistor 41, the 10-PMOS transistor 48, the inversion control line 2, the 5 th connection line 39, the pixel unit output electrode 44, the analog low level line 8, and the analog high level line 81 constitute a level shift gate 49, and the 10-NMOS transistor 41, the 10 th PMOS transistor 48 are controlled by the signal on the inversion control line 2 to alternately transmit the fixed level on the analog low level line 8 and the fixed level on the analog high level line 81 to the pixel unit output electrode 44, respectively;

and the 1 st latch 69, the 2 nd latch 68, the level inversion gate 37 and the level conversion gate 49 form an electrical series structure.

The specific circuit connection mode is as follows:

in the 1 st latch 69, the 1 st-NMOS gate 5, the 4 th-NMOS gate 18 are connected to the addressing line 1, and the 1 st-NMOS drain 82 is connected to the positive phase line 3, and the 4 th-NMOS drain 19 is connected to the negative phase line 20.

And the 1 st-NMOS source 80, the 2 nd-NMOS gate 7, the 2 nd-PMOS gate 78, the 3 rd-NMOS drain 12 and the 3 rd-PMOS drain 74 are connected to the 1 st connection line 79;

and the 4 th-NMOS source 16, the 3 rd-NMOS gate 14, the 3 rd-PMOS gate 71, the 2 nd-NMOS drain 11, and the 2 nd-PMOS drain 75 are connected to the 2 nd connection line 70;

and the 2 nd-PMOS source 76 and the 3 rd-PMOS source 73 are connected to the digital power line 83;

and the 2 nd-NMOS source electrode 10 and the 3 rd-NMOS source electrode 13 are connected with the digital ground wire 6;

in the 2 nd latch 68, the 8 th-NMOS gate 65 is connected to the output control line 85, the 8 th-NMOS drain 67 is connected to the 2 nd connection line 70, the 9 th-NMOS gate 51 is connected to the reset control line 84, and the 9 th-NMOS drain 50 is connected to the Vcom synchronization signal line 38;

and the 8 th-NMOS source 64, the 6 th-NMOS gate 25, the 6 th-PMOS gate 61, the 7 th-NMOS drain 29 and the 7 th-PMOS drain 57 are connected to the 3 rd connection line 63;

and the 9 th-NMOS source 53, the 7 th-NMOS gate 32, the 7 th-PMOS gate 55, the 6 th-NMOS drain 28, and the 6 th-PMOS drain 59 are connected to the 4 th connection line 54.

In the level inversion gate 37, the 5 th-PMOS gate 21 and the 5 th-NMOS gate 36 are both connected to the inversion control line 2, the 5 th-PMOS drain 24 is connected to the 3 rd connection line 63, the 5 th-NMOS drain 33 is connected to the 4 th connection line 54, and the 5 th-PMOS source 23 and the 5 th-NMOS source 34 are both connected to the 5 th connection line 39;

in the level shift gate 49, the 10 th-NMOS gate 40 and the 10 th-PMOS gate 47 are both connected to the 5 th connection line 39, the 10 th-NMOS source 42 is connected to the analog low level line 8, the 10 th-PMOS source 46 is connected to the analog high level line 81, and the 10 th-NMOS drain 43 and the 10 th-PMOS drain 45 are both connected to the pixel unit output electrode 44.

at least any two adjacent, front and back signal periods of the pulse wave signal Vcom transmitted on the common electrode.

The first step mainly involves the 1 st latch 69: sampling a pair of inverted levels on the positive phase line 3 and the negative line bit line 20 into the 1 st latch 69 during a previous signal cycle;

the second step mainly involves the 2 nd latch 68, the level inversion gate 37, the level shift gate 49: the level stored in the 1 st latch 69 is sampled and stored in the 2 nd latch 68 in the first half of the latter signal period, and a pair of inverted electrical signal waveforms stored in the 2 nd latch 68 are alternately intercepted by controlling the level inversion gate 37 and synthesized into an electrical signal to be output to the level conversion gate 49;

the third step mainly involves the 2 nd latch 68, the level inversion gate 37, the level shift gate 49: the level on the Vcom synchronous signal line 38 is sampled and stored in the 2 nd latch 68 in the second half signal period of the next signal period, and at the same time, a pair of inverted electric signal waveforms stored in the 2 nd latch 68 are cut off alternately again by controlling the level inversion gate 37 and synthesized into an electric signal to be output to the level conversion gate 49;

finally, the fixed low level on the analog low level line 8 is selected to be output to the pixel unit output electrode 44, or the fixed high level on the analog high level line 81 is selected to be output to the pixel unit output electrode 44, so as to achieve the purpose of alternately inputting the fixed level on the analog low level line 8 and the fixed level on the analog high level line 81 to the pixel unit output electrode 44.

The driving method further includes: while the second and third operations are performed in the next signal cycle, the first operation may be performed in the 1 st latch 69, that is: the level samples from the positive phase line 3 and the negative bit line 20 are again stored in the 1 st latch 69, and the second step, the third step, and the first step in the 1 st latch 69 are repeated in the signal period of the immediately following signal period, which continues to be performed for a plurality of consecutive signal periods corresponding to the pulse wave signal Vcom transmitted on the common electrode, in the 2 nd latch 68, the level inversion gate 37, and the level conversion gate 49, respectively, so that an electric signal can be continuously output at the pixel unit output electrode 44.

The specific implementation method comprises the following steps:

in the 1 st latch 69, the first latch is selected,

the 1 st latch 69 enters an input data state when a high level is present on the addressing line 1, where: the 1 st-NMOS transistor 4 and the 4 th-NMOS transistor 17 are turned on simultaneously, wherein the positive phase signal level on the positive phase line 3 will be inputted to the 1 st connection line 79 through the 1 st-NMOS transistor 4, and the negative phase signal level on the negative phase line 20 will be inputted to the 2 nd connection line 70 through the 4 th-NMOS transistor 17, i.e. the electrical signal on the 1 st connection line 79 and the electrical signal on the 2 nd connection line 70 become a pair of non-overlapping signals in opposite phases, i.e. the stored signal in the 1 st memory 69 will be updated by the signals inputted from the positive phase line 3 and the negative phase line 20;

the 1 st latch 69 enters a latched data state when low on the addressing line 1, where: the 1 st NMOS transistor 4 and the 4 th NMOS transistor 17 are turned off at the same time, and the updated signal will be stored in the 1 st latch 69 until the addressing line 1 appears high again.

As shown in the waveform diagram of one of the application scenarios shown in figure 2 (the shaded portions in the figure represent omitted waveforms),

during time T1, the 1 st latch 69 enters an input data state in which: the pulse wave signal Sg _ n transmitted on the addressing line 1 is at a high level, and a high-level part identified by an ellipse 1 in the pulse wave signal da _ i transmitted on the positive phase line 3 is input to the 1 st connecting line 79 as schematically indicated by a one-way arrow line 1 to form a high-level part identified by an ellipse 2 in the pulse wave signal la1 transmitted on the 1 st connecting line 79; meanwhile, the low level part identified by ellipse 3 in the pulse wave signal daB _ i transmitted on the negative phase line 20 is inputted onto the 2 nd connection line 70 as schematically indicated by the one-way arrow line 2 and forms the low level part identified by ellipse 4 in the pulse wave signal laB1 transmitted on the 2 nd connection line 70;

when the 1 st latch 69 enters a latched data state within time T2, wherein: the pulse wave signal Sg _ n transmitted on the addressing line 1 is at a low level, the pulse wave signal la1 transmitted on the 1 st connecting line 79 maintains the same high level as the high level part identified by the ellipse 2, and synchronously, the pulse wave signal laB1 transmitted on the 2 nd connecting line 70 maintains the same low level as the low level part identified by the ellipse 4;

when the 1 st latch 69 enters an input data state within time T3, wherein: the pulse wave signal Sg _ n transmitted on the addressing line 1 is at a high level, and a low-level part identified by an ellipse 5 in the pulse wave signal da _ i transmitted on the positive phase line 3 is inputted as schematically indicated by a one-way arrow line 3 and updated to form a low-level part identified by an ellipse 6 in the pulse wave signal la1 transmitted on the 1 st connecting line 79; synchronously, the high level part identified by ellipse 7 in the pulse wave signal daB _ i transmitted on the negative phase line 20 is inputted and updated as schematically shown by the one-way arrow line 4 to form the high level part identified by ellipse 8 in the pulse wave signal laB1 transmitted on the 2 nd connecting line 70;

when the 1 st latch 69 enters a latched data state within time T4, wherein: the pulse wave signal Sg _ n transmitted on the addressing line 1 is at a low level, the pulse wave signal la1 transmitted on the 1 st connecting line 79 maintains the same low level value as the low level part identified by the ellipse 6, and simultaneously, the pulse wave signal laB1 transmitted on the 2 nd connecting line 70 maintains the same high level value as the high level part identified by the ellipse 8.

In the 2 nd latch 68 described above,

the signal on the output control line 85 and the electrical signal on the reset control line 84 are a pair of signals with high levels that do not overlap with each other, that is: the electrical signal on the output control line 85 is not allowed to be high at the same time as the electrical signal on the reset control line 84, but the electrical signal on the output control line 85 is allowed to be low at the same time as the electrical signal on the reset control line 84.

In particular, the present invention relates to a method for producing,

when the electrical signal on the output control line 85 is high and the electrical signal on the reset control line 84 is low, the 2 nd latch 68 enters the data input state from the 1 st latch 69, wherein: the 8 th NMOS transistor 66 is controlled to be turned on and the 9 th NMOS transistor 52 is controlled to be turned off, at which time the signal level on the 2 nd connecting line 70 is inputted to the 3 rd connecting line 63 through the 8 th NMOS transistor 66.

Further, the signal level on the 3 rd connection line 63 generates a signal level on the 4 th connection line 54 that is inverted from the signal level on the 3 rd connection line 63 through the circuit connection constructed by the 6 th-NMOS transistor 27 and the 6 th-PMOS transistor 62, and as a result, the original signal in the 2 nd latch 68 will be updated by the signal inputted from the 1 st latch 69.

When the electrical signal on the output control line 85 goes low and the electrical signal on the reset control line 84 remains low, the 2 nd latch 68 enters a latched data state in which: the 8 th NMOS transistor 66 is controlled to be turned off, and the 9 th NMOS transistor 52 is controlled to be still in an off state, the signal inputted from the 1 st latch 69 will be latched in the 2 nd latch 68 until the control line goes high again or until the signal level on the reset control line 84 goes high;

when the electrical signal on the reset control line 84 is high and the electrical signal on the output control line 85 is low, the 2 nd latch 68 enters the data state input from the Vcom synchronization signal line 38, where: the 9 th NMOS transistor 52 is controlled to be turned on and the 8 th NMOS transistor 66 is controlled to be turned off, at which time the signal level on the Vcom synchronization signal line 38 is inputted to the 4 th connection 54 through the 9 th NMOS transistor 52.

Further, the signal level on the 4 th connection line 54 generates a signal level on the 3 rd connection line 63 that is inverted from the signal level on the 4 th connection line 54 through the circuit connection constructed by the 7 th-NMOS transistor 31 and the 7 th-PMOS transistor 56, so that the original signal in the 2 nd latch 68 will be updated by the input signal on the Vcom synchronization signal line 38.

When the signal level on the Vcom synchronization signal line 38 changes to a low level and the signal level on the output control line 85 remains low, the 2 nd latch 68 enters a latched data state in which: the 9 th NMOS transistor 52 is controlled to be turned off and the 8 th NMOS transistor 66 is controlled to be still in the off state, at this time, the telecommunication input from the Vcom synchronization signal line 38 will be latched in the 2 nd latch 68 until the reset control line 84 is high again or the output control line 85 is high again.

One of the 2 nd latch 68 application scenarios shown in figure 3,

here, a waveform diagram illustrating a case where the frequency of the pulse wave signal Ssh transmitted on the output control line 85, the frequency of the pulse wave signal Sre transmitted on the reset control line 84, and the frequency of the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 are the same as the frequency of the pulse wave signal Vcom transmitted on the common electrode is described, and one of the characteristics includes: the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 is in reverse phase with the pulse wave signal Vcom transmitted on the common electrode, the high level of the pulse wave signal Ssh transmitted on the output control line 85 and the high level of the pulse wave signal Sre transmitted on the reset control line 84 respectively appear in two adjacent half periods of the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 and only appear once, and the second characteristic includes: the third characteristic is that a high-level up-jump edge Ssh _ upe of the pulse wave signal Ssh transmitted on the output control line 85 occurs first, then a jump edge Svc _ mde of the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 occurs after a time T23, then a high-level up-jump edge Sre _ upe of the pulse wave signal Sre transmitted on the reset control line 84 occurs after a time T24, and T23 and T24 are the same in time: the total time that one bit of arbitrary data (either high or low) occupies the 2 nd latch 68 is no more than the sum of the times T15, T16, T17, T18, where: the effective time of the 2 nd latch 68 for latching the one-bit data (either high level or low level) is the sum of the T23 and T24 times, the sum of the T23 and T24 times does not exceed the sum of the T15 and T16 times, T23 is regarded as the positive half field of the one-bit data and corresponds to the low level of the pulse wave signal Vcom transmitted on the common electrode, T24 is regarded as the negative half field of the one-bit data and corresponds to the high level of the pulse wave signal Vcom transmitted on the common electrode, and the sum of the remaining T17 and T18 times is the reset time.

In particular, the present invention relates to a method for producing,

when in time T15, the 2 nd latch 68 enters the input data state from the 1 st latch 69, where: the pulse wave signal Ssh transmitted on the output control line 85 is at a high level, and the pulse wave signal Sre transmitted on the reset control line 84 is at a low level, the waveform portion identified by the ellipse 51 in the pulse wave signal laB1 transmitted on the 2 nd connection line 70 is inputted to the 3 rd connection line 63 as indicated by the one-way arrow line 51 to form the waveform portion identified by the ellipse 52 in the pulse wave signal laB2 transmitted on the 3 rd connection line 63, and further, is inversely transmitted to the 4 th connection line 54 as indicated by the one-way arrow line 52 and forms the waveform portion identified by the ellipse 53 in the pulse wave signal la2 transmitted on the 4 th connection line 54;

when within time T16, the 2 nd latch 68 enters a latched data state in which: the pulse wave signal Ssh transmitted on the output control line 85 and the pulse wave signal Sre transmitted on the reset control line 84 are both at low level, the pulse wave signal la2 transmitted on the 4 th connection line 54 maintains the same waveform as the waveform portion identified by the ellipse 13, and synchronously, the pulse wave laB2 transmitted on the 3 rd connection line 63 maintains the same waveform as the waveform portion identified by the ellipse 12;

when in time T17, the 2 nd latch 68 enters the data state input from the Vcom synchronization signal line 38, where: the pulse wave signal Sre transmitted on the reset control line 84 is at high level, and the pulse wave signal Ssh transmitted on the output control line 85 is at low level, the waveform portion identified by the ellipse 54 in the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 is inputted to the 4 th connection line 54 as indicated by the one-way arrow line 53 to form the waveform portion identified by the ellipse 55 in the pulse wave signal la2 transmitted on the 4 th connection line 54, and further, is inversely transmitted to the 3 rd connection line 63 as indicated by the one-way arrow line 54 and forms the waveform portion identified by the ellipse 56 in the pulse wave signal laB2 transmitted on the 3 rd connection line 63;

when within time T18, the 2 nd latch 68 enters a latched data state in which: the pulse wave signal Ssh transmitted on the output control line 85 and the pulse wave signal Sre transmitted on the reset control line 84 are both at low level, the pulse wave signal la2 transmitted on the 4 th connection line 54 maintains the same waveform as the waveform portion identified by the ellipse 15, and synchronously, the pulse wave signal laB2 transmitted on the 3 rd connection line 63 maintains the same waveform as the waveform portion identified by the ellipse 16;

when in time T19, the 2 nd latch 68 enters the input data state from the 1 st latch 69, where: the pulse wave signal Ssh transmitted on the output control line 85 is at a high level, and the pulse wave signal Sre transmitted on the reset control line 84 is at a low level, the waveform portion identified by the ellipse 57 in the pulse wave signal laB1 transmitted on the 2 nd connection line 70 is inputted and formed as indicated by the one-way arrow line 55, the waveform portion identified by the ellipse 58 in the pulse wave signal laB2 transmitted on the 3 rd connection line 63 is further inputted and formed as indicated by the one-way arrow line 56, and further, the waveform portion identified by the ellipse 59 in the pulse wave signal la2 transmitted on the 4 th connection line 54 is inverted and formed as indicated by the one-way arrow line 56;

when in time T20, the 2 nd latch 68 enters the data state input from the Vcom synchronization signal line 38, where: the pulse wave signal Sre transmitted on the reset control line 84 is at a high level, and the pulse wave signal Ssh transmitted on the output control line 85 is at a low level, the waveform portion identified by the ellipse 60 in the pulse wave signal Svc transmitted on the Vcom synchronization signal line 38 is schematically input as indicated by the one-way arrow line 57 and forms the waveform portion identified by the ellipse 61 in the pulse wave signal la2 transmitted on the 4 th connection line 54, and further, the waveform portion identified by the ellipse 62 in the pulse wave signal laB2 transmitted on the 3 rd connection line 63 is schematically inverted and formed as indicated by the one-way arrow line 58.

In the level inversion gate 37:

when the signal level on the inversion control line 2 is low level, the 5 th-PMOS transistor 22 is controlled to be turned on, and the 5 th-NMOS transistor 35 is controlled to be in an off state, at this time, the signal level on the 3 rd connection line 63 is input to the 5 th connection line 39 through the 5 th-PMOS transistor 22;

when the signal level on the inversion control line 2 is high level, the 5 th NMOS transistor 35 is controlled to be turned on, and the 5 th PMOS transistor 22 is controlled to be in an off state, at this time, the signal level on the 4 th connection line 54 is input to the 5 th connection line 39 through the 5 th NMOS transistor 35;

as a result, when the signal on the inversion control line 2 is a square wave, the signal level on the 3 rd connection line 63 and the signal level on the 4 th connection line 54 are alternately input to the 5 th connection line 39.

A waveform diagram illustration of one of the application scenarios of the level-inversion gate 37 as shown in fig. 4;

here, a waveform diagram in the case where the frequency and the phase of the pulse wave signal Sc transmitted on the inversion control line 2 are the same as those of the pulse wave signal Vcom transmitted on the common electrode is described, and one of the characteristics includes: the signal on the 3 rd connection line 63 adopts the pulse wave signal laB2 transmitted on the 3 rd connection line 63 generated by the application scenario of fig. 3, and the signal on the 4 th connection line 54 adopts the pulse wave signal la2 transmitted on the 4 th connection line 54 generated by the application scenario of fig. 4, wherein: t21, T22 are any two adjacent half cycles of the pulse wave signal Sc transmitted on the inversion control line 2.

When the pulse wave signal Sc transmitted on the inversion control line 2 is at a low level during the time T21, the waveform portion identified by the ellipse 63 in the pulse wave signal laB2 transmitted on the 3 rd connection line 63 is inputted to the 5 th connection line 39 as indicated by the one-way arrow line 61 and forms the waveform portion identified by the ellipse 64 in the pulse wave signal Vcpe transmitted on the 5 th connection line 39;

when the pulse wave signal Sc transmitted on the inversion control line 2 is at a high level during the time T22, the waveform portion identified by the ellipse 65 in the pulse wave signal la2 transmitted on the 4 th connection line 54 is inputted to the 5 th connection line 39 as illustrated by the one-way arrow line 62 and forms the waveform portion identified by the ellipse 66 in the pulse wave signal Vcpe transmitted on the 5 th connection line 39;

as a result, when the signal Sc is a continuous square wave, the waveform of the pulse wave signal Vcpe transmitted on the 5 th connection line 39 is synthesized by alternately cutting out the partial waveform of the pulse wave laB2 transmitted on the 3 rd connection line 63 and the partial waveform of the pulse wave la2 transmitted on the 4 th connection line 54 on the 5 th connection line 39.

Meanwhile, in the level shift gate 49:

when the signal level on the 5 th connection line 39 is at a high level, the 10 th NMOS transistor 41 is controlled to be turned on, and the 10 th PMOS transistor 48 is controlled to be in an off state, at this time, the fixed level on the analog low level line 8 is input to the pixel unit output electrode 44 through the turned-on 10 th NMOS transistor 41;

when the signal level on the 5 th connection line 39 is at a low level, the 10 th PMOS transistor 48 is controlled to be turned on, and the 10 th NMOS transistor 41 is controlled to be in an off state, at this time, the fixed level on the analog high level line 81 is input to the pixel unit output electrode 44 through the turned-on 10 th PMOS transistor 48;

as a result the electrical signal on the 5 th connection line 39 will control the level shifting gate 49 to either output a fixed high level or to output a fixed low level and if the level value on the analog high level line 81 or the level value on the analog low level line 8 is changed, the output signal level value on the pixel cell output electrode 44 will follow the corresponding change.

As shown in fig. 5, the waveform diagram of one of the application scenarios of the level shift gate 49, here, it is described that the pulse wave signal Vcpe transmitted on the 5 th connection line 39 alternately intercepts fixed levels from the fixed low level VL provided on the analog low level line 8 and the fixed high level VH provided on the analog high level line 81 to generate a new waveform diagram, wherein: t13 and T14 are any two adjacent low and high levels of the pulse wave signal Vcpe transmitted on the 5 th connection line 39.

In particular, the present invention relates to a method for producing,

during a time T13, when the pulse wave signal Vcpe transmitted on the 5 th connection line 39 is at a high level, the level portion identified by the ellipse 31 in the fixed low level VL provided on the analog low level line 8 is inputted to the pixel cell output electrode 44 as indicated by the one-way arrow line 23 and forms the level portion identified by the ellipse 32 in the pulse wave signal Vpe transmitted on the pixel cell output electrode 44;

here, during the time T14, when the pulse wave signal Vcpe transmitted on the 5 th connection line 39 is at the low level, the level portion identified by the ellipse 34 in the fixed high level VH provided on the analog high level line 81 is inputted to the pixel-unit output electrode 44 as illustrated by the one-way arrow line 24 and forms the level portion identified by the ellipse 33 in the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44.

As a result, when the pulse wave signal Vcpe transmitted on the 5 th connection line 39 is a continuous square wave, the waveform of the pulse signal Vpe transmitted on the pixel unit output electrode 44 is synthesized by alternately intercepting the fixed low level VL provided on the analog low level line 8 and the fixed high level VH provided on the analog high level line 81 at the pixel unit output electrode 44, wherein the pulse signal Vpe transmitted on the pixel unit output electrode 44 and the pulse wave signal Vcpe transmitted on the 5 th connection line 39 are in an inverse relationship.

Finally, the voltage difference between the electrical signal output on the pixel cell output electrode 44 and the electrical signal applied on the Vcom common electrode will generate an electric field that will be used to control the physical properties of the liquid crystal material filled between the pixel cell output electrode 44 and the Vcom common electrode.

As shown in fig. 6, a waveform diagram of one application scenario of the pixel circuit and the driving method thereof of the present invention,

here, the electric field relationship between the pulse wave signal Vcom transmitted on the common electrode and the pulse wave signal Vpe transmitted on the pixel unit output electrode 44 generated in the form of the application scenario of fig. 4 is described, in which: the T31, T32 times are any two adjacent half cycles of the pulsed wave signal Vcom transmitted on the common electrode, and the T33, T34 times are the next two adjacent half cycles of the pulsed wave signal Vcom transmitted on the common electrode, which exemplify four implemented electric field relationships that may occur between the pulsed wave signal Vcom transmitted on the common electrode and the pulsed wave signal Vpe transmitted on the pixel cell output electrode 44 during the four times T31, T32, T33, T34, and one of the features includes: the voltage difference between the fixed low level VL provided on the analog low level line 8 and the low level V0 of the pulse wave signal transmitted on the common electrode must not exceed the threshold voltage of the driven liquid crystal material to form a zero electric field, and the voltage difference between the fixed high level VH provided on the analog high level line 81 and the high level V1 of the pulse wave signal transmitted on the common electrode must not exceed the threshold voltage of the driven liquid crystal material to form a zero electric field, which is not positive or negative and is negligible in controlling the physical properties of the liquid crystal material, and the two characteristics include: the fixed high level VH provided on the analog high level line 81 and the low level V0 of the pulse wave signal transmitted on the common electrode constitute a positive electric field, the fixed low level VL provided on the analog low level line 8 and the high level V1 of the pulse wave signal transmitted on the common electrode constitute a negative electric field, and the third characteristic comprises: the pulse wave signal Vpe transmitted to the pixel unit output electrode 44, which is generated finally after the application scenario of fig. 3, the application scenario of fig. 4, and the application scenario of fig. 5 are sequentially adopted, has the following characteristics: in at least any two adjacent, front and rear signal periods of the pulse wave signal Vcom transmitted on the common electrode, and after the pulse wave signal Vcom is inputted to the 1 st connection line 79 in the 1 st latch 69 through the positive phase line 3 and kept at the low level in the previous signal period and is synchronously inputted to the 2 nd connection line 70 in the 1 st latch 69 through the negative phase line 20 and kept at the high level in the previous signal period, a waveform having an alternating current driving function is present on the pulse wave signal Vpe transmitted on the pixel unit output electrode 44 generated in the subsequent signal period, and the waveform generates a pair of adjacent positive electric fields and negative electric fields with respect to the adjacent low level and high level in one period of the pulse wave signal Vcom transmitted on the common electrode, and the adjacent positive electric fields and negative electric fields constitute a significant control function on the physical properties of the liquid crystal material, or at least any two adjacent Vcom signals, a, In the preceding and following signal periods, and after the high level is inputted to the 1 st connection line 79 in the 1 st latch 69 through the positive phase line 3 and is maintained, and the low level is synchronously inputted to the 2 nd connection line 70 in the 1 st latch 69 through the negative phase line 20 and is maintained, a corresponding waveform exists on the pulse wave signal Vpe transmitted on the pixel unit output electrode 44 generated in the following signal period, and the corresponding waveform generates a pair of adjacent zero electric fields with respect to the adjacent low level and the high level in one period of the pulse wave signal Vcom transmitted on the common electrode, and the adjacent zero electric fields constitute a waveform having no significant control effect on the physical properties of the liquid crystal material.

In particular, the present invention relates to a method for producing,

during the time T31, a zero electric field is formed between the level part indicated by the ellipse 71 in the low level VL of the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44 and the level part indicated by the ellipse 73 in the low level V0 of the pulse wave signal Vcom transmitted on the common electrode as indicated by the one-way arrow line 5, and a positive electric field is formed between the level part indicated by the ellipse 72 in the high level VH of the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44 and the level part indicated by the ellipse 73 in the low level V0 of the pulse wave signal Vcom transmitted on the common electrode as indicated by the one-way arrow line 6;

during the time T32, a negative electric field is formed between the level portion indicated by the ellipse 74 in the low level VL of the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44 and the level portion indicated by the ellipse 75 in the high level V1 of the pulse wave signal Vcom transmitted on the common electrode as indicated by the one-way arrow line 7, and a zero electric field is formed between the level portion indicated by the ellipse 76 in the high level VH of the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44 and the level portion indicated by the ellipse 75 in the high level V1 of the pulse wave signal Vcom transmitted on the common electrode as indicated by the one-way arrow line 8;

during the time T33, a zero electric field is formed between the level portion identified by the ellipse 77 in the low level VL of the pulse wave signal Vpe transmitted on the pixel-unit output electrode 44, as indicated by the one-way arrow line 9, and the level portion identified by the ellipse 78 in the low level V0 of the pulse wave signal Vcom transmitted on the common electrode;

during the time T34, a zero electric field is formed between the level portion indicated by the ellipse 79 in the high level VH of the pulse wave signal Vpe transmitted on the pixel unit output electrode 44 and the level portion indicated by the ellipse 80 in the high level V1 of the pulse wave signal Vcom transmitted on the common electrode as indicated by the one-way arrow line 10;

as a result, adjacent positive electric fields and negative electric fields in adjacent times T31, T32 constitute an alternating current driving state to meet the characteristic that the driven liquid crystal material needs alternating current driving.

It should be understood that the present invention is not limited to the embodiments described herein, and that various modifications and changes obvious to those skilled in the art in light of the above teachings should be made without departing from the spirit and scope of the present invention.

Claims

1. The digital 16-tube silicon-based liquid crystal display chip pixel circuit is characterized in that: the 1 st latch is composed of a1 st latch, a2 nd latch, a level reversal gate and a level conversion gate, wherein the 1 st-NMOS tube, the 2 nd-PMOS tube, the 3 rd-NMOS tube, the 3 rd-PMOS tube, the 4 th-NMOS tube, a1 st connecting wire and a2 nd connecting wire; the 8 th-NMOS tube, the 6 th-PMOS tube, the 7 th-NMOS tube, the 7 th-PMOS tube, the 9 th-NMOS tube, the 3 rd connecting wire and the 4 th connecting wire form a2 nd latch; the 5 th PMOS tube, the 5 th NMOS tube, the 3 rd connecting wire, the 4 th connecting wire and the 5 th connecting wire form a level inversion gate; the 10 th NMOS tube, the 10 th PMOS tube, the inversion control line, the 5 th connecting line, the pixel unit output electrode, the analog low level line and the analog high level line form a level conversion gate, and the 1 st latch, the 2 nd latch, the level inversion gate and the level conversion gate form an electrical series connection structure; is also provided with: addressing lines, inversion control lines, digital power lines, digital ground lines, data bit lines, Vcom synchronous signal lines, output control lines, reset control lines, analog high-level lines, analog low-level lines and pixel unit output electrodes, wherein the addressing lines, the inversion control lines, the digital power lines, the digital ground lines, the data bit lines, the Vcom synchronous signal lines, the output control lines, the reset control lines, the analog high-level lines, the analog low-level lines and the pixel unit output electrodes are respectively and electrically connected with the 16 MOS transistors, and the fixed level value on;

in the 1 st latch, a1 st-NMOS gate and a 4 th-NMOS gate are connected with an addressing line, a1 st-NMOS drain is connected with a positive phase line, a 4 th-NMOS drain is connected with a negative phase line, a1 st-NMOS source, a2 nd-NMOS gate, a2 nd-PMOS gate, a 3 rd-NMOS drain and a 3 rd-PMOS drain are connected with a1 st connecting line, a 4 th-NMOS source, a 3 rd-NMOS gate, a 3 rd-PMOS gate, a2 nd-NMOS drain and a2 nd-PMOS drain are connected with a2 nd connecting line, a2 nd-PMOS source and a 3 rd-PMOS source are connected with a digital power line, and a2 nd-NMOS source and a 3 rd-NMOS source are connected with a digital ground line; in the 2 nd latch, the 8 th-NMOS gate is connected with the output control line, the 8 th-NMOS drain is connected with the 2 nd connecting line, the 9 th-NMOS gate is connected with the reset control line, the 9 th-NMOS drain is connected with the Vcom synchronous signal line, the 8 th-NMOS source, the 6 th-NMOS gate, the 6 th-PMOS gate, the 7 th-NMOS drain and the 7 th-PMOS drain are connected with the 3 rd connecting line, and the 9 th-NMOS source, the 7 th-NMOS gate, the 7 th-PMOS gate, the 6 th-NMOS drain and the 6 th-PMOS drain are connected with the 4 th connecting line; in the level inversion gate, the 5 th-PMOS gate and the 5 th-NMOS gate are connected with an inversion control line, the 5 th-PMOS drain is connected with a 3 rd connecting line, the 5 th-NMOS drain is connected with a 4 th connecting line, and the 5 th-PMOS source and the 5 th-NMOS source are connected with a 5 th connecting line; in the level conversion gate, the 10 th-NMOS gate and the 10 th-PMOS gate are both connected with the 5 th connecting line, the 10 th-NMOS source is connected with the analog low level line, the 10 th-PMOS source is connected with the analog high level line, and the 10 th-NMOS drain and the 10 th-PMOS drain are both connected with the pixel unit output electrode.

2. The pixel circuit of digital 16-transistor silicon-based liquid crystal display chip of claim 1, wherein: the 1 st-NMOS tube, the 2 nd-PMOS tube, the 3 rd-NMOS tube, the 3 rd-PMOS tube, the 4 th-NMOS tube, the 5 th-PMOS tube, the 6 th-NMOS tube, the 6 th-PMOS tube, the 7 th-NMOS tube, the 7 th-PMOS tube, the 8 th-NMOS tube and the 9 th-NMOS tube adopt low-voltage MOS tube structures with working voltage not more than 2.0V, and the 10 th-PMOS tube and the 10 th-NMOS tube adopt high-voltage MOS tube structures with working voltage not less than 2.0V.

3. The method for driving the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip according to claim 1 or 2, wherein: in at least any two adjacent, front and rear signal periods of the pulse wave signal Vcom transmitted on the common electrode, the first step involves the 1 st latch: sampling a pair of inverted levels on the positive phase line and the negative line bit line in a previous signal period and storing the sampled inverted levels into a1 st latch; the second step involves the 2 nd latch, the level inversion gate, the level translation gate: the level stored by the 1 st latch is sampled and stored in the 2 nd latch in the first half signal period of the next signal period, and meanwhile, a pair of inverted electrical signal waveforms stored by the 2 nd latch are intercepted alternately by controlling a level inversion gate and synthesized into an electrical signal to be output to a level conversion gate; the third step involves the 2 nd latch, the level inversion gate, the level shift gate: and in the latter half signal period of the latter signal period, the level on the Vcom synchronous signal line is sampled and stored in the 2 nd latch, meanwhile, a pair of inverted electrical signal waveforms stored in the 2 nd latch are intercepted again by controlling the level inversion gate alternately and synthesized into an electrical signal to be output to the level conversion gate, and finally, the fixed low level on the analog low level line is controlled or selected to be output to the pixel unit output electrode, or the fixed high level on the analog high level line is selected to be output to the pixel unit output electrode, so that the purpose of alternately inputting the fixed level on the analog low level line and the fixed level on the analog high level line to the pixel unit output electrode is achieved.

4. The driving method of the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip as claimed in claim 3, further comprising: and simultaneously performing the second step and the third step in the next signal period, performing the first step operation on the 1 st latch, namely: the level on the data bit line is sampled and stored into the 1 st latch again, and the second step, the third step and the first step of operation in the 1 st latch are repeated respectively in the 2 nd latch, the level inversion gate and the level conversion gate in the signal period immediately following the signal period, and thus continuously performed, and corresponding to a plurality of continuous signal periods of the pulse wave signal Vcom transmitted on the common electrode, the electric signal is continuously output at the pixel unit output electrode.

5. The method for driving the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip according to claim 3, wherein: the waveform in the case where the frequency of the pulse wave signal Ssh transmitted on the output control line, the frequency of the pulse wave signal Sre transmitted on the reset control line, and the frequency of the pulse wave signal Svc transmitted on the Vcom synchronization signal line are the same as the frequency of the pulse wave signal Vcom transmitted on the common electrode has the following characteristics: the pulse wave signal Svc transmitted on the Vcom synchronization signal line is in reverse phase with the pulse wave signal Vcom transmitted on the common electrode, and the high level of the pulse wave signal Ssh transmitted on the output control line and the high level of the pulse wave signal Sre transmitted on the reset control line respectively appear in two adjacent half periods of the pulse wave signal Svc transmitted on the Vcom synchronization signal line and appear only once; firstly generating a high-level up-jumping edge Ssh _ upe of a pulse wave signal Ssh transmitted on an output control line, then generating a jumping edge Svc _ mde of a pulse wave signal Svc transmitted on a Vcom synchronous signal line after T23 time, and then generating a high-level up-jumping edge Sre _ upe of a pulse wave signal Sre transmitted on a reset control line after T24 time, wherein T23 and T24 time are the same; the total time that an arbitrary bit occupies the 2 nd latch, either high or low, is no more than the sum of the times T15, T16, T17, T18, where: the effective time of the 2 nd latch for latching the one-bit data, the high level or the low level is the sum of the time of T23 and T24, the sum of the time of T23 and T24 does not exceed the sum of the time of T15 and T16, T23 is regarded as the positive half field of the one-bit data and corresponds to the low level of the pulse wave signal Vcom transmitted on the common electrode, T24 is regarded as the negative half field of the one-bit data and corresponds to the high level of the pulse wave signal Vcom transmitted on the common electrode, and the sum of the rest of the time of T17 and T18 is the reset time.

6. The method for driving the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip according to claim 3, wherein: the pulse wave signal Ssh transmitted on the output control line is at a high level, and the pulse wave signal Sre transmitted on the reset control line is at a low level, and the 2 nd latch enters a state of inputting data from the 1 st latch; the pulse wave signal Ssh transmitted on the output control line and the pulse wave signal Sre transmitted on the reset control line are both low level, and the 2 nd latch enters a latch data state; the pulse wave signal Sre transmitted on the reset control line is at a high level, and the pulse wave signal Ssh transmitted on the output control line is at a low level, and the 2 nd latch enters a state where data is input from the Vcom synchronization signal line.

7. The method for driving the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip according to claim 3, wherein: the waveform in the case where the frequency and phase of the pulse wave signal Sc transmitted through the inversion control line are the same as those of the pulse wave signal Vcom transmitted through the common electrode has the following characteristics: the signal on the 3 rd connection line is the pulse wave signal laB2 transmitted on the 3 rd connection line, the signal on the 4 th connection line is the pulse wave signal la2 transmitted on the 4 th connection line, and when the signal Sc is a continuous square wave, the partial waveform of the pulse wave laB2 transmitted on the 3 rd connection line and the partial waveform of the pulse wave la2 transmitted on the 4 th connection line are alternately intercepted on the 5 th connection line and synthesized into the waveform of the pulse wave signal Vcpe transmitted on the 5 th connection line.

8. The method for driving the pixel circuit of the digital 16-transistor silicon-based liquid crystal display chip according to claim 3, wherein: a voltage difference between a fixed low level VL provided on the analog low level line and a low level V0 of the pulse wave signal transmitted on the common electrode must not exceed a threshold voltage of the driven liquid crystal material to form a zero electric field, and a voltage difference between a fixed high level VH provided on the analog high level line and a high level V1 of the pulse wave signal transmitted on the common electrode must not exceed a threshold voltage of the driven liquid crystal material to form a zero electric field, which is not positive or negative and is negligible in controlling physical characteristics of the liquid crystal material; a positive electric field is formed by the fixed high level VH provided on the analog high level line and the low level V0 of the pulse wave signal transmitted on the common electrode, and a negative electric field is formed by the fixed low level VL provided on the analog low level line and the high level V1 of the pulse wave signal transmitted on the common electrode; the pulse wave signal Vpe transmitted on the pixel unit output electrode, which is finally generated after the 2 nd latch application scenario, the level inversion gate application scenario and the level conversion gate application scenario are adopted in sequence, has the following characteristics: in at least any two adjacent, preceding and succeeding signal periods of the pulse wave signal Vcom transmitted on the common electrode, and after the pulse wave signal Vcom is input to the 1 st latch through the positive phase line and held at the low level in the preceding signal period and is synchronously input to the 1 st latch through the negative phase line and held at the high level, a waveform having an alternating current driving action exists on the pulse wave signal Vpe transmitted on the pixel unit output electrode generated in the succeeding signal period, the waveform generates a pair of adjacent positive and negative fields with respect to the adjacent low and high levels in one period of the pulse wave signal Vcom transmitted on the common electrode, the adjacent positive and negative fields constitute a pair of adjacent positive and negative fields that exert a significant control action on the physical properties of the liquid crystal material, or in at least any two adjacent, preceding and succeeding signal periods of the pulse wave signal Vcom transmitted on the common electrode, and the positive phase line is input to the 1 st latch through the positive phase line and held at the high level in the preceding signal period, And after the synchronous input and low level keeping of the 1 st latch through the negative phase line, there is a corresponding waveform on the pulse wave signal Vpe transmitted on the pixel unit output electrode generated in the next signal period, the corresponding waveform generates a pair of adjacent zero electric fields with respect to the adjacent low level and high level in one period of the pulse wave signal Vcom transmitted on the common electrode, and the adjacent zero electric fields form a waveform without obvious control effect on the physical properties of the liquid crystal material.