CN111428196A - Non-monotonic function approximate calculation device based on random calculation - Google Patents

Non-monotonic function approximate calculation device based on random calculation Download PDF

Info

Publication number
CN111428196A
CN111428196A CN202010234283.1A CN202010234283A CN111428196A CN 111428196 A CN111428196 A CN 111428196A CN 202010234283 A CN202010234283 A CN 202010234283A CN 111428196 A CN111428196 A CN 111428196A
Authority
CN
China
Prior art keywords
bit stream
unit
random bit
random
special value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010234283.1A
Other languages
Chinese (zh)
Inventor
潘红兵
董虹希
秦子迪
邱禹欧
郑沐晗
王宇宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University
Original Assignee
Nanjing University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University filed Critical Nanjing University
Priority to CN202010234283.1A priority Critical patent/CN111428196A/en
Publication of CN111428196A publication Critical patent/CN111428196A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention discloses a non-monotonic function approximate calculation device based on random calculation, which comprises an input shift unit, a special value generation unit, a random bit stream generation unit, an inversion selection unit, a logic operation unit and a counter unit. The input shifting unit takes out high m bits of an input independent variable x as the input of a special value generating unit, the special value generating unit obtains a special value required by a device through combinational logic mapping, a random bit stream generating unit converts the special value into a random bit stream, a logic operation unit performs bitwise logic operation on the random bit stream and outputs a corresponding result bit stream, and a counter unit counts the number of '1' in the result bit stream to obtain an output result. The device can realize approximate calculation of a non-monotonic function based on a random calculation principle, and greatly reduces the power consumption and the area overhead of a hardware framework while keeping higher precision.

Description

Non-monotonic function approximate calculation device based on random calculation
Technical Field
The invention relates to the field of design of very large scale integrated circuits, in particular to a hardware device for calculating a non-monotonic function with low power consumption and high precision.
Background
Non-monotonic functions are widely used in digital signal processing field as a common function, such as sin (pi x)/pi, sin (2 pi x) and other sine functions. A sinusoidal signal is a common signal source with the most unique frequency component, and any complex signal (e.g., a sound signal) can be decomposed into a superposition of a plurality of sinusoidal signals with different frequencies and different amplitudes through fourier transform. For example, the Fourier series component of a signal may be expressed as ansin(n2πfx)、bncos (n2 π fx), where n denotes the nth harmonic, an、bnThe coefficients representing the nth harmonic, f representing the frequency, and x being time, are arguments. Due to the real-time requirement of hardware implementation, approximation calculation is often performed when complex functions are generated in an actual system. The sinusoidal signal generator may use an approximation calculation to obtain the desired sinusoidal signal.
The methods for approximating the computation function mainly include an iterative method, a polynomial expansion method, and a piecewise linear approximation method. The iteration method represented by a Newton iteration method and a coordinate rotation digital computation method (CORDIC) needs to carry out repeated iteration calculation, and has long calculation time and high consumption of hardware resources; the polynomial expansion method increases proportionally with the increase of expansion order, and the multiplication and addition units required by a hardware circuit also increase proportionally; the piecewise linear approximation method divides the input range into a plurality of parts, each part is approximated by a line segment, only one multiply-add unit is needed, and the circuit delay is low.
The general piecewise linear approximation needs to use a lookup table to store the slope and endpoint values of the segment, and needs a multiplier and an adder to perform multiply-add operation, which occupies a large area in hardware implementation. Random computation represents a number by simple circuitry as a string of random bit streams, the size of the number being represented by the ratio of the number of 1's in the string in the bit stream. The representation method can convert the multiplication and addition operation into simple logic gate operation, and greatly reduces the hardware expense. Combining random computations with piecewise linear approximations can effectively reduce the power consumption and area of hardware circuits.
Disclosure of Invention
The invention aims to provide a non-monotonic function approximate calculation device based on random calculation, which realizes the purposes of high calculation precision, simple calculation logic, less power consumption and smaller area.
The technical scheme of the invention is as follows:
a non-monotonic function approximate calculation device based on random calculation comprises an input shift unit, a special value generation unit, a random bit stream generation unit, an inversion selection unit, a logic operation unit and a counter unit; the input shift unit is used for extracting the high m bits of the argument x as the index p ═ p of the special value generation unitmpm-1…p1(binary 0 or 1) while retaining the low (10-m) bits of the argument x as the fractional part q ═ q10-mq9-m…q1(binary 0 or 1) where the argument x takes a value in the range of [0,1), expressed as a 10-bit binary number, and the number of shifts m determines the number of uniform segments 2 of the function in the input rangemThe more the number of segments, the higher the approximation accuracy; the special value generating unit is used for generating a function value F and a special item of the segmentation end point
Figure BDA0002430444500000021
And a selection signal Sel for obtaining a function value F and a special item through combinational logic mapping according to the index p generated by the input shift unit
Figure BDA0002430444500000022
Setting a selection signal Sel according to the property of the objective function; the random bit stream generating unit is used for generating a function value F and a special item
Figure BDA0002430444500000023
The fractional part q is converted into a random bit stream F _ b,
Figure BDA0002430444500000024
q _ b; the negation selection unit is used for selecting whether to negate the random bit stream Q _ b according to a selection signal Sel and outputting a bit stream Q _ b; the logic operation unitFor random bit stream
Figure BDA0002430444500000025
And Q _ b is subjected to bitwise NAND operation to obtain representation
Figure BDA0002430444500000026
And then represent the random bit stream
Figure BDA0002430444500000027
Performing bitwise AND operation on the random bit stream F _ b and the random bit stream F _ b to obtain a random bit stream o _ b representing y; and the counter unit is used for counting the number of '1' in the bit stream o _ b output by the logic operation unit to obtain a binary representation of the output value y.
Further, when the argument x is in an increasing section, the special value generation unit obtains a function value F ═ F ((n +1) k) and a special term by a combinational logic mapping
Figure BDA0002430444500000028
When the independent variable x is in a subtraction interval, the special value generating unit obtains a special value F (F) (nk) and a special item through combinational logic mapping
Figure BDA0002430444500000029
Wherein k is 1/2mIn order to be at the interval of the segments,
Figure BDA00024304445000000210
for the number of segments where x is input, n ═ pm*2m-1+pm-1*2m-2+…+p1*20。
Further, the negation selection unit performs a selection operation according to a selection signal Sel: if the selection signal Sel is 0, it indicates that the argument x is in an increasing interval, and the random bit stream q _ b is inverted, and if the selection signal Sel is 1, it indicates that the argument x is in a decreasing interval, and the inversion operation is not performed.
The device of the invention simply transforms the approximate formulas of the non-monotonic functions in different monotonic intervals, and uses the combinational logic mapping and random calculation, thereby avoiding the consumption of a large amount of lookup tables, multipliers and common adder resources, so that the hardware has smaller occupied area and lower power consumption under the condition of keeping the precision of the quasi-summation calculation result to be more ideal, can better accord with the hardware design trend of the current digital signal processing, and is more suitable for application scenes such as embedded equipment with high real-time performance.
Drawings
FIG. 1 is an architectural diagram of the device of the present invention.
Fig. 2 is a schematic diagram of a specific structure of the random bit stream generation unit.
Fig. 3 is a schematic diagram of the structure of a linear feedback shift register.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
This example is illustrated by taking sin (π x)/π function as an example, and approximating sin (π x)/π function using the following formula:
Figure BDA0002430444500000031
where x is a function argument, x ∈ [0,1), represented by a 10-bit binary number, k 1/2mFor the segmentation step size, m is a positive integer smaller than 10, and in the following embodiments, m is illustrated as 3;
Figure BDA0002430444500000032
for the number of segments of the input x, the value of n is obtained by shifting the argument, and the input argument x is shifted to the left by three bits to obtain the three higher bits p ═ p3p2p1,n＝p3*22+p2*21+p1*20。
The derivation process of formula (1) is as follows, and can be obtained from the formula of the first-order Taylor series expansion
f(x)＝f(x0)+f′(x0)*Δx，Δx＝x-x0(2)
When the argument x is in the monotonically increasing interval [0,0.5), (2) may be transformed as follows:
Figure BDA0002430444500000033
when the argument x is in the monotonically decreasing interval [0.5,1), (2) can be transformed as follows:
Figure BDA0002430444500000034
for equation (3), F ═ F ((n +1) k) is defined,
Figure BDA0002430444500000035
since f (x) is an increasing function in the interval [0,0.5),
Figure BDA0002430444500000036
defining fractional part
Figure BDA0002430444500000037
Q is more than 0 and less than 1, then
Figure BDA0002430444500000038
For equation (4), F ═ F (nk) is defined,
Figure BDA0002430444500000039
since f (x) is a decreasing function in the interval [0.5,1),
Figure BDA00024304445000000310
defining fractional part
Figure BDA00024304445000000311
Figure BDA00024304445000000311
0＜q＜1。
In the apparatus for approximate calculation of sin (pi x)/pi function of this embodiment, the input x has a value range of [0,1 ], and the output function result has a value range of [0,1 ]. The overall hardware architecture diagram is shown in fig. 1, and mainly includes six units working in the following order: input shift unit, special value generation unit, random bit stream generation unit, and fetch unitThe device comprises an inverse selection unit, a logic operation unit and a counter unit. The input shifting unit is used for extracting the number n of the sections where the independent variable x is located and acquiring the decimal part q, and the unit is realized by shifting operation. A special value generation unit for generating F sum according to the value of the fractional number n
Figure BDA0002430444500000041
And select signal Sel, the unit is implemented by a combinational logic map whose circuits appear as a series of and, or, and not gates. The random bit stream generation unit is used for generating a random bit stream according to the input F,
Figure BDA0002430444500000042
q-value conversion into a corresponding random bit stream Fb,
Figure BDA0002430444500000043
q _ b, the unit comprising a linear feedback shift register and a comparator. The negation selection unit is used for selecting whether to carry out bitwise negation on the output value q _ b of the random bit stream generation unit according to a selection signal Sel, carrying out negation operation when Sel is 0, and not carrying out negation operation when Sel is 1, and comprises an inverter and a multiplexer. The logic operation unit is used for calculating
Figure BDA0002430444500000044
And outputs to a counter unit, which consists of a nand gate and an and gate. The counter unit is used for counting the number of 1 in the bit stream output by the logic operation unit and outputting the number as a calculation result. The function and the specific implementation process of each unit are explained in detail as follows:
as shown in fig. 1, the input x in this embodiment is a fixed-point number of 10 bits, and since the value range of the input x is 0 to 1, the input only includes a decimal number of 10 bits. Firstly, in an input shifting unit, an input x is shifted to the left by three bits to obtain three high bits p ═ p3p2p1And lower seven positions q ═ q7q6q5q4q3q2q1(ii) a p is output to specialThe value generating unit is used as the input of the combinational logic mapping, and seven bits q and three bits 0 are spliced to obtain {000q7q6q5q4q3q2q1Directly output to the random bit stream generation unit. The special value generating unit carries out the carnot diagram simplification through a truth table between p and each bit of the special value needing mapping, in the embodiment, p is 3 bits, the segment number n has eight cases of 0,1,2,3, 4,5,6 and 7, when n is 0,1,2 and 3, the current input is in a monotone increasing interval, and the special value F is F ((n +1) k) and
Figure BDA0002430444500000045
the values of are approximately:
Figure BDA0002430444500000046
when n is 4,5,6,7, it indicates that the current input is in a monotonically decreasing interval, and the special values F, (nk) and
Figure BDA0002430444500000047
Figure BDA0002430444500000051
the values of are approximately:
Figure BDA0002430444500000052
from the above F and
Figure BDA0002430444500000053
can be seen in F sum in monotonically increasing and decreasing intervals
Figure BDA0002430444500000054
The values are symmetrical, i.e. n-0 and n-7, n-1 and n-6, n-2 and n-5, n-3 and n-4, F and
Figure BDA0002430444500000055
equal value due toHerein, in the passing of p3p2p1Mapping F and
Figure BDA0002430444500000056
when each bit is in the group, the symmetric characteristic can be used to save logic resources, and the specific mapping scheme is as follows:
first, p input to a special value generation unit is judged3p2p1P in (1)3If p is3When p is equal to 0, p is directly used2p1Performing combinational logic mapping if p3When 1, then p is2p1Inverting and then performing combinational logic mapping, F [ -i [ ]]And
Figure BDA0002430444500000057
denotes F and
Figure BDA0002430444500000058
the ith fraction bit, p, of the approximationiTo index the ith bit of p, the list of combinatorial logical mappings is as follows:
Figure BDA0002430444500000059
Figure BDA00024304445000000510
Figure BDA0002430444500000061
obtaining F of 10bit and F of 10bit after the above-mentioned combinational logic mapping
Figure BDA0002430444500000062
The value, the right column of the table, is the logical expression of the circuit. From the above analysis, it can be seen that the function sin (π x)/π in this embodiment is an increasing function over the interval [0,0.5) and a decreasing function over the interval [0.5,1), and therefore the expression of the selection signal Sel is
Figure BDA0002430444500000063
Appearing as a not gate in the circuit.
The random bit stream generation unit receives the fractional part q of 10 bits from the input shift unit, and receives F of 10 bits and F of 10 bits from the special value generation unit
Figure BDA0002430444500000064
The random number generator comprises a linear feedback shift register L FSR and a comparator, the random number generator generates 1-bit output in each clock cycle, the specific structure is shown in FIG. 2, X9, X8, …, X0 in the input register represents 10-bit binary representation of the device input argument X, L9, L08, …, L0 represents 10 registers in L FSR, the operation principle of L FSR is shown in FIG. 3, L FSR has 1024 different states in 1024 clock cycles by designing the feedback signal in the diagram, namely, pseudo-random states are generated, three L FSRs need to have independent initial states to ensure the independence of three random bit streams, therefore, in the diagram of FIG. 1, L FSR1, L FSR2, L FSR3 represents three independent linear feedback shift registers to generate random bit stream of random bit stream
Figure BDA0002430444500000065
q-value conversion into a corresponding random bit stream F _ b with length of 1024 bits,
Figure BDA0002430444500000066
q_b。
As can be seen from the derivation of equation (3), when the argument x is in the monotonically increasing interval, an operation of 1 needs to be performed on the fractional part q, and according to the principle of random computation, the operation is performed by inverting the random bit stream q _ b, so that the output q _ b of the random bit stream generation unit first passes through an inversion selection unit. The negation selection unit comprises an inverter and a multiplexer, and the working principle of the unit is that whether the input random bit stream Q _ b is negated or not is judged according to a selection signal Sel, when Sel is 0, the argument x is located in a monotonically increasing interval and needs to be negated, and when Sel is 1, the argument x is not negated, so that the output Q _ b is obtained.
The logic operation unit receives the output F _ b of the random bit stream generation unit,
Figure BDA0002430444500000067
And the output Q _ b of the inverting selection unit and using the principle of random calculation
Figure BDA0002430444500000068
The calculation is converted into a NAND gate and an AND gate, wherein the NAND gate is used for realizing
Figure BDA0002430444500000071
And gates for implementing
Figure BDA0002430444500000072
And outputs a bit stream o b to the counter unit.
The counter unit obtains a final function output result by counting the number of '1' in the bit stream o _ b, the final output is represented by a binary number of 10 bits, and the default decimal point is before the highest bit, namely the output range is in the interval of [0,1 ].
The embodiment only takes sin (pi x)/pi as an example, and the method can be used for generating other non-monotonic functions and can be used for a signal generator.
The foregoing is only a preferred embodiment of this invention and it should be noted that modifications can be made by those skilled in the art without departing from the principle of the invention and these modifications should also be considered as the protection scope of the invention.

Claims (4)

1. A non-monotonic function approximate calculation device based on random calculation is characterized by comprising an input shift unit, a special value generation unit, a random bit stream generation unit, an inversion selection unit, a logic operation unit and a counter unit;
the input shifting unit is used for extracting high m bits of an independent variable x as an index p of the special value generating unit, and simultaneously keeping low (10-m) bits of the independent variable x as a decimal part q, wherein the value range of the independent variable x is [0,1 ];
the special value generating unit is used for generating a function value F and a special item of the segmentation end point
Figure FDA0002430444490000011
And a selection signal Sel;
the random bit stream generating unit is used for generating a function value F and a special item
Figure FDA0002430444490000012
The fractional part q is converted into a random bit stream F _ b,
Figure FDA0002430444490000013
q_b；
The negation selection unit is used for selecting whether to negate the random bit stream Q _ b according to a selection signal Sel and outputting a bit stream Q _ b;
the logic operation unit is used for random bit stream
Figure FDA0002430444490000014
And Q _ b is subjected to bitwise NAND operation to obtain representation
Figure FDA0002430444490000015
And then represent the random bit stream
Figure FDA0002430444490000016
Performing bitwise AND operation on the random bit stream F _ b and the random bit stream F _ b to obtain a random bit stream o _ b representing y;
and the counter unit is used for counting the number of '1' in the bit stream o _ b output by the logic operation unit to obtain a binary representation of the output value y.
2. The non-monotonic function approximation calculation apparatus based on random calculation as claimed in claim 1,when the argument x is in an increasing section, the special value generation unit obtains a function value F ═ F ((n +1) k) and a special term by a combinational logic mapping
Figure FDA0002430444490000017
When the independent variable x is in a subtraction interval, the special value generating unit obtains a special value F (F) (nk) and a special item through combinational logic mapping
Figure FDA0002430444490000018
Wherein k is 1/2mIn order to be at the interval of the segments,
Figure FDA0002430444490000019
is the number of segments where input x is located.
3. The apparatus according to claim 1, wherein the negation selection unit performs a selection operation according to a selection signal Sel: if the selection signal Sel is 0, it indicates that the argument x is in an increasing interval, and the random bit stream q _ b is inverted, and if the selection signal Sel is 1, it indicates that the argument x is in a decreasing interval, and the inversion operation is not performed.
4. The apparatus of claim 1, wherein the random bit stream generator comprises a linear feedback shift register and a comparator.
CN202010234283.1A 2020-03-30 2020-03-30 Non-monotonic function approximate calculation device based on random calculation Pending CN111428196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010234283.1A CN111428196A (en) 2020-03-30 2020-03-30 Non-monotonic function approximate calculation device based on random calculation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010234283.1A CN111428196A (en) 2020-03-30 2020-03-30 Non-monotonic function approximate calculation device based on random calculation

Publications (1)

Publication Number Publication Date
CN111428196A true CN111428196A (en) 2020-07-17

Family

ID=71549108

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010234283.1A Pending CN111428196A (en) 2020-03-30 2020-03-30 Non-monotonic function approximate calculation device based on random calculation

Country Status (1)

Country Link
CN (1) CN111428196A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113792511A (en) * 2021-09-03 2021-12-14 上海交通大学 Single-variable random circuit with high calculation accuracy and low hardware overhead and configuration method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110705196A (en) * 2019-09-25 2020-01-17 电子科技大学 Error-free adder based on random calculation
CN110837624A (en) * 2019-11-13 2020-02-25 南京大学 Approximate calculation device for sigmoid function
CN110879697A (en) * 2019-10-29 2020-03-13 南京大学 Device for approximately calculating tanh function

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110705196A (en) * 2019-09-25 2020-01-17 电子科技大学 Error-free adder based on random calculation
CN110879697A (en) * 2019-10-29 2020-03-13 南京大学 Device for approximately calculating tanh function
CN110837624A (en) * 2019-11-13 2020-02-25 南京大学 Approximate calculation device for sigmoid function

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZIDI QIN 等: "A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing", 《IEEE ACCESS》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113792511A (en) * 2021-09-03 2021-12-14 上海交通大学 Single-variable random circuit with high calculation accuracy and low hardware overhead and configuration method thereof
CN113792511B (en) * 2021-09-03 2023-11-03 上海交通大学 Single-variable random circuit with high calculation accuracy and low hardware cost and configuration method thereof

Similar Documents

Publication Publication Date Title
Saokar et al. High speed signed multiplier for digital signal processing applications
Volkova et al. Towards hardware IIR filters computing just right: Direct form I case study
Reddy et al. Design of approximate booth squarer for error-tolerant computing
Julio et al. Energy-efficient Gaussian filter for image processing using approximate adder circuits
Ashrafi et al. A direct digital frequency synthesizer based on the quasi-linear interpolation method
Gadda et al. 64-bit ALU design using vedic mathematics
JP2005174077A (en) Function operation method and circuit
CN115658008A (en) Resource multiplexing type transcendental function operation implementation method
CN111428196A (en) Non-monotonic function approximate calculation device based on random calculation
Chandra A novel method for scalable VLSI implementation of hyperbolic tangent function
Brisebarre et al. A lattice basis reduction approach for the design of finite wordlength FIR filters
Bellal et al. Improved affine arithmetic-based precision analysis for polynomial function evaluation
Lee et al. Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation
Daud et al. Hybrid modified booth encoded algorithm-carry save adder fast multiplier
Ma et al. A 2 n scaling scheme for signed RNS integers and its VLSI implementation
He et al. A probabilistic prediction based fixed-width booth multiplier
CN111428195A (en) Subtraction function approximate calculation device based on random calculation
Nagayama et al. Compact numerical function generators based on quadratic approximation: Architecture and synthesis method
Nagayama et al. Design method for numerical function generators based on polynomial approximation for FPGA implementation
Wazurkar et al. Globally asynchronous locally synchronous (GALS) pipelined signed multiplier
Zhang et al. Implementation of high accuracy trigonometric function on FPGA by Taylor expansion
Indhumaraghathavalli et al. Digital Signal Processing Applications using Multiplier Technique in Fixed Point Arithmetic
Dhobi et al. Fpga implementation of fir filter using various algorithms: a retrospective
Khan et al. Modulo Ling Adder for high speed DA-RNS system
Krstić et al. BINARY TO RNS ENCODER FOR THE MODULI SET {2n− 1, 2n, 2n+ 1} WITH EMBEDDED DIMINISHED-1 CHANNEL FOR DSP APPLICATION

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200717

RJ01 Rejection of invention patent application after publication