CN111418067A - Image sensor, method for manufacturing image sensor, and pixel circuit - Google Patents
Image sensor, method for manufacturing image sensor, and pixel circuit Download PDFInfo
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Abstract
An image sensor (200), a method of manufacturing an image sensor (200) and a pixel circuit. The image sensor (200) includes: a plurality of pixel units (210); wherein the circuitry of each pixel cell (210) is disposed on a plurality of wafers (221,222), the circuitry of each pixel cell (210) being electrically connected between the plurality of wafers (221, 222).
Description
Copyright declaration
The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.
The present application relates to the field of image sensors, and more particularly, to an image sensor, a method of manufacturing the image sensor, and a pixel circuit.
A Cmos Image Sensor (CIS) is widely used in the fields of consumer electronics, security monitoring, industrial automation, artificial intelligence, internet of things, etc., for collecting and sorting image data information, and providing an information source for subsequent processing and application.
The CIS may be classified into a rolling shutter image sensor (RS-CIS) and a global shutter image sensor (GS-CIS) according to an exposure and corresponding readout mode. In the design of the CIS, the voltage dominated GS-CIS is a mainstream solution. However, the current GS-CIS has a complex structure, on one hand, the area of a unit pixel is large, and on the other hand, a large number of transistors/capacitors occupy more pixel area, which affects the fill factor (fillfactor), the photosensitive efficiency and the number of electrons in a full well, thereby affecting the performance of the image sensor.
Therefore, how to improve the performance of the image sensor becomes a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the application provides an image sensor, a method for preparing the image sensor and a pixel circuit, which can improve the performance of the image sensor.
In a first aspect, an image sensor is provided, including: a plurality of pixel units; the circuit of each pixel unit is arranged on a plurality of wafers, and the circuit of each pixel unit is electrically connected among the wafers.
In a second aspect, there is provided a method of manufacturing an image sensor, comprising: preparing a first circuit of each pixel unit in a plurality of pixel units of an image sensor on a first wafer; preparing a second circuit of each pixel unit on a second wafer; electrically connecting the first and second circuits between the first and second wafers.
In a third aspect, a pixel circuit of an image sensor is provided, including: the device comprises a photodiode, a transmission tube, a reset tube, a first source follower, a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube; the grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube; the source electrode of the first source follower is connected to the drain electrode of the bias tube; the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube; the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube; the source of the second source follower is connected to the row strobe pipe.
According to the technical scheme, the circuits of the pixel units are arranged on the wafers, the pixel circuits are connected through the electric connection among the wafers, on one hand, the area of the pixels can be reduced, on the other hand, the photodiodes can occupy the pixel area in a large proportion, the filling factor, the photosensitive efficiency and the number of full-well electrons are improved, and therefore the performance of the image sensor can be improved.
Fig. 1 is a schematic diagram of a pixel circuit of an image sensor according to an embodiment of the present application.
Fig. 2 is a schematic diagram of an image sensor according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a pixel circuit of an image sensor according to another embodiment of the present application.
Fig. 4 is a timing diagram of the pixel circuit in fig. 3.
Fig. 5 to 8 are schematic diagrams of the arrangement of the pixel circuit of the image sensor according to the embodiment of the present application.
Fig. 9 is a schematic flow chart of a method of manufacturing an image sensor according to an embodiment of the present application.
Fig. 10 to 13 are schematic views of a manufacturing process of an image sensor according to an embodiment of the present application.
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.
It should be understood that the specific examples are provided herein only to assist those skilled in the art in better understanding the embodiments of the present application and are not intended to limit the scope of the embodiments of the present application.
It should also be understood that, in the various embodiments of the present application, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the inherent logic of the processes, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It should also be understood that the various embodiments described in this specification can be implemented individually or in combination, and the examples in this application are not limited thereto.
The technical solution of the embodiment of the present application may be applied to various image sensors, for example, a global shutter image sensor, but the embodiment of the present application is not limited thereto.
Fig. 1 shows a schematic diagram of a pixel circuit 100 of a global shutter image sensor. As shown in fig. 1, the pixel circuit 100 includes eight transistors, a photodiode for sensing light, and two capacitors. The area of the pixel is large due to the fact that the number of devices is large, and a large number of transistors/capacitors occupy a large area of the pixel, so that the filling factor, the photosensitive efficiency and the number of full-well electrons are influenced, and the performance of the image sensor is influenced.
In view of this, embodiments of the present application provide an improved image sensor design scheme to improve the performance of an image sensor.
Fig. 2 shows a schematic diagram of an image sensor 200 according to an embodiment of the present application.
As shown in fig. 2, the image sensor 200 includes a plurality of pixel units 210 (two are shown in fig. 2), wherein the circuits of each pixel unit 210 are disposed on a plurality of wafers (two are shown in fig. 2, i.e., a first wafer 221 and a second wafer 222) between which the circuits of each pixel unit 210 are electrically connected.
In the embodiment of the present application, the circuits of the pixel unit 210 are disposed on a plurality of wafers, and the electrical connection between the plurality of wafers is used to realize a complete pixel circuit. By the arrangement mode, the area of the pixel is reduced, and the photodiode can occupy a larger proportion of the area of the pixel, so that the performance of the image sensor can be improved.
Alternatively, the electrical connection may be an intermetallic bond connection.
For example, as shown in fig. 2, inter-metal bonding is performed between the first wafer 221 and the second wafer 222 by using the bonding electrodes 231 and 232, so that the circuit of the pixel unit 210 is electrically connected between the first wafer 221 and the second wafer 222.
It should be understood that the electrical connection may be other electrical connection manners as long as the electrical connection between the wafers can be achieved, and the embodiment of the present application is not limited thereto.
The plurality of wafers may be arranged in a stacked configuration, i.e., the plurality of wafers are vertically stacked, such as the stacked configuration shown in fig. 2.
Optionally, as shown in fig. 2, in a two-wafer design, the circuit of each pixel unit 210 includes a first circuit and a second circuit, the first circuit is disposed on the first wafer 221, the second circuit is disposed on the second wafer 222, and the first circuit and the second circuit are electrically connected between the first wafer 221 and the second wafer 222.
Optionally, as shown in fig. 2, the first circuit includes a photodiode 211. Fewer devices other than the photodiode 211 may be provided in the first circuit so that the photodiode occupies a larger proportion of the pixel area.
In the embodiment of the present application, various pixel circuits may be used for the pixel unit 210, and the embodiment of the present application is not limited thereto. The following describes the arrangement of the circuit of the pixel unit 210 by taking the design of two wafers as an example, but the invention should not be construed as being limited to the embodiment of the present application.
FIG. 3 shows a schematic diagram of a pixel circuit 300 of an image sensor according to one embodiment of the present application. The pixel circuit 300 may be the circuit of the pixel cell 210 in fig. 2.
As shown in fig. 3, the pixel circuit 300 may include: the circuit comprises a photodiode 301, a transmission tube 302, a reset tube 303, a first source follower 304, a bias tube 305, a first switch tube 306, a second switch tube 307, a third switch tube 308, a fourth switch tube 309, a signal capacitor 310, a reference capacitor 311, a second source follower 312 and a row gate tube 313.
The transmission tube 302, the reset tube 303, the first source follower 304, the bias tube 305, the first switching tube 306, the second switching tube 307, the third switching tube 308, the fourth switching tube 309, the second source follower 312 and the row gate tube 313 may be N-type semiconductor transmission tubes (nMOS transistors).
The gate of the first source follower 304 is connected to the photodiode 301 through the pass transistor 302, and is connected to a power supply VDD1 through the reset transistor 303. The source of the first source follower 304 is connected to the drain of the bias tube 305. The drain of the first source follower 304 is connected to a power supply VDD 1. The drain of the bias transistor 305 is connected to the reference capacitor 311 through the first switch transistor 306, and is connected to the signal capacitor 310 through the third switch transistor 308. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch tube 307, and is connected to the signal capacitor 310 through the fourth switch tube 309. The source of the second source follower 312 is connected to the row strobe 313. The drain of the second source follower 312 is connected to a power supply VDD 2.
The timing diagram of the pixel circuit 300 is shown in fig. 4. The voltages in fig. 4 are control voltages applied to the gates of the respective transistors. When exposure is about to be cut off, the bias tube 305 is opened and works in a saturation region, then the reset tube 303 is closed, the first switch tube 306 is opened, and reference voltage Vref is stored in the reference capacitor 311; then the first switch 306 is closed, then the transmission tube 302 is opened, the photodiode 301 injects electrons into the gate of the first source follower 304, the voltage drops, then the transmission tube 302 is closed, the third switch 308 is opened, the signal voltage Vsig is stored in the signal capacitor 310, and then the third switch 308 is closed. Thus, the reference voltage and the signal voltage of each pixel are already stored in the respective reference capacitor and signal capacitor at this time, and then only the reference voltage and the signal voltage of each row need to be read out row by row. Specifically, the second switch tube 307 is opened first, the reference voltage Vref is output through the source end of the second source follower 312, the second switch tube 307 is closed, the fourth switch tube 309 is opened, at this time, the source end of the second source follower 312 has the signal voltage Vsig again, and Vref-Vsig is a signal corresponding to the incident light intensity.
The pixel circuit 300 may be disposed on and electrically connected between a plurality of wafers. The embodiments of the present application do not limit the distribution of the devices of the pixel circuit 300 on a plurality of wafers.
Optionally, in an embodiment of the present application, as shown in fig. 5, the pixel circuit 300 is disposed on two wafers, wherein a first circuit of the pixel circuit 300 includes a photodiode 301, a transfer transistor 302, a reset transistor 303 and a first source follower 304, and is disposed on the first wafer; the second circuit of the pixel circuit 300 includes a bias transistor 305, a first switch transistor 306, a second switch transistor 307, a third switch transistor 308, a fourth switch transistor 309, a signal capacitor 310, a reference capacitor 311, a second source follower 312, and a row gate transistor 313, and is disposed on a second wafer.
On the first wafer, the gate of the first source follower 304 is connected to the photodiode 301 through the pass transistor 302 and to the power supply VDD1 through the reset transistor 303. The drain of the first source follower 304 is connected to a power supply VDD 1.
On the second wafer, the drain of the bias transistor 305 is connected to the reference capacitor 311 through the first switch transistor 306, and is connected to the signal capacitor 310 through the third switch transistor 308. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch tube 307, and is connected to the signal capacitor 310 through the fourth switch tube 309. The source of the second source follower 312 is connected to the row strobe 313. The drain of the second source follower 312 is connected to a power supply VDD 2.
The source of the first source follower 304 and the drain of the bias tube 305 are electrically connected between the first wafer and the second wafer. For example, the source of the first source follower 304 and the drain of the bias tube 305 may be connected by an intermetallic bond.
In the above embodiment, the first source follower 304 and the bias tube 305 are connected by the first wafer and the second wafer. Other locations in the pixel circuit 300 may also be selected where the first wafer and the second wafer are connected.
Alternatively, in another embodiment of the present application, as shown in fig. 6, the first circuit of the pixel circuit 300 includes a photodiode 301, a transfer transistor 302, a reset transistor 303, a first source follower 304, and a bias transistor 305, which are disposed on the first wafer; the second circuit of the pixel circuit 300 includes a first switch tube 306, a second switch tube 307, a third switch tube 308, a fourth switch tube 309, a signal capacitor 310, a reference capacitor 311, a second source follower 312 and a row gate tube 313, which are disposed on a second wafer.
On the first wafer, the gate of the first source follower 304 is connected to the photodiode 301 through the pass transistor 302 and to the power supply VDD1 through the reset transistor 303. The drain of the first source follower 304 is connected to a power supply VDD 1. The source of the first source follower 304 is connected to the drain of the bias tube 305.
On the second wafer, the first switch tube 306 is connected to the reference capacitor 311, and the third switch tube 308 is connected to the signal capacitor 310. The gate of the second source follower 312 is connected to the reference capacitor 311 through the second switch tube 307, and is connected to the signal capacitor 310 through the fourth switch tube 309. The source of the second source follower 312 is connected to the row strobe 313. The drain of the second source follower 312 is connected to a power supply VDD 2.
The drain of the bias transistor 305 is electrically connected to the first switch transistor 306 and/or the third switch transistor 308 between the first wafer and the second wafer, so that the drain of the bias transistor 305 is connected to the reference capacitor 311 through the first switch transistor 306 and is connected to the signal capacitor 310 through the third switch transistor 308.
Alternatively, the circuit of the pixel unit 210 in fig. 2 may also employ the pixel circuit 100 shown in fig. 1.
As shown in fig. 1, the pixel circuit 100 includes: the circuit comprises a photodiode 101, a transmission tube 102, a reset tube 103, a first source follower 104, a bias tube 105, a first switch tube 106, a second switch tube 107, a first capacitor 108, a second capacitor 109, a second source follower 110 and a row gate tube 111.
Similarly, the transmission tube 102, the reset tube 103, the first source follower 104, the bias tube 105, the first switch tube 106, the second switch tube 107, the second source follower 110 and the row gate tube 111 may adopt N-type semiconductor transmission tubes.
The gate of the first source follower 104 is connected to the photodiode 101 through the pass transistor 102, and is connected to a power supply VDD1 through the reset transistor 103. The source of the first source follower 104 is connected to the drain of the bias tube 105. The drain of the first source follower 104 is connected to a power supply VDD 1. The drain of the bias tube 105 is connected to the first capacitor 108 through the first switch tube 106, and is connected to the second capacitor 109 and the gate of the second source follower 110 through the first switch tube 106 and the second switch tube 107. The source of the second source follower 110 is connected to the row strobe 111. The drain of the second source follower 110 is connected to a power supply VDD 2.
The working principle of the pixel circuit 100 is similar to that of the pixel circuit 300, except that the pixel circuit 100 only adopts two switching tubes, the first switching tube 106 and the second switching tube 107 are simultaneously opened to store the reference voltage Vref in the second capacitor 109, and the second switching tube 107 is closed to store the signal voltage Vsig in the first capacitor 108; in the signal readout phase, Vref is read out first, and then the second switch 107 is turned on to read out (Vref + Vsig)/2.
Alternatively, in an embodiment of the present application, as shown in fig. 7, the pixel circuit 100 is disposed on two wafers, wherein a first circuit of the pixel circuit 100 includes a photodiode 101, a transfer transistor 102, a reset transistor 103 and a first source follower 104, and is disposed on the first wafer; the second circuit of the pixel circuit 100 includes a bias transistor 105, a first switch 106, a second switch 107, a first capacitor 108, a second capacitor 109, a second source follower 110, and a row gate transistor 111, and is disposed on the second wafer.
On the first wafer, the gate of the first source follower 104 is connected to the photodiode 101 through the pass transistor 102, and is connected to the power supply VDD1 through the reset transistor 103. The drain of the first source follower 104 is connected to a power supply VDD 1.
On the second wafer, the drain of the bias transistor 105 is connected to the first capacitor 108 through the first switch transistor 106, and is connected to the second capacitor 109 and the gate of the second source follower 110 through the first switch transistor 106 and the second switch transistor 107. The source of the second source follower 110 is connected to the row strobe 111. The drain of the second source follower 110 is connected to a power supply VDD 2.
The source of the first source follower 104 and the drain of the bias tube 105 are electrically connected between the first wafer and the second wafer.
Alternatively, in another embodiment of the present application, as shown in fig. 8, the first circuit of the pixel circuit 100 includes a photodiode 101, a transmission transistor 102, a reset transistor 103, a first source follower 104, and a bias transistor 105, which are disposed on the first wafer; the second circuit of the pixel circuit 100 includes a first switch 106, a second switch 107, a first capacitor 108, a second capacitor 109, a second source follower 110, and a row gate 111, and is disposed on a second wafer.
On the first wafer, the gate of the first source follower 104 is connected to the photodiode 101 through the pass transistor 102, and is connected to the power supply VDD1 through the reset transistor 103. The source of the first source follower 104 is connected to the drain of the bias tube 105. The drain of the first source follower 104 is connected to a power supply VDD 1.
On the second wafer, the first switch 106 is connected to the first capacitor 108, and is connected to the second capacitor 109 and the gate of the second source follower 110 through the second switch 107. The source of the second source follower 110 is connected to the row strobe 111. The drain of the second source follower 110 is connected to a power supply VDD 2.
The drain of the bias transistor 105 and the first switch 107 are electrically connected between the first wafer and the second wafer, so that the drain of the bias transistor 105 is connected to the first capacitor 108 through the first switch 106, and is connected to the second capacitor 109 and the gate of the second source follower 110 through the first switch 106 and the second switch 107.
It should be understood that, besides the above description, the circuit of the pixel unit 210 may also adopt other pixel circuits, and in addition, the device distribution of the pixel circuits on a plurality of wafers may also adopt other subsections, which is not limited by the embodiment of the present application.
According to the technical scheme, the circuits of the pixel units are arranged on the wafers, the pixel circuits are connected through the electric connection among the wafers, on one hand, the area of the pixels can be reduced, on the other hand, the photodiodes can occupy the pixel area in a large proportion, the filling factor, the photosensitive efficiency and the number of full-well electrons are improved, and therefore the performance of the image sensor can be improved.
The image sensor and the pixel circuit thereof according to the embodiment of the present application are described above, and the manufacturing method thereof is described below. It should be understood that, for the sake of brevity, the description of the embodiments of the method described below may refer to the embodiments described above.
Fig. 9 shows a schematic flow diagram of a method 900 of preparing an image sensor of an embodiment of the application.
A first circuit for each of a plurality of pixel units of an image sensor is fabricated 910 on a first wafer.
The first circuit includes a photodiode and may include fewer other devices so that the photodiode occupies a larger proportion of the pixel area.
As shown in fig. 10, a photodiode 1001, and a small number of other devices, may be fabricated on a first wafer 1000, and provided with a bonding electrode 1002.
A second circuit for each pixel cell is fabricated 920 on a second wafer.
The second circuit includes devices other than the first circuit.
As shown in fig. 11, devices other than the first circuit may be prepared on the second wafer 1100, and a bonding electrode 1102 may be provided.
930 electrically connecting the first and second circuits between the first and second wafers.
Optionally, the first circuit and the second circuit may be connected between the first wafer and the second wafer by using an intermetallic bond.
As shown in fig. 12, a first wafer 1000 is bonded to a second wafer 1100, wherein for each pixel circuit, an inter-metal bond is made with bonding electrodes 1002 and 1102 to achieve a circuit connection between the two wafers.
Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower;
the second circuit comprises a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
The grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;
the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube;
the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;
a source electrode of the second source follower is connected to the row gate tube;
and electrically connecting the source electrode of the first source follower and the drain electrode of the bias tube between the first wafer and the second wafer.
Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission transistor, a reset transistor, a first source follower, and a bias transistor;
the second circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
The grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;
the source electrode of the first source follower is connected to the drain electrode of the bias tube;
the first switch tube is connected to the reference capacitor, and the third switch tube is connected to the signal capacitor;
the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;
a source electrode of the second source follower is connected to the row gate tube;
and electrically connecting the drain electrode of the bias tube and the first switching tube and/or the third switching tube between the first wafer and the second wafer, so that the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube.
Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission tube, a reset tube, and a first source follower;
the second circuit comprises a bias tube, a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
The grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;
the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube;
a source electrode of the second source follower is connected to the row gate tube;
and electrically connecting the source electrode of the first source follower and the drain electrode of the bias tube between the first wafer and the second wafer.
Optionally, in an embodiment of the present application, the first circuit includes a photodiode, a transmission transistor, a reset transistor, a first source follower, and a bias transistor;
the second circuit comprises a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
The grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;
the source electrode of the first source follower is connected to the drain electrode of the bias tube;
the first switch tube is connected to the first capacitor and is connected to the second capacitor and the grid electrode of the second source follower through the second switch tube;
a source electrode of the second source follower is connected to the row gate tube;
and electrically connecting the drain electrode of the bias tube and the first switch tube between the first wafer and the second wafer, so that the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube.
Optionally, after 930, the first wafer may be thinned so that the photodiode receives an optical signal.
As shown in fig. 13, after the first wafer 1000 and the second wafer 1100 are bonded, the first wafer 1000 is thinned so that the photodiode 1001 is on the surface of the pixel so as to receive the optical signal.
It should be understood that, although the above description is made by taking the design of two wafers as an example, the technical solution of the embodiments of the present application is not limited to the two wafers. For more than two wafers, the two wafer design described above may be used between each wafer.
It should also be understood that the technical solution of the embodiment of the present application is not limited to the global shutter image sensor, and other image sensors may also adopt the technical solution of the embodiment of the present application to reduce the pixel area and improve the performance of the image sensor.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on the understanding, the technical solution of the present application essentially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (30)
- An image sensor, comprising:a plurality of pixel units;the circuit of each pixel unit is arranged on a plurality of wafers, and the circuit of each pixel unit is electrically connected among the wafers.
- The image sensor of claim 1, wherein the plurality of wafers are arranged in a stack.
- The image sensor of claim 1 or 2, wherein the plurality of wafers comprises a first wafer and a second wafer, the circuitry of each pixel unit comprises a first circuit and a second circuit, the first circuit is disposed on the first wafer, the second circuit is disposed on the second wafer, and the first circuit and the second circuit are electrically connected between the first wafer and the second wafer.
- The image sensor of claim 3, wherein the first circuit comprises a photodiode.
- The image sensor of claim 3 or 4, wherein the first circuit comprises a photodiode, a transfer transistor, a reset transistor and a first source follower;the second circuit comprises a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
- The image sensor of claim 5, wherein the gate of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;the source electrode of the first source follower and the drain electrode of the bias tube are electrically connected between the first wafer and the second wafer;the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube;the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;the source of the second source follower is connected to the row strobe pipe.
- The image sensor of claim 3 or 4, wherein the first circuit comprises a photodiode, a transmission tube, a reset tube, a first source follower and a bias tube;the second circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
- The image sensor of claim 7, wherein the gate of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;the source electrode of the first source follower is connected to the drain electrode of the bias tube;the drain electrode of the bias tube is connected to the reference capacitor through the first switch tube and is connected to the signal capacitor through the third switch tube, wherein the drain electrode of the bias tube is electrically connected with the first switch tube and/or the third switch tube between the first wafer and the second wafer;the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;the source of the second source follower is connected to the row strobe pipe.
- The image sensor of claim 3 or 4, wherein the first circuit comprises a photodiode, a transfer transistor, a reset transistor and a first source follower;the second circuit comprises a bias tube, a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
- The image sensor of claim 9, wherein the gate of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;the source electrode of the first source follower and the drain electrode of the bias tube are electrically connected between the first wafer and the second wafer;the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube;the source of the second source follower is connected to the row strobe pipe.
- The image sensor of claim 3 or 4, wherein the first circuit comprises a photodiode, a transmission tube, a reset tube, a first source follower and a bias tube;the second circuit comprises a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
- The image sensor of claim 11, wherein the gate of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;the source electrode of the first source follower is connected to the drain electrode of the bias tube;the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube, wherein the drain electrode of the bias tube and the first switch tube are electrically connected between the first wafer and the second wafer;the source of the second source follower is connected to the row strobe pipe.
- The image sensor of any of claims 1-12, wherein the electrical connection comprises an intermetallic bond connection.
- A method of making an image sensor, comprising:preparing a first circuit of each pixel unit in a plurality of pixel units of an image sensor on a first wafer;preparing a second circuit of each pixel unit on a second wafer;electrically connecting the first and second circuits between the first and second wafers.
- The method of claim 14, wherein the first circuit comprises a photodiode.
- The method of claim 14 or 15, wherein the first circuit comprises a photodiode, a pass transistor, a reset transistor, and a first source follower;the second circuit comprises a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
- The method of claim 16, wherein the gate of the first source follower is connected to the photodiode through the transfer transistor and to a power supply through the reset transistor;the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube;the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;a source electrode of the second source follower is connected to the row gate tube;wherein said electrically connecting said first circuitry and said second circuitry between said first wafer and said second wafer comprises:and electrically connecting the source electrode of the first source follower and the drain electrode of the bias tube between the first wafer and the second wafer.
- The method of claim 14 or 15, wherein the first circuit comprises a photodiode, a pass transistor, a reset transistor, a first source follower, and a bias transistor;the second circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube.
- The method of claim 18, wherein the gate of the first source follower is connected to the photodiode through the transfer tube and to a power supply through the reset tube;the source electrode of the first source follower is connected to the drain electrode of the bias tube;the first switch tube is connected to the reference capacitor, and the third switch tube is connected to the signal capacitor;the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;a source electrode of the second source follower is connected to the row gate tube;wherein said electrically connecting said first circuitry and said second circuitry between said first wafer and said second wafer comprises:and electrically connecting the drain electrode of the bias tube and the first switch tube and/or the third switch tube between the first wafer and the second wafer, so that the drain electrode of the bias tube is connected to the reference capacitor through the first switch tube and is connected to the signal capacitor through the third switch tube.
- The method of claim 14 or 15, wherein the first circuit comprises a photodiode, a pass transistor, a reset transistor, and a first source follower;the second circuit comprises a bias tube, a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
- The method of claim 20, wherein the gate of the first source follower is connected to the photodiode through the transfer transistor and to a power supply through the reset transistor;the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube;a source electrode of the second source follower is connected to the row gate tube;wherein said electrically connecting said first circuitry and said second circuitry between said first wafer and said second wafer comprises:and electrically connecting the source electrode of the first source follower and the drain electrode of the bias tube between the first wafer and the second wafer.
- The method of claim 14 or 15, wherein the first circuit comprises a photodiode, a pass transistor, a reset transistor, a first source follower, and a bias transistor;the second circuit comprises a first switch tube, a second switch tube, a first capacitor, a second source follower and a row gate tube.
- The method of claim 22, wherein the gate of the first source follower is connected to the photodiode through the transfer transistor and to a power supply through the reset transistor;the source electrode of the first source follower is connected to the drain electrode of the bias tube;the first switch tube is connected to the first capacitor and is connected to the second capacitor and the grid electrode of the second source follower through the second switch tube;a source electrode of the second source follower is connected to the row gate tube;wherein said electrically connecting said first circuitry and said second circuitry between said first wafer and said second wafer comprises:and electrically connecting the drain electrode of the bias tube and the first switch tube between the first wafer and the second wafer, so that the drain electrode of the bias tube is connected to the first capacitor through the first switch tube and is connected to the second capacitor and the grid electrode of the second source follower through the first switch tube and the second switch tube.
- The method of any of claims 14 to 23, wherein electrically connecting the first and second circuits between the first and second wafers comprises:and connecting the first circuit and the second circuit by adopting intermetallic bonding between the first wafer and the second wafer.
- The method of any one of claims 15 to 24, further comprising:and thinning the first wafer so that the photodiode receives an optical signal.
- A pixel circuit of an image sensor, comprising:the device comprises a photodiode, a transmission tube, a reset tube, a first source follower, a bias tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a signal capacitor, a reference capacitor, a second source follower and a row gate tube;the grid electrode of the first source follower is connected to the photodiode through the transmission tube and is connected to a power supply through the reset tube;the source electrode of the first source follower is connected to the drain electrode of the bias tube;the drain electrode of the bias tube is connected to the reference capacitor through the first switching tube and is connected to the signal capacitor through the third switching tube;the grid electrode of the second source follower is connected to the reference capacitor through the second switching tube and is connected to the signal capacitor through the fourth switching tube;the source of the second source follower is connected to the row strobe pipe.
- The pixel circuit according to claim 26, wherein the pixel circuit is disposed on and electrically connected between a plurality of wafers.
- The pixel circuit according to claim 26 and 27, wherein the photodiode, the transfer transistor, the reset transistor and the first source follower are disposed on a first wafer;the bias transistor, the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the signal capacitor, the reference capacitor, the second source follower, and the row gate transistor are disposed on a second wafer;the source electrode of the first source follower and the drain electrode of the bias tube are electrically connected between the first wafer and the second wafer.
- The pixel circuit according to claims 26 and 27, wherein the photodiode, the transfer transistor, the reset transistor, the first source follower, and the bias transistor are disposed on a first wafer;the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the signal capacitor, the reference capacitor, the second source follower and the row gate tube are arranged on a second wafer;the drain electrode of the bias tube is electrically connected with the first switch tube and/or the third switch tube between the first wafer and the second wafer.
- The pixel circuit according to any of claims 26 to 29, wherein the electrical connection comprises an inter-metal bond connection.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2018/118152 WO2020107316A1 (en) | 2018-11-29 | 2018-11-29 | Image sensor, method for preparing image sensor, and pixel circuit |
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| US6635857B1 (en) * | 2000-07-10 | 2003-10-21 | National Semiconductor Corporation | Method and apparatus for a pixel cell architecture having high sensitivity, low lag and electronic shutter |
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| CN206301795U (en) * | 2016-02-08 | 2017-07-04 | 半导体元件工业有限责任公司 | imaging pixel array and processor system |
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| US9299736B2 (en) * | 2014-03-28 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| CN104701334A (en) * | 2015-02-15 | 2015-06-10 | 格科微电子（上海）有限公司 | Deep-groove isolated stacked image sensor manufacturing method |
| CN106328581B (en) * | 2015-07-02 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
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| US6635857B1 (en) * | 2000-07-10 | 2003-10-21 | National Semiconductor Corporation | Method and apparatus for a pixel cell architecture having high sensitivity, low lag and electronic shutter |
| CN104333720A (en) * | 2014-11-12 | 2015-02-04 | 上海集成电路研发中心有限公司 | High-frame-rate global pixel CMOS (Complementary Metal Oxide Semiconductor) image sensor and signal transmission method thereof |
| CN105049750A (en) * | 2015-07-02 | 2015-11-11 | 上海念瞳半导体科技有限公司 | Pixel circuit and control method thereof and global contrast detection image sensor |
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