CN111416814A - Method for realizing POS signal effective data extraction based on FPGA - Google Patents

Abstract

The invention discloses a method for realizing POS signal effective data extraction based on an FPGA. Firstly, carrying out byte escape and effective byte identification processing on data received by a current clock, and adding an effective identification of 0 or 1 to each byte in the data after escape replacement; next, performing byte internal smoothing on the data after the byte escape, namely, moving all effective bytes to the right side of the data for alignment, and assisting with the identification of the number of the effective bytes; and finally, splicing the data with the smoothed bytes with the residual data of the previous clock to obtain effective data extracted by the current clock, and adding an identifier for judging whether the data is effective, and meanwhile, moving the residual effective bytes of the data with the smoothed bytes after splicing to the right of the data to be used for splicing the next clock. The method provided by the invention can well solve the problem of real-time extraction of the effective data of the POS signal, and has wide application value in the field of POS signal protocol analysis processing.

Description

Method for realizing POS signal effective data extraction based on FPGA

Technical Field

The invention relates to the field of POS signal protocol analysis processing, in particular to a method for realizing POS signal effective data extraction based on an FPGA (field programmable gate array), which is used for the protocol analysis of POS signals to extract IP (Internet protocol) data packets.

Background

POS, Packet Over SDH, is a way to carry IP Packet data transport Over SDH signals. The backbone network based on the POS technology has the advantages of higher bandwidth, flexible networking scheme, strong network management performance, quick recovery function and the like, and is widely applied to the construction of metropolitan area networks. When the POS signal is processed by protocol parsing, one of the technical difficulties is how to extract valid data of the POS signal. The extraction of the valid data of the POS signal is usually realized by software, that is, a piece of data is collected first, and then the piece of data is analyzed offline one byte by one byte. The processing mode of the software is simple due to the byte-by-byte sequential processing, but cannot meet the requirement on real-time performance, only can analyze and process a section of data off line, and the rest of data can be discarded. Therefore, the method for extracting the effective data of the POS signal, which can meet the real-time requirement, plays a crucial role in the field of POS signal protocol analysis processing.

Disclosure of Invention

In view of the state of the prior art and the problems in the prior art, the invention provides a method for extracting effective data of a POS signal in real time, namely a method for extracting the effective data of the POS signal based on an FPGA.

The technical scheme adopted by the invention is as follows: a method for realizing POS signal effective data extraction based on FPGA is realized on a hardware platform based on FPGA, and is characterized by comprising the following steps:

firstly, carrying out byte escape and valid byte identification processing on data received by a current clock, namely replacing two continuous bytes of 0x5e7d or 0x5d7d with 0x7e or 0x7d, and adding a valid identifier of 0 or 1 to each byte in the data after escape replacement;

step two, performing byte internal smoothing on the data after the byte escape, namely moving all effective bytes to the right side of the data for alignment, and assisting with the identification of the number of the effective bytes;

thirdly, splicing the data with the smoothed bytes with the remaining data of the previous clock to obtain the effective data extracted by the current clock, and adding an effective identifier of the data, wherein the splicing method comprises the steps of firstly placing the remaining effective bytes of the previous clock on the right side of the finally extracted effective data, and then completing the effective bytes obtained by smoothing the bytes in the current clock to obtain the finally extracted effective data;

and step four, when the splicing processing is finally carried out, the data after byte smoothing is moved to the right side of the data by the residual effective bytes after the splicing processing so as to be used when the data is provided for the next clock splicing processing.

The beneficial effects produced by the invention are as follows: because the POS protocol is analyzed by adopting a hardware mode based on the FPGA, the method is a mode of parallel processing of multiple bytes, compared with the traditional software single-byte analysis mode, the scheme can extract effective data in POS signals in real time without caching a section of data and then analyzing, which is incomparable with the software implementation mode, and the method is implemented on the FPGA by adopting a byte escape, byte internal smoothing and data splicing mode, thereby skillfully solving the problem of hardware implementation complexity.

Drawings

FIG. 1 is a schematic diagram of a method for extracting valid data of POS signals according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings:

fig. 1 is a schematic diagram illustrating a method for extracting valid data of a POS signal according to the present invention, where the data illustrated in the diagram includes 8 bytes, i.e., the method requires 8 bytes to be processed simultaneously per clock cycle. Assume that the data received at clock cycle clk0 (first come byte low) is 64' haa5d7d5d7daa5e7 d; firstly, byte escaping and valid byte identification processing needs to be carried out on the data, namely, two continuous bytes of 0x5e7d or 0x5d7d are replaced by 0x7e or 0x7d, each byte in the data after escaping and replacing is assisted by a valid identification of 0 or 1, the data received by clk0 is escaped and replaced to obtain 64 'haa 7d007d00aa7e00, because two bytes are replaced by one byte, an invalid byte is generated, which is replaced by 00, a byte valid identification corresponding to each byte of the data after replacing is generated, which is 8' b11010110, and from the right, the 0 th, 3 rd and 5 th bytes are invalid because of escaping and replacing; next, byte smoothing needs to be performed on the data 64 ' haa7d007d00aa7e00 after the escape replacement, that is, all the valid bytes are moved to the right side of the data to be aligned, and the identifier of the number of valid bytes is used as an auxiliary, where after the data is smoothed, 64 ' hnull _ null _ null _ null _ aa7d7daa7e is obtained, null indicates that the byte can be any value or does not care how much, and the corresponding number of valid bytes, byte _ valid _ num _ current, is 5 here, which can be obtained by adding each bit in the byte valid identifier 8 ' b11010110 obtained after the previous escape replacement; finally, the smoothed data is spliced with the remaining data of the previous clock to obtain valid data extracted by the current clock, and with the help of whether the data is valid or not, when the current clock cycle clk0, since the valid byte number byte _ valid _ num _ before of the remaining data of the previous clock cycle is 0, that is, the splicing of the clock cycle before clk0 is completed, and there is no data "pushed" when clk0, only the smoothed data 64' hnull _ null _ null _ aa7d7daa7e and the corresponding valid byte number byte _ valid _ num _ current are considered to be 5, since one data includes 8 bytes and the valid byte number of the smoothed data is only 5, the final data extracted by the clock cycle clk0 is invalid, that is, the is _ valid; although the clock cycle clk0 does not extract valid data, the data 64 'hnull _ null _ null _ aa7d7daa7e should not be discarded and should be provided to the next clock cycle for further processing, so the data 64' hnull _ null _ null _ aa7d7daa 7d 7e with a byte _ valid _ num _ before 5 in the clock cycle clk1 as indicated by the arrow "= >" at the time of obtaining clk 0.

Assume that the data received at clock cycle clk1 is 64' h5d7daaaa5e7 daaaa; obtaining data 64' h7d00aaaa7e00aaaa after byte escape; then, carrying out byte internal smoothing to obtain data 64' hnull _ null _7daaaa7eaaaa and the value of the effective byte number byte _ valid _ num _ current of the current clock is 6; finally, the smoothed data 64 ' hnull _ null _7daaaaa 7eaaa and the remaining data 64 ' hnull _ null _ null _ aa7d7daa7e of the previous clock cycle are spliced, specifically, the value of the valid byte number byte _ valid _ num _ before of the previous clock cycle is 5, so that the 5 valid bytes of the previous clock cycle are placed in the clock cycle clk1 to extract the lower 5 bytes of the data, the lowest 3 bytes in the 6 valid bytes of the current clock cycle are filled with the extracted data, and the extracted data of the clock cycle 1 is 64 ' h7 eaaaaa 7d7daa7e, and the valid data identifier is _ valid is 1; since the number of valid bytes after smoothing at clk1 is 6, and the number of valid bytes of the remaining data in the previous clock cycle is 5, the total valid byte is 11, and after 8 bytes of the extracted data are obtained after splicing, 3 bytes remain, that is, the 3 rd, 4 th and 5 th bytes in the remaining smoothed data, and after moving the 3 bytes to the right of the data, 64' hnull _ null _ null _ null _ null _ null _7daaa is obtained and provided for processing in the next clock cycle, that is, the data in clk2 identified by arrow "= >" at clock cycle clk1 in the figure.

As described above, it is assumed that the data 64 'h 5d7 daaaaaaaaaaaaaaaaa is received in the clock cycle clk2, the data 64' h7d00 aaaaaaaaaaaaaaaaaa is obtained after byte escape, then the data 64 'hnull _7 daaaaaaaaaaaaaaa is obtained by byte internal smoothing, and finally the smoothed data 64' hnull _7 daaaaaaaaaaaaa is spliced with the remaining data 64 'hnull _ null _ null _ null _ null _7daaaaa in the previous clock cycle, so as to obtain the valid data 64' haaaaaaaaaaaaaaaaaaaaaaa _7daaaaa extracted in the current clock cycle 2, and the data valid identifier is _ valid is 1.

It can be seen from the above-mentioned process that the method can process 8 bytes of data received in one clock cycle at the same time, and extract the data flowing through in real time through logical processing such as byte escape, byte internal smoothing, data splicing and the like without offline cache, thereby greatly improving the processing speed, which is incomparable with software-based implementation. In conclusion, the method provided by the invention has the characteristic of real-time performance, and provides a valuable reference for the POS signal analysis processing technology.

Claims (1)

1. A method for realizing POS signal effective data extraction based on FPGA is realized on a hardware platform based on FPGA, and is characterized by comprising the following steps:

firstly, carrying out byte escape and valid byte identification processing on data received by a current clock, namely replacing two continuous bytes of 0x5e7d or 0x5d7d with 0x7e or 0x7d, and adding a valid identifier of 0 or 1 to each byte in the data after escape replacement;

step two, performing byte internal smoothing on the data after the byte escape, namely moving all effective bytes to the right side of the data for alignment, and assisting with the identification of the number of the effective bytes;

thirdly, splicing the data with the smoothed bytes with the remaining data of the previous clock to obtain the effective data extracted by the current clock, and adding an effective identifier of the data, wherein the splicing method comprises the steps of firstly placing the remaining effective bytes of the previous clock on the right side of the finally extracted effective data, and then completing the effective bytes obtained by smoothing the bytes in the current clock to obtain the finally extracted effective data;

and step four, when the splicing processing is finally carried out, the data after byte smoothing is moved to the right side of the data by the residual effective bytes after the splicing processing so as to be used when the data is provided for the next clock splicing processing.

Images