CN111415902A - Metal nanostructure, manufacturing method thereof, electronic device and electronic equipment - Google Patents
Metal nanostructure, manufacturing method thereof, electronic device and electronic equipment Download PDFInfo
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- CN111415902A CN111415902A CN202010147555.4A CN202010147555A CN111415902A CN 111415902 A CN111415902 A CN 111415902A CN 202010147555 A CN202010147555 A CN 202010147555A CN 111415902 A CN111415902 A CN 111415902A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1094—Conducting structures comprising nanotubes or nanowires
Abstract
The invention discloses a metal nano structure and a manufacturing method thereof, an electronic device and electronic equipment, relates to the technical field of nano structure manufacturing, and aims to effectively solve the problem that the conventional patterning process is not suitable for manufacturing the metal nano structure. The manufacturing method of the metal nano structure comprises the steps of providing a substrate; forming patterned nanostructures on a substrate; metal nanostructures are formed on the surface of the patterned nanostructures facing away from the substrate. The metal nano structure is prepared by the preparation method provided by the invention, and the metal nano structure provided by the invention is applied to electronic devices and electronic equipment.
Description
Technical Field
The invention relates to the technical field of nano structure manufacturing, in particular to a metal nano structure and a manufacturing method thereof, an electronic device and electronic equipment.
Background
Nanostructures are made of nanomaterials whose dimensions in at least one direction are limited to 100 nanometers or less, including nanowires, nanorods, nanotubes, nanobelts, nanosheets, and the like.
The metal nano structure has the advantages of high mechanical strength, good conductivity and large specific surface area, and has wide application prospect in multiple aspects.
When a metal nano-wire material is used for manufacturing a metal nano-structure applied to an electronic device, a conventional patterning process is no longer suitable for manufacturing the metal nano-structure because the metal nano-wire material is extremely difficult to etch, and therefore a manufacturing method suitable for the metal nano-structure is urgently needed to be provided.
Disclosure of Invention
The invention aims to provide a metal nanostructure and a manufacturing method thereof, an electronic device and electronic equipment, so that the metal nanostructure is directly formed on the surface of a patterned nanostructure under the shielding of the patterned nanostructure, the metal nanostructure can be directly manufactured without patterning through one-time film forming, and the problem that the conventional patterning process is not suitable for manufacturing the metal nanostructure is effectively solved.
In order to achieve the above object, the present invention provides a method for fabricating a metal nanostructure, comprising:
providing a substrate;
forming patterned nanostructures on a substrate;
metal nanostructures are formed on the surface of the patterned nanostructures facing away from the substrate.
Preferably, forming patterned nanostructures on a substrate comprises:
forming a plurality of groove bodies and a patterned mask layer covering the groove bodies on a substrate; the patterned mask layer is provided with a plurality of hollow parts which are in one-to-one correspondence with the plurality of groove bodies.
Preferably, forming a plurality of trenches and a patterned mask layer covering the plurality of trenches on a substrate includes:
forming a patterned mask layer on the surface of the substrate;
a plurality of trenches is formed in the substrate using the patterned mask layer.
Preferably, the orthographic projection of each hollow part on the layer where the groove bottom of the groove body is located in the groove bottom of the groove body, or coincides with the groove bottom of the groove body.
Preferably, the patterned mask layer further comprises a plurality of shielding parts; when forming a plurality of trenches and a patterned mask layer covering the plurality of trenches on a substrate, forming the plurality of trenches and the patterned mask layer covering the plurality of trenches on the substrate further includes:
forming a plurality of projections corresponding to the plurality of shielding portions one to one on the substrate; two adjacent groove bodies are provided with inner walls extending towards the bulges.
Preferably, adjacent two of the grooves communicate with each other.
Preferably, the patterned mask layer comprises:
a first support section;
a second support part spaced from and disposed opposite to the first support part;
and at least one load beam disposed between the first support and the second support.
Preferably, when the patterned nanostructure forms a metal nanostructure on a surface facing away from the substrate, the method further comprises:
forming a bottom metal layer on the surface of the substrate, wherein the orthographic projection of the metal nano structure on the layer of the bottom metal layer is independent from the bottom metal layer;
and/or the presence of a gas in the gas,
the material of the patterned nano structure comprises any one of silicon nitride, silicon carbide, silicon oxide and silicon oxynitride;
and/or the presence of a gas in the gas,
the metal nanostructure material includes any one of ruthenium, cobalt, and molybdenum.
Compared with the prior art, the method for manufacturing the metal nanostructure, provided by the invention, has the advantages that the patterned nanostructure is formed on the substrate, so that when the metal nanostructure is formed on the surface of the patterned nanostructure, which is far away from the substrate, the patterned nanostructure is used as a shielding layer, the metal nanostructure material layer is formed in one step without patterning, and the metal nanostructure which is consistent with the patterned nanostructure can be formed on the surface of the patterned nanostructure, which is far away from the substrate. Therefore, the method for manufacturing the metal nano structure provided by the invention does not need to pattern the metal nano wire material layer which is extremely difficult to etch, and can effectively solve the problem that the conventional patterning process is not suitable for manufacturing the metal nano structure.
The invention also provides a metal nano structure, which is prepared by the preparation method of the metal nano structure.
Compared with the prior art, the metal nano structure manufactured by the manufacturing method of the metal nano structure provided by the invention has the same beneficial effects as the manufacturing method, and the details are not repeated herein.
The invention also provides an electronic device comprising the metal nanostructure provided by the invention.
Compared with the prior art, the electronic device comprising the metal nanostructure provided by the invention has the same beneficial effects as the manufacturing method of the metal nanostructure provided by the invention, and the details are not repeated herein.
The invention also provides an electronic device which comprises the metal nano structure provided by the invention.
Compared with the prior art, the electronic device comprising the metal nanostructure provided by the invention has the same beneficial effects as the manufacturing method of the metal nanostructure provided by the invention, and the details are not repeated herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a flow chart of a method for fabricating a metal nanostructure according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a patterned nanostructure provided by an embodiment of the present invention;
FIG. 3 is a cross-sectional view in the front view of FIG. 2;
FIG. 4 is a cross-sectional view taken along the left side of FIG. 2;
FIG. 5 is a schematic top view of a metal nanostructure provided by an embodiment of the present invention;
FIG. 6 is a cross-sectional view in the front view direction of FIG. 5;
FIG. 7 is a cross-sectional view in the left-hand direction of FIG. 5;
FIG. 8 is a front view in cross-section of a second patterned nanostructure provided in accordance with embodiments of the present invention;
FIG. 9 is a front view in cross-section of a third patterned nanostructure provided in accordance with embodiments of the present invention;
FIG. 10 is a schematic view of a metal nanostructure corresponding to a third patterned nanostructure provided by embodiments of the present invention;
FIG. 11 is a front view in cross-section of a fourth patterned nanostructure provided in accordance with embodiments of the present invention;
FIG. 12 is a schematic view of a metallic nanostructure corresponding to a fourth patterned nanostructure;
FIG. 13 is a schematic diagram of a structure for forming a layer of masking material on a substrate according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a structure after forming a mesa on a substrate according to an embodiment of the present invention;
FIG. 15 is a schematic top view of a patterned photoresist provided by an embodiment of the invention;
FIG. 16 is a cross-sectional view in the front elevation of FIG. 15;
FIG. 17 is a schematic structural diagram of a patterned mask layer provided in accordance with an embodiment of the present invention;
FIG. 18 is a schematic structural diagram of a patterned photoresist removed structure according to an embodiment of the present invention.
The photoresist comprises a substrate 10, a substrate 100, a groove 101, a protrusion 102, a boss 11, a patterned nanostructure 110, a patterned mask layer 1100, a hollow part 1101, a shielding part 1102, a mask material layer 1103, a first supporting part 1104, a second supporting part 1105, a carrier beam 12, a metal nanostructure 120, a first metal nanostructure 121, a second metal nanostructure 122, a third metal nanostructure 13, a bottom metal layer 14 and a patterned photoresist.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In addition, in the present invention, directional terms such as "upper" and "lower" are defined with respect to a schematically placed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the orientation in which the components are placed in the drawings.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
The application of metal nanowire materials including but not limited to ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc. in the advanced interconnection process of integrated circuits is the hot spot of current research. The method for forming the metal nano structure by using the metal nano wire material comprises a metal stripping process, a side wall transfer process, a Damascus process and the like.
The metal stripping process is suitable for the metal nanowire material layer with the smooth surface appearance, but not suitable for the metal nanowire material layer with the step-type appearance. In addition, the metal lift-off process also has the problem of impurity residues, which will degrade the performance of electronic devices employing the metal nanostructures.
The cross-sectional shape of the metal nanostructure formed by the side wall transfer process is not controllable, and the problems of plasma damage and the like exist.
The damascene process can overcome the problems of the metal stripping process, but has the problem of complex process.
Therefore, although the method for manufacturing the metal nanostructure appears in the prior art, the method is not suitable for manufacturing the metal nanostructure due to the problems of impurity pollution, uncontrollable appearance, complex process and the like.
In view of the above problems, the present invention provides a method for fabricating a metal nanostructure, and fig. 1 is a flowchart illustrating a method for fabricating a metal nanostructure according to an embodiment of the present invention. As shown in fig. 1, the method for fabricating a metal nanostructure includes:
s10: referring specifically to fig. 2, a substrate 10 is provided. The substrate 10 may be, for example, a bulk Silicon substrate, a Silicon-On-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, a Silicon Germanium substrate, a group III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG), although not limited thereto.
S11: referring specifically to fig. 2-4, patterned nanostructures 11 are formed on a substrate 10. The patterned nanostructures 11 may be considered as a mask for the subsequent formation of the metal nanostructures 12 or as a patterned template for the automated patterning of the metal nanostructures 12. The specific structure of the patterned nanostructure 11 depends on the specific structure of the metal nanostructure 12 required for practical conditions, and is not particularly limited herein.
To facilitate forming the patterned nanostructures 11 on the substrate 10 using conventional patterning processes, such as photolithographic etching processes, the patterned nanostructures 11 are preferably of a material that is readily formed on the substrate 10 and that is readily amenable to conventional patterning processes. For example: any of silicon nitride, silicon carbide, silicon oxide, and silicon oxynitride, but the present invention is not limited thereto.
S12: referring specifically to fig. 5-7, metallic nanostructures 12 are formed on the surface of the patterned nanostructures 11 facing away from the substrate 10. The specific structure of the metal nanostructures 12 is consistent with the specific structure of the patterned nanostructures 11 as a mask or patterned template. The metal nanostructures 12 are preferably made of a material having a strong current carrying capability and a small contact resistance with the patterned nanostructures 11, such as: ruthenium, cobalt, molybdenum, or the like, but not limited thereto.
After the patterned nanostructures 11 are formed, they are used as a mask or patterning template for the subsequent formation of metal nanostructures 12. On this basis, the metal nanostructures 12 can be formed in conformity with the patterned nanostructures 11. In view of the fact that the material for forming the metal nanostructure 12 is less suitable for the conventional patterning process than the material for forming the patterned nanostructure 11, the method for fabricating a metal nanostructure provided by the embodiment of the present invention can form the metal nanostructure 12 directly without the patterning process by one-step film formation, thereby effectively solving the problem that the conventional patterning process is not suitable for forming the metal nanostructure 12.
As one possible implementation, with continued reference to fig. 2-4, patterned nanostructures 11 are formed on a substrate 10, comprising:
a plurality of trenches 100 and a patterned mask layer 110 covering the plurality of trenches 100 are formed on the substrate 10. The patterned mask layer 110 has a plurality of hollow portions 1100 corresponding to the plurality of slots 100 one by one.
Here, the one-to-one correspondence between the plurality of grooves 100 and the plurality of hollow portions 1100 means that the plurality of grooves 100 and the plurality of hollow portions 1100 correspond to each other from a spatial perspective.
When the formed patterned nanostructure 11 has a plurality of grooves 100 and a patterned mask layer 110 covering the plurality of grooves 100, and the patterned mask layer 110 has a plurality of hollow portions 1100 corresponding to the plurality of grooves 100 one by one, a metal film layer is formed on the surface of the patterned mask layer 110 away from the substrate 10 by a one-time film forming process, and meanwhile, since the patterned mask layer 110 has a plurality of hollow portions 1100 corresponding to the plurality of grooves 100 one by one, the metal film layer is automatically patterned through the plurality of hollow portions 1100 in the one-time film forming process, so that the metal nanostructure 12 is formed on the surface of the substrate 10 away from the area of the patterned mask layer 110 without the hollow portions 1100. The metal film layer is automatically located in the grooves 100 corresponding to the hollow-out portions 1100 and in the areas of the substrate 10 not covered by the patterned mask layer 110, corresponding to the hollow-out portions 1100.
As an example, referring specifically to fig. 3, an orthographic projection of the hollow 1100 at a level of the bottom of the tank 100 is located within the bottom of the tank 100 or coincides with the bottom of the tank 100. It should be understood that the cross-sectional shapes of the slot 100 and the hollow 1100 are not limited in detail.
Referring to fig. 3, the patterned mask layer 110 may include a plurality of shielding portions 1101 in addition to the plurality of hollow portions 1100. At this time, when forming the plurality of trenches 100 and the patterned mask layer 110 covering the plurality of trenches 100 on the substrate 10, forming the plurality of trenches 100 and the patterned mask layer 110 covering the plurality of trenches 100 on the substrate 10 further includes: a plurality of projections 101 (see fig. 8 in particular) are formed on the substrate 10 in one-to-one correspondence with the plurality of shielding portions 1101, where one-to-one correspondence between the plurality of shielding portions 1101 and the plurality of projections 101 refers to a spatial correspondence, and the plurality of shielding portions 1101 and the plurality of projections 101 correspond to one-to-one correspondence.
As an example, with particular reference to fig. 9, two adjacent channels 100 have inner walls extending towards the protrusion 101, the inner walls being perpendicular to the substrate 10. In other words, an orthogonal projection of the hollow 1100 on a level of the groove bottom of the groove body 100 is located in the groove bottom of the groove body 100, that is, an orthogonal projection of the shielding part 1101 corresponding to the protrusion 101 located between two adjacent groove bodies 100 on a level of the protrusion 101 covers the protrusion 101. That is, the shielding portion 1101 and the projection 101 corresponding thereto form a nearly T-shaped structure. Referring to fig. 10 in particular, when the metal nanostructure 12 is formed by a single film forming process, the nearly T-shaped structure can completely and naturally isolate the metal nanostructure 12 formed on the shielding portion 1101 from the metal film layer formed on the substrate 10 in the area not covered by the shielding portion 1101. That is, since the protrusion 101 extends inward, a metal film layer is not formed on the sidewall of the protrusion 101, and the purpose of complete natural isolation is achieved. When the metal nano structure with the structure is applied to an electronic device, the performance of the electronic device can be further improved.
It should be understood that when the protrusion 101 is relatively high, a metal film layer is formed on the surface of the patterned mask layer 110 away from the substrate 10 by a single film forming process, and the metal film layer can be relatively easily patterned into the metal nano-structure 12 by magnetron sputtering.
As another example, referring specifically to fig. 11, two adjacent channels 100 have inner walls that are concave toward the protrusion 101. Referring to fig. 12 in particular, since two adjacent tanks 100 have inner walls that are recessed toward the protrusions 101, when the metal nanostructures 12 are formed by a single film forming process, the metal nanostructures 12 formed on the shielding portions 1101 and the metal film layer formed in the region of the substrate 10 that is not covered by the shielding portions 1101 are completely and naturally isolated by the recessed portions of the protrusions 101. When the metal nano structure with the structure is applied to an electronic device, the performance of the electronic device can be further improved.
As a third example, referring to fig. 3 in particular, the protrusion 101 located between two adjacent slots 100 is completely removed, and the shielding portion 1101 corresponding to the position of the removed protrusion 101 is in a suspended state. Referring specifically to fig. 6, there is no solid structure that can bear a metal layer between the metal nanostructures 12 formed in the shielding portion 1101 and the metal film layer formed in the region of the substrate 10 not covered by the shielding portion 1101, so that it is possible to fully ensure complete natural isolation between the surface metal nanostructures 12 and the bottom metal film layer 13. When the metal nano structure with the structure is applied to an electronic device, the performance of the electronic device can be further improved.
As another possible implementation, with continued reference to fig. 2-4, the patterned mask layer 110 includes: the first support portion 1103. A second support portion 1104 disposed apart from and opposite to the first support portion 1103; and at least one load beam 1105 disposed between the first support portion 1103 and the second support portion 1104. In this case, the first support portion 1103, the second support portion 1104, and at least one load beam 1105 form a plurality of shielding portions 1101, and the first support portion 1103, the second support portion 1104, and the load beam 1105 enclose a plurality of hollow portions 1100. At this time, referring to fig. 5, the metal nanostructure 12 formed on the surface of the patterned nanostructure 11 away from the substrate 10 includes a first metal nanostructure 120 correspondingly formed on the first support portion 1103 away from the surface of the substrate 10, a second metal nanostructure 121 correspondingly formed on the second support portion 1104 away from the surface of the substrate 10, and a third metal nanostructure 122 correspondingly formed on the load beam 1105 away from the surface of the substrate 10. The third metal nanostructure 122 is a nanowire, a nanosheet, or the like, the first metal nanostructure 120 and the second metal nanostructure 121 can be used as a pad, and in practical application, the conductivity of the third metal nanostructure 122, which is used as a nanowire or a nanosheet, can be directly measured by electrically communicating the first metal nanostructure 120 and the second metal nanostructure 121.
It should be noted that the size of the third metal nanostructure 122, which is a nanowire or a nanosheet, can be controlled by controlling the size of the carrier beam 1105, and the size of the carrier beam 1105 can be flexibly controlled by a conventional patterning process, so that the third metal nanostructure 122 in this embodiment has the advantage of flexible size control.
As a possible implementation manner, as shown in fig. 5 to 7, 10, and 12, when the metal nanostructure 12 is formed on the surface of the patterned nanostructure 11 away from the substrate 10, the method for manufacturing the metal nanostructure further includes:
a bottom metal layer 13 is formed on the surface of the substrate 10, and the orthogonal projection of the metal nanostructure 12 at the level of the bottom metal layer 13 is independent of the bottom metal layer 13.
For example: after forming a plurality of trenches 100 on the substrate 10 by using the patterned mask layer 110, if the metal nanostructures 12 are formed on the surface of the patterned nanostructures 11 away from the substrate 10, the metal nanostructures 12 are substantially formed on the surface of the patterned mask layer 110 having the shielding portion 1101 away from the substrate 10. Meanwhile, under the shielding of the shielding portion 1101, the bottom metal layer 13 is formed on the bottom of the tank body 100 and the region of the substrate 10 not covered by the shielding portion 1101.
Another example is: when the substrate 10 has a higher protruding portion, the vertical distance between the metal nanostructure 12 and the bottom metal layer 13 is higher, and the isolation between the metal nanostructure 12 and the bottom metal layer 13 is better. Accordingly, the better the performance of the electronic device having the metal nanostructures 12.
These partial regions of the metal film corresponding to the openings 1100 form a bottom metal layer 13 in the regions of the substrate 10 not covered by the patterned nanomask layer 110.
The plurality of grooves 100 formed on the substrate 10 can increase the vertical distance between the metal nanostructure 12 and the bottom metal layer 13 to ensure the isolation between the metal nanostructure 12 and the bottom metal layer 13, so that the electronic device to which the metal nanostructure 12 is applied has good performance.
The method of forming the patterned nanostructures 11 on the substrate 10 and the metal nanostructures 12 on the surface of the patterned nanostructures 11 facing away from the substrate 10 will be described in detail below with reference to the drawings, it being understood that the following description is intended to be illustrative only and not limiting.
S20 referring to fig. 13, a mask material layer 1102 is formed on the surface of the substrate 10 by using a conventional film forming process, such as low pressure Chemical Vapor Deposition (L owPressure Chemical Vapor Deposition, abbreviated as L PCVD).
S21: referring specifically to fig. 14, patterning the layer of masking material 1102 and the substrate 10 forms the mesa 102. The mesa 102 is the region where the patterned nanostructure 11 is formed in this embodiment. The patterned layer of masking material 1102 and substrate 10 may be processed using a conventional photolithographic etching process to form the mesa 102 including portions of the layer of masking material 1102 and portions of the substrate 10.
S22: referring specifically to fig. 15 and 16, patterned photoresist 14 is formed on the surface of mesa 102 facing away from substrate 10. A layer of photoresist may be formed on the surface of the mesa 102 facing away from the substrate 10, on the basis of which the patterned photoresist 14 is formed. The specific structure of the patterned photoresist 14 determines the specific structure of the subsequently formed patterned mask layer 110, patterned nanostructures 11, and metal nanostructures 12.
S23, referring to fig. 17 specifically, the patterned mask material layer 1102 on the bump 102 is removed by using the patterned photoresist 14 as a mask to form the patterned mask layer 110, and an exemplary specific structure of the patterned mask layer 110 refers to the specific structure of the patterned mask layer 110 described above, which is not described herein again.
S24: referring specifically to fig. 18, patterned photoresist 14 is removed.
S25: referring to fig. 8, the substrate 10 in the region of the mesa 102 is etched down using the patterned mask layer 110 as a mask to form the trench 100, and the region of the mesa 102 shielded by the patterned mask layer 110 forms the protrusion 101.
S26: referring to fig. 3, 9 and 11 specifically, the protrusion 101 between two adjacent grooves 100 is etched by using an anisotropic etching method, and the etched amount of the protrusion 101 may be determined according to specific working conditions, which is not specifically limited herein. For example: the protrusions 101 between two adjacent grooves 100 may be completely etched away, or a certain amount of the protrusions 101 may be etched, so that the orthographic projection of the finally formed protrusions 101 on the surface of the substrate 10 is completely covered by the orthographic projection of the shielding portions 1101, corresponding to the patterned mask layer 110, on the surface of the substrate 10.
S27: referring specifically to fig. 5 to 7, 10 and 12, a metallization process is used to form metal nanostructures 12 on the surface of the shielding portion 1101 away from the substrate 10, and at the same time, a bottom metal layer 13 is formed on the bottom of the trench 100 and on the area of the substrate 10 not covered by the patterned mask layer 110. An exemplary structure of the metal nanostructure 12 is described above and the metal nanostructure 12 is not described herein.
The embodiment of the invention also provides a metal nano structure. The metal nano structure is manufactured by the manufacturing method of the metal nano structure provided by the embodiment of the invention.
The metal nanostructure manufactured by the manufacturing method of the metal nanostructure provided by the embodiment of the invention has the same beneficial effects as the manufacturing method, and the details are not repeated herein.
The embodiment of the invention also provides an electronic device. The electronic device at least comprises the metal nano structure manufactured by the embodiment. For example: the electronic device may be a gate-all-around transistor or the like. As for the beneficial effects of the electronic device, the beneficial effects of the foregoing metal nanostructure manufacturing method can be referred to, and are not described herein again.
The embodiment of the invention also provides an integrated circuit. The integrated circuit at least comprises the metal nano structure provided by the embodiment. As for the beneficial effects of the integrated circuit, the beneficial effects of the foregoing metal nanostructure manufacturing method can be referred to, and are not described herein again.
The embodiment of the invention also provides a chip. The chip comprises the metal nano structure provided by the embodiment. As for the beneficial effects of the chip, the beneficial effects of the foregoing metal nanostructure manufacturing method can be referred to, and are not described herein again.
The embodiment of the invention also provides electronic equipment, which comprises the metal nano structure provided by the embodiment. As for the beneficial effects of the electronic device, the beneficial effects of the foregoing metal nanostructure manufacturing method can be referred to, and are not described herein again.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A method of fabricating a metal nanostructure, comprising:
providing a substrate;
forming patterned nanostructures on the substrate;
and forming metal nanostructures on the surface of the patterned nanostructure, which faces away from the substrate.
2. The method of claim 1, wherein forming patterned nanostructures on the substrate comprises:
forming a plurality of groove bodies and a patterned mask layer covering the groove bodies on the substrate; the patterned mask layer is provided with a plurality of hollow parts which are in one-to-one correspondence with the plurality of groove bodies.
3. The method of claim 2, wherein forming a plurality of trenches and a patterned mask layer over the plurality of trenches on the substrate comprises:
forming the patterned mask layer on the surface of the substrate;
and forming the plurality of grooves on the substrate by using the patterned mask layer.
4. The method of claim 2, wherein an orthographic projection of each hollow portion on a layer of the groove bottom of the groove body is located in the groove bottom of the groove body, or coincides with the groove bottom of the groove body.
5. The method of claim 2, wherein the patterned mask layer further comprises a plurality of shielding portions; when forming a plurality of trenches and a patterned mask layer covering the plurality of trenches on the substrate, forming the plurality of trenches and the patterned mask layer covering the plurality of trenches on the substrate further includes:
forming a plurality of projections corresponding to the plurality of shielding portions one to one on the substrate; two adjacent groove bodies are provided with inner walls extending towards the bulges.
6. The method of claim 2, wherein adjacent two of the channels communicate with each other.
7. The method of claim 2, wherein the patterned mask layer comprises:
a first support section;
a second support part spaced from and disposed opposite to the first support part;
and at least one load beam disposed between the first and second supports.
8. The method as claimed in any one of claims 1 to 7, further comprising, when forming the metal nanostructure on a surface of the patterned nanostructure facing away from the substrate:
forming a bottom metal layer on the surface of the substrate, wherein the orthographic projection of the metal nanostructure on the layer of the bottom metal layer is independent of the bottom metal layer;
and/or the presence of a gas in the gas,
the material of the patterned nano structure is any one of silicon nitride, silicon carbide, silicon oxide and silicon oxynitride;
and/or the presence of a gas in the gas,
the metal nano structure is made of any one of ruthenium, cobalt and molybdenum.
9. A metal nanostructure, characterized in that it is produced by the method for producing a metal nanostructure according to any one of claims 1 to 8.
10. An electronic device comprising the metal nanostructure of claim 9.
11. An electronic device comprising the metal nanostructure of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010147555.4A CN111415902B (en) | 2020-03-05 | 2020-03-05 | Metal nano structure, manufacturing method thereof, electronic device and electronic equipment |
Applications Claiming Priority (1)
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199004A (en) * | 2013-02-22 | 2013-07-10 | 国家纳米科学中心 | Manufacturing method of III-group nitride nano-structure |
| CN103258741A (en) * | 2012-02-20 | 2013-08-21 | 中芯国际集成电路制造(上海)有限公司 | Nanowire field effect transistor and forming method thereof |
| CN104609360A (en) * | 2013-11-05 | 2015-05-13 | 中国科学院微电子研究所 | Nano wire and array formation method |
| CN104795326A (en) * | 2014-01-16 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon nanowire structure |
| CN108091569A (en) * | 2016-11-23 | 2018-05-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
| US20180277682A1 (en) * | 2015-12-07 | 2018-09-27 | Institute of Microelectronics, Chinese Academy of Sciences | Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same |
| CN110620033A (en) * | 2019-08-26 | 2019-12-27 | 中国科学院微电子研究所 | Method for manufacturing metal nanowire or sheet and nanowire or sheet |
-
2020
- 2020-03-05 CN CN202010147555.4A patent/CN111415902B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258741A (en) * | 2012-02-20 | 2013-08-21 | 中芯国际集成电路制造(上海)有限公司 | Nanowire field effect transistor and forming method thereof |
| CN103199004A (en) * | 2013-02-22 | 2013-07-10 | 国家纳米科学中心 | Manufacturing method of III-group nitride nano-structure |
| CN104609360A (en) * | 2013-11-05 | 2015-05-13 | 中国科学院微电子研究所 | Nano wire and array formation method |
| CN104795326A (en) * | 2014-01-16 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon nanowire structure |
| US20180277682A1 (en) * | 2015-12-07 | 2018-09-27 | Institute of Microelectronics, Chinese Academy of Sciences | Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same |
| CN108091569A (en) * | 2016-11-23 | 2018-05-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
| CN110620033A (en) * | 2019-08-26 | 2019-12-27 | 中国科学院微电子研究所 | Method for manufacturing metal nanowire or sheet and nanowire or sheet |
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