CN111415617A - Method for improving gamma voltage stabilization time of O L ED panel by adding latch - Google Patents
Method for improving gamma voltage stabilization time of O L ED panel by adding latch Download PDFInfo
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- CN111415617A CN111415617A CN202010255959.5A CN202010255959A CN111415617A CN 111415617 A CN111415617 A CN 111415617A CN 202010255959 A CN202010255959 A CN 202010255959A CN 111415617 A CN111415617 A CN 111415617A
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- latch
- atch
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- gamma voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
Abstract
The invention relates to a method for improving gamma voltage stabilization time of an O L ED panel by adding a latch, wherein a driving chip of the O L ED panel comprises a latch, a gamma voltage block, a decoder and a channel amplifier, particularly, the latch comprises a PC L K latch, an S L ATCH latch and a T L2 ATCH latch, the T L ATCH latch is activated in the range from the current activation of the S L ATCH latch to the next activation of the S L ATCH latch, and the gamma voltage block and the channel amplifier normally work after the T L ATCH latch is activated.
Description
Technical Field
The invention relates to the technical field of improving the gamma voltage stabilization time of an O L ED panel, in particular to a method for improving the gamma voltage stabilization time of an O L ED panel by adding latches.
Background
In recent years, the screen resolution has been gradually improved, and QHD-plus and FHD-plus require 21:9 or 21:10 screens. And, due to the effect of folding the handset, the resolution is getting larger and larger. For example, QHD +:1440RGB x3360 (screen resolution 1440 x3360 of QHD +); QXGA +:1600RGBx3360 ((screen resolution 1600 x3360 of QXGA +)), FHD +:1080RGBx2520 (screen resolution 1080 x2520 of FHD +), UXGA +:1200RGBx2520 (screen resolution 1200 x2520 of UXGA +). with the increase of screen resolution, the progress of communication technology requires AR or VR applications to increase operations of 90Hz and 120Hz instead of the conventional 60Hz operation, and the 5G communication era comes due to the increase of data transmission rate.
From the perspective of the design of the O L ED driver chip, the screen resolution is getting higher and higher, and the absolute time for driving the panel is decreasing.
FIG. 1 shows a schematic block diagram of the internal circuitry of an O L ED panel driver chip corresponding to 1440RGBG X3360 of QHD +21:9, which consists of a 720RGBG rendering based latch (latch), an R/G/B gamma voltage block (gamma), a 720RGBG Decoder (Decoder), and a channel Amplifier (AMP). The output of the latch and the output of the R/G/B gamma voltage block combine to drive the Decoder and channel amplifier.
Conventional latch structures as shown in fig. 4, the latches are dual stack latch structures, and the latches are generally composed of two layers of latches, including a PC L K latch at a first layer and an S L ATCH latch at a second layer the PC L K latch is a pixel clock latch and the S L ATCH latch is a line latch.
The O L ED panel driving chip using the conventional latch structure of FIG. 4 has driving timing and Source block operation timing as shown in FIG. 2, a 21:9 RGBX3360 resolution of QHD-plus, a 90 Hz. frame frequency scanning driver running on two phase control clocks GCK1 and GCK2, EM is Emission driving, SOUT1 and SOUT2 are Source output, and the O L ED panel is divided into Source change state (Source changing), Programming state (Programming) and excitation state (Emission).
In detail, as in fig. 2, G1 is a single row time, 3.26 us. charges the O L ED panel during G1 and stores the charged voltage in the capacitor, with the conventional dual stack latch structure of fig. 4, after the PC L K latch completes transferring all the pixel data of one group, the S L0 ATCH latch is activated S L1 ATCH latch is activated and the gamma voltage block and the Channel Amplifier can normally operate, when the PC L K latch does not complete transferring all the pixel data of one group, the S L ATCH latch will not be activated S L ATCH latch is activated in the range from the current group of data transfer end to the next group of data start transfer of the PC L K latch, thus the activation range of the S L latch is very narrow, when the O L ED panel enters the programming state, the L K latch has not yet completed transferring all the pixel data of the PC group, therefore the S L h latch cannot enter the O state, when the atc 2K latch enters the programming state, the atc 2K latch can enter the S L state, the gamma voltage is set when the ATCH panel is stable, the ATCH latch is set at the stable time when the ATCH gate initialization time is set by the ATCH Amplifier, the ATCH latch is stable.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for improving the gamma voltage stabilization time of an O L ED panel by adding a latch, which can improve the gamma voltage stabilization time of an O L ED panel.
The technical scheme includes that a method for improving gamma voltage stabilization time of an O L ED panel by adding a latch is adopted, a driving chip of the O L ED panel comprises a latch, a gamma voltage block, a decoder and a channel amplifier, particularly, the latch comprises a PC L K latch, an S L ATCH latch and a T L ATCH latch, the T L ATCH latch is activated in a range from current activation of the S L ATCH latch to next activation of the S L ATCH latch, and the gamma voltage block and the channel amplifier are enabled to normally work after the T L ATCH latch is activated.
Preferably, the latch is a three-stack latch structure.
The PC L K latch is a pixel clock latch for synchronous output of pixel data, and the PC L K latch is a first layer latch.
The S L ATCH latch is a line latch, the S L ATCH latch is activated after the PC L K latch outputs all pixel data of one group, and the S L ATCH latch is a second-layer latch.
The T L ATCH latch is a third layer latch.
More preferably, the T L ATCH latch includes a T L ATCH1 latch and a T L0 ATCH2 latch, the T L ATCH1 latch is activated in a range from the current activation of the S L ATCH latch to the next activation of the S L ATCH latch, the T L ATCH2 latch is activated in a range from the current activation of the S L ATCH latch to the next activation of the S L ATCH latch, and the activation of the T L ATCH1 latch and/or the T L ATCH2 latch enables the gamma voltage block and the channel amplifier to work normally.
The invention has the advantages that the activation range of the T L ATCH latch is wider, so that the T L ATCH latch can be activated and operated when the PC L K latch does not synchronously transmit all pixel data of one group.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of the internal circuitry of a conventional O L ED panel driver chip;
fig. 2 is a driving timing and a source block operation timing of an O L ED panel driving chip employing a conventional latch structure;
FIG. 3 is a driving timing and source block operation timing of an O L ED panel driver chip employing the improved latch structure of the present invention;
FIG. 4 is a conventional dual stack latch structure;
fig. 5 is an improved three-stack latch structure of the present invention.
Detailed Description
The invention will now be further described with reference to the accompanying drawings. These drawings are simplified schematic diagrams only illustrating the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
In a preferred embodiment, a method for improving gamma voltage stabilization time of an O L ED panel by adding a latch, a driving chip of the O L ED panel comprises a latch, a gamma voltage block, a decoder and a channel amplifier, the latch comprises a PC L K latch, an S L ATCH latch and a T L ATCH latch, the T L ATCH latch is activated within a range from the current activation of the S L ATCH latch to the next activation of the S L ATCH latch, and the gamma voltage block and the channel amplifier are enabled to work normally after the T L ATCH latch is activated.
As shown in FIG. 5, the latches are three-stack latch structures, the PC L K latch is a pixel clock latch for synchronous output of pixel data, the PC L K latch is a first-layer latch, the S L ATCH latch is a line latch, the S L ATCH latch is activated after the PC L K latch outputs all pixel data in a group, the S L ATCH latch is a second-layer latch, and the T L ATCH latch is a third-layer latch.
The T L ATCH latches include a T L ATCH1 latch and a T L ATCH2 latch, the T L ATCH1 latch activates in the range from the S L ATCH latch currently activated to the next activation of the S L ATCH latch, and the T L ATCH2 latch activates in the range from the S L ATCH latch currently activated to the next activation of the S L ATCH latch.
Because the T L ATCH latch activates in the range from the S L ATCH latch currently activated to the next activation of the S L ATCH latch, the selectable range of T L ATCH latch activations is wide, and therefore the T L ATCH latch also activates operation when the PC L K latch does not complete the synchronized transfer of all pixel data for a group.
The driving timing and Source block operation timing of the O L ED panel driving chip using the three-stack latch structure of fig. 5 are shown in fig. 3, and similarly, 1440RGBX3360 with resolution QHD-plus of 21:9, a scanning driving program with frame frequency of 90 Hz. are run on two phase control clocks GCK1 and GCK2, EM is Emission driving, SOUT1 and SOUT2 are Source outputs, the O L ED panel is divided into Source change state (Source changing), Programming state (Programming), and firing state (Emission).
In detail, as in fig. 3, G1 is a single row time, which is 3.26 us. during G1, the channel amplifier charges the O L ED panel and stores the charged voltage in the capacitor after the PC L K latch completes the transfer of all the pixel data in a group, the S L0 ATCH latch is activated, the T L ATCH1 latch is activated in the range where the S L ATCH latch is currently activated to the next activation of the S L ATCH latch, the T L ATCH2 latch is activated in the range where the S L ATCH latch is currently activated to the next activation of the S L ATCH latch, and thus the selectable ranges of the activation of the T L ATCH1 latch, the T L ATCH2 latch are wide.
The T L ATCH1 latch and the T L ATCH2 latch can still be activated to operate when the O L ED panel enters a programming state, although the PC L K latch does not finish the data transmission of all pixels of one group, the T L ATCH1 latch and the T L ATCH2 latch can still be activated to operate, the setting time (Channel Amplifier) and the Gamma stabilizing time (Gamma stabilizing 393985) of the Channel Amplifier are not limited by the S38 ATCH latch, and the Gamma stabilizing time and the setting time of the Channel Amplifier are both longer than those of the traditional Channel Amplifier.
The invention adds the T L ATCH latch, and although the area of the driving chip is slightly increased, the gamma stabilizing time and the setting time of the channel amplifier can be effectively lengthened.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (3)
1. A method for improving gamma voltage stabilization time of an O L ED panel by increasing a latch comprises the steps that a driving chip of the O L ED panel comprises the latch, a gamma voltage block, a decoder and a channel amplifier, and is characterized in that the latch comprises a PC L K latch, an S L ATCH latch and a T L ATCH latch, the T L ATCH latch is activated in the range from the current activation of the S L ATCH latch to the next activation of the S L ATCH latch, and the gamma voltage block and the channel amplifier are enabled to work normally after the T L ATCH latch is activated.
2. The method of claim 1, wherein the latches are tri-stack latches,
the PC L K latch is a pixel clock latch and is used for synchronous output of pixel data, and the PC L K latch is a first-layer latch;
the S L ATCH latch is a line latch, the S L ATCH latch is activated after the PC L K latch outputs all pixel data of one group, the S L ATCH latch is a second-layer latch;
the T L ATCH latch is a third layer latch.
3. The method for increasing gamma voltage stabilization time of an O L ED panel by an additional latch according to claim 1, wherein the T L ATCH latch comprises a T L0 ATCH1 latch and a T L1 ATCH2 latch, the T L ATCH1 latch is activated in a range from the S L ATCH latch currently activated to the S L ATCH latch next activated, the T L ATCH2 latch is activated in a range from the S L ATCH latch currently activated to the S L ATCH latch next activated, and the T L ATCH1 latch and/or the T L ATCH2 latch are activated to enable the gamma voltage block and the channel amplifier to work normally.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010255959.5A CN111415617B (en) | 2020-04-02 | 2020-04-02 | Method for increasing gamma voltage stabilization time of OLED panel by adding latch |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010255959.5A CN111415617B (en) | 2020-04-02 | 2020-04-02 | Method for increasing gamma voltage stabilization time of OLED panel by adding latch |
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| CN111415617A true CN111415617A (en) | 2020-07-14 |
| CN111415617B CN111415617B (en) | 2021-07-06 |
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| CN111415617B (en) | 2021-07-06 |
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