CN111414199B - Method and device for implementing instruction fusion - Google Patents
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- CN111414199B CN111414199B CN202010260633.1A CN202010260633A CN111414199B CN 111414199 B CN111414199 B CN 111414199B CN 202010260633 A CN202010260633 A CN 202010260633A CN 111414199 B CN111414199 B CN 111414199B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000002159 abnormal effect Effects 0.000 claims description 21
- 230000005856 abnormality Effects 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 238000004590 computer program Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Abstract
The invention relates to a microprocessor design technology, in particular to a method and a device for realizing instruction fusion. The invention can effectively realize instruction fusion, has simple design and can ensure the realization of accurate exception.
Description
Technical Field
The invention relates to a microprocessor design technology, in particular to a method and a device for realizing instruction fusion.
Background
When a processor architecture with a fixed instruction length expands a new instruction, because the number of instructions is increased, more encoding bits are needed to be used as operation codes to represent instruction functions, and after the operation codes are removed, the number of operands which can be represented by the remaining bits in the instruction encoding is limited, so that some instructions may not be encoded normally. For example, normally, a floating-point multiply-add instruction requires 3 source operands and 1 destination operand, we use FPMA Rd, rs1, rs2, rs3 to indicate that the instruction performs the function Rd = (Rs 1 xRs) + Rs3. The architecture typically defines 32 software visible floating-point registers, one requiring a 5-bit representation of the floating-point register operand, and 3 source operands and 1 destination operand requiring 20-bit instruction encodings. When 4 floating-point register type operands can not be encoded, the architecture uses an accumulation multiply instruction, the instruction only explicitly encodes 2 source operands and 1 destination operand, we use FPFMA Rd, RS1 and Rs2 to indicate, the destination operand Rd is implicitly used as a source operand, the completed function is Rd = (Rs 1 xRs) + Rd, the accumulation multiply instruction also completes the floating-point multiply-add function, but belongs to a destructive instruction, and the added number content in the multiply-add operation is destroyed. Assume that the function of the normal floating-point multiply-add instruction (Rs 1xRs 2) + Rs3 is completed by the multiply-accumulate instruction, which means that FPFMA Rs3, rs1, rs2, that is, rs3= (Rs 1xRs 2) + Rs3, and the addend Rs3 is rewritten.
Some architectures define a prefix instruction for performing non-destructive instruction functions in conjunction with the immediately following instruction. For convenience of description, we will refer to the PREFIX instruction with PREFIX Rd, rs, whose function is to write the value in the floating-point register Rs into Rd, which can be fused with the following instruction that satisfies certain conditions into one instruction for execution. For example, we use the prefix instruction and multiply-accumulate instruction as shown below to perform normal floating-point multiply-add function:
PREFIX Rd, Rs3
FPFMA Rd, Rs1, Rs2
the functions completed by the above two instructions are: rd = (Rs 1xRs 2) + Rs3.
The architecture requires that when the microprocessor is designed, the prefix instruction and the following instruction (for convenience of description, the prefix instruction is called as a prefix instruction) which can be fused with the prefix instruction can be separately executed or can be fused into one instruction for execution. No matter which way is adopted for execution, when the prefixed instruction is abnormal, it must be ensured that the precise exception can be realized, that is, if the prefixed instruction updates the architecture state, the exception report is at the prefixed instruction, and the exception return address is the address of the prefixed instruction, and if the prefixed instruction does not update the architecture state, the exception report is at the prefixed instruction, and the exception return address is at the address of the prefixed instruction.
In summary, it is easy to implement that when a microprocessor is designed, a prefix instruction and a prefixed instruction are separately executed, but if the prefix instruction and the prefixed instruction are fused into one instruction for execution, performance and power consumption of a processor are beneficial, and how to ensure that a design meets an architecture requirement is a challenge.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention can effectively realize the instruction fusion, is beneficial to improving the performance of a processor and reducing the power consumption of the processor, has simple design and can ensure the realization of accurate exception.
In order to solve the technical problems, the invention adopts the technical scheme that:
an implementation method for instruction fusion comprises the following implementation steps:
1) In the instruction fetching stage, an instruction is fetched;
2) In the decoding stage, judging whether a prefix instruction meeting the fusion condition and a prefixed instruction appear continuously and are decoded in the same beat, if so, fusing the prefix instruction to the prefixed instruction to form an instruction, marking the instruction as a fusion instruction, changing a source operand of the prefix instruction into a source operand of the fusion instruction, and replacing an implicit source operand; if not, normally decoding the instruction;
3) Renaming, dispatching and executing the instruction, if the instruction is a fusion instruction, adding a mark bit to the fusion instruction, and transmitting the added mark bit stage by stage along a pipeline;
4) In the submitting stage, whether the fused instruction with the additional mark bit is abnormal is judged, if the fused instruction is not abnormal, the fused instruction is submitted and the submitted address is advanced by two instructions, if the fused instruction is abnormal, the fused instruction cannot be submitted, the prefix instruction and the prefixed instruction do not update the architecture state, the current submitted address stays at the prefix instruction, so that the exception is reported at the prefix instruction, and the exception return address is the address of the prefix instruction.
Optionally, the detailed steps of step 2) include:
2.1 Judging whether the instructions decoded simultaneously contain a prefix instruction, if so, skipping to execute the step 2.2), otherwise, skipping to execute the step 2.6);
2.2 Judging whether the prefix instruction is the last effective instruction, if not, skipping to execute the step 2.3), otherwise, skipping to execute the step 2.6);
2.3 Judging whether the next instruction of the prefix instruction meets the fusion condition and can be fused with the prefix instruction, if so, skipping to execute the step 2.4), otherwise, skipping to execute the step 2.6);
2.4 Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fused instruction, and then jump to execute step 2.5);
2.5 ) the source operand of the prefix instruction becomes one of the source operands of the fused instruction, replaces the implicit source operand, and then jumps to execute step 3);
2.6 Normal decoding is performed and then a jump is performed to step 3).
Optionally, the detailed steps of step 4) include:
4.1 Judging whether the instruction entering the submission stage is a fusion instruction according to the mark bits transmitted step by step along with the pipeline, if so, executing the step 4.2), otherwise, executing the step 4.5);
4.2 Judging whether the fusion instruction is abnormal or not, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3 An exception is reported at the prefix instruction, the exception return address being the address of the prefix instruction;
4.4 Commit the fused instruction, commit the address advance two instructions;
4.5 Judging whether the non-fusion instruction is abnormal, if so, skipping to execute the step 4.6), otherwise, skipping to execute the step 4.7);
4.6 An exception is reported at the instruction, the exception return address being the address of the instruction;
4.7 The commit address advances by one instruction).
In addition, the invention also provides a device for realizing the instruction fusion, and the device for realizing the instruction fusion is programmed or configured to execute the steps of the method for realizing the instruction fusion.
Furthermore, the invention also provides a microprocessor which is programmed or configured to execute the steps of the method for implementing the instruction fusion.
Compared with the prior art, the invention has the following advantages:
1. the invention has simple design. The invention judges whether the prefix instruction and the prefixed instruction which meet the fusion condition appear continuously and are decoded in the same time in the decoding stage, if yes, the prefix instruction is fused on the prefixed instruction to form an instruction, the instruction is marked as a fusion instruction, the marking bit is transmitted step by step along the production line, the submission address is updated according to the marking bit in the submission stage, and the production line is simple in design.
2. The invention can ensure the realization of accurate abnormity. When the invention has instruction fusion, if the fusion instruction is normally submitted, the address is submitted to advance two instructions, if the fusion instruction is abnormal, the abnormality is reported at the prefix instruction, the prefix instruction does not update the architecture state, and the abnormal return address is the address of the prefix instruction, thereby realizing the accurate abnormality.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Fig. 2 is a detailed flow chart of the embodiment of the invention.
Detailed Description
As shown in fig. 1, the implementation steps of the method for implementing instruction fusion in this embodiment include:
1) In the instruction fetching stage, an instruction is fetched; this step is the same as the prior art;
2) In the decoding stage, judging whether a prefix instruction meeting the fusion condition and a prefixed instruction appear continuously and are decoded in the same beat, if so, fusing the prefix instruction to the prefixed instruction to form an instruction, marking the instruction as a fusion instruction, changing a source operand of the prefix instruction into a source operand of the fusion instruction, and replacing an implicit source operand; if not, normally decoding the instruction;
3) Renaming, dispatching and executing the instruction, if the instruction is a fusion instruction, adding a mark bit to the fusion instruction, and transmitting the added mark bit stage by stage along a pipeline; this step is indistinguishable for fused and normal instructions;
4) In the submitting stage, whether the fusion instruction with the additional mark bit is abnormal or not is judged, if the fusion instruction is not abnormal, the fusion instruction is submitted and the submitted address is advanced by two instructions, if the fusion instruction is abnormal, the fusion instruction cannot be submitted, the prefix instruction and the prefixed instruction do not update the architecture state, the current submitted address stays at the prefix instruction, so that the abnormality is reported at the prefix instruction, and the abnormal return address is the address of the prefix instruction, so that the precise abnormality of the floating point can be realized, and the requirement of the architecture is met.
In step 2) of this embodiment, the merging condition is to determine whether there are prefix instructions and prefixed instructions that satisfy the merging condition and are continuously appeared and decoded in the same beat. Therefore, if the prefix instruction is the last one of the effective instructions decoded simultaneously, instruction fusion does not occur, the prefix instruction is normally decoded and enters a rename pipeline station without waiting for the arrival of a subsequent instruction, so even if the instruction which is directly following the prefix instruction can be fused with the prefix instruction, the prefix instruction does not reach the decoding stage simultaneously, and therefore the fusion does not occur.
In this embodiment, the detailed steps of step 2) include:
2.1 Judging whether the instructions decoded simultaneously contain a prefix instruction, if so, skipping to execute the step 2.2), otherwise, skipping to execute the step 2.6);
2.2 Judging whether the prefix instruction is the last effective instruction, if not, skipping to execute the step 2.3), otherwise, skipping to execute the step 2.6);
2.3 Judging whether the next instruction of the prefix instruction meets the fusion condition and can be fused with the prefix instruction, if the fusion condition is met, skipping to execute the step 2.4), otherwise skipping to execute the step 2.6);
2.4 Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fused instruction, and then jump to execute step 2.5);
2.5 ) the source operand of the prefix instruction becomes one of the source operands of the fused instruction, replaces the implicit source operand, and then jumps to execute step 3);
2.6 Normal decoding is performed and then a jump is performed to step 3).
As shown in fig. 2, the detailed steps of step 4) include:
4.1 According to the mark bit transmitted along the pipeline step by step, judging whether the instruction entering the submission stage is a fusion instruction, if so, executing the step 4.2), otherwise, executing the step 4.5);
4.2 Judging whether the fusion instruction is abnormal or not, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3 An exception is reported at the prefix instruction, the exception return address being the address of the prefix instruction;
4.4 Commit the fused instruction, commit the address advance two instructions;
4.5 Judging whether the non-fusion instruction is abnormal, if so, skipping to execute the step 4.6), otherwise, skipping to execute the step 4.7);
4.6 An exception is reported at the instruction, the exception return address being the address of the instruction;
4.7 The commit address advances by one instruction).
In summary, the method for implementing instruction fusion in this embodiment determines, in a decoding stage, whether a prefix instruction and a prefixed instruction that satisfy a fusion condition continuously appear and are decoded in the same beat, if so, the prefix instruction is fused to the prefixed instruction to form a fused instruction, a source operand of the prefix instruction is changed into a source operand of the fused instruction to replace an implicit source operand, if the fused instruction is normally submitted in a submission stage, a submission address advances by two instructions, if the fused instruction is abnormal, an exception is reported at the prefixed instruction, the prefix instruction does not update an architectural state, and an exception return address is an address of the prefixed instruction. The invention has simple design and can ensure the realization of accurate abnormity.
In addition, the present embodiment also provides an apparatus for implementing instruction fusion, which is programmed or configured to execute the steps of the method for implementing instruction fusion.
In addition, the present embodiment also provides a microprocessor programmed or configured to execute the steps of the method for implementing instruction fusion.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (4)
1. A method for implementing instruction fusion is characterized by comprising the following implementation steps:
1) In the instruction fetching stage, an instruction is fetched;
2) In the decoding stage, judging whether a prefix instruction meeting the fusion condition and a prefixed instruction appear continuously and are decoded in the same beat, if so, fusing the prefix instruction to the prefixed instruction to form an instruction, marking the instruction as a fusion instruction, changing a source operand of the prefix instruction into a source operand of the fusion instruction, and replacing an implicit source operand; if not, normally decoding the instruction;
3) Renaming, allocating and executing the instruction, if the instruction is a fusion instruction, adding a mark bit to the fusion instruction, and transmitting the added mark bit along the pipeline stage by stage;
4) In the submitting stage, judging whether the fused instruction with the additional mark bit is abnormal or not, if the fused instruction is not abnormal, submitting the fused instruction and advancing the submitted address by two instructions, if the fused instruction is abnormal, the fused instruction cannot be submitted, the prefix instruction and the prefixed instruction do not update the architectural state, the current submitted address stays at the prefix instruction, so that the prefix instruction reports the abnormality, and the abnormal return address is the address of the prefix instruction;
the detailed steps of the step 2) comprise:
2.1 Judging whether the instructions decoded simultaneously contain a prefix instruction, if so, skipping to execute the step 2.2), otherwise, skipping to execute the step 2.6);
2.2 Judging whether the prefix instruction is the last effective instruction, if not, skipping to execute the step 2.3), otherwise, skipping to execute the step 2.6);
2.3 Judging whether the next instruction of the prefix instruction meets the fusion condition and can be fused with the prefix instruction, if so, skipping to execute the step 2.4), otherwise, skipping to execute the step 2.6);
2.4 Fuse the prefix instruction into the next instruction to form an instruction, mark the instruction as a fused instruction, and then jump to execute step 2.5);
2.5 Source operand of prefix instruction becomes one source operand of fused instruction, replaces implicit source operand, and then jumps to execute step 3);
2.6 Normal decoding is performed and then a jump is performed to step 3).
2. The method for implementing instruction fusion according to claim 1, wherein the detailed step of step 4) comprises:
4.1 Judging whether the instruction entering the submission stage is a fusion instruction according to the mark bits transmitted step by step along with the pipeline, if so, executing the step 4.2), otherwise, executing the step 4.5);
4.2 Judging whether the fusion instruction is abnormal or not, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3 An exception is reported at the prefix instruction, the exception return address being the address of the prefix instruction;
4.4 Commit the fused instruction, commit the address advance two instructions;
4.5 Judging whether the non-fusion instruction is abnormal, if so, skipping to execute the step 4.6), otherwise, skipping to execute the step 4.7);
4.6 An exception is reported at the instruction, the exception return address being the address of the instruction;
4.7 The commit address advances by one instruction).
3. An apparatus for implementing instruction fusion, wherein the apparatus is programmed or configured to execute the steps of the method for implementing instruction fusion of claim 1 or 2.
4. A microprocessor, characterized in that the microprocessor is programmed or configured to perform the steps of the method of implementing the instruction fusion of claim 1 or 2.
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