CN111404829B - Port aggregation method, device, equipment and storage medium - Google Patents
Port aggregation method, device, equipment and storage medium Download PDFInfo
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- CN111404829B CN111404829B CN202010307197.9A CN202010307197A CN111404829B CN 111404829 B CN111404829 B CN 111404829B CN 202010307197 A CN202010307197 A CN 202010307197A CN 111404829 B CN111404829 B CN 111404829B
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- 238000003860 storage Methods 0.000 title claims abstract description 13
- 238000004590 computer program Methods 0.000 claims description 8
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
- H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/24—Multipath
- H04L45/245—Link aggregation, e.g. trunking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
The present disclosure provides a port aggregation method, a device, equipment and a storage medium, where the port aggregation method is used to generate a sequence table when an interface board performs port aggregation, the interface board has a plurality of first ports, and each first port is correspondingly connected with a second port of a screen; the method comprises the following steps: acquiring parameters of a second port correspondingly connected with each first port, wherein the parameters of the second port comprise a screen plate number; and arranging the first ports according to the parameters of the second ports to generate a port aggregation sequence table, wherein the mesh plate numbers of the second ports which are correspondingly connected with the adjacent first ports are different. Each first port of the interface board is connected with different mesh boards at intervals, and then when data transmission is carried out between the interface board and the mesh boards, data flow can be distributed to different mesh boards, load balancing is achieved, and packet loss is avoided.
Description
Technical Field
The disclosure relates to the technical field of network equipment, and in particular relates to a port aggregation method, device, equipment and storage medium.
Background
A Switch (Switch) is a network device for forwarding electrical (optical) signals, which can provide a single shared electrical signal path for any two network nodes accessing the Switch, and is most commonly an ethernet Switch, and other common switches include a voice over telephone Switch, a fiber optic Switch, and the like. The switch is internally provided with a plurality of ports, such as a panel port, an internal port on an interface board, an internal port on a screen board and the like; in view of the working property of the switch, each port needs to pass huge traffic, and compared with the panel port, the traffic pressure of the internal port is particularly high, so that the internal traffic of the switch easily exceeds the load capacity of the internal port, and the packet is lost.
Disclosure of Invention
The present disclosure provides a port aggregation method, device, apparatus, and storage medium.
Specifically, the present disclosure is implemented by the following technical scheme:
in a first aspect, a port aggregation method is provided, configured to generate a sequence table when an interface board performs port aggregation, where the interface board has a plurality of first ports, and each first port is correspondingly connected to a second port of a mesh board; the method comprises the following steps:
acquiring parameters of a second port correspondingly connected with each first port, wherein the parameters of the second port comprise a screen plate number;
and arranging the first ports according to the parameters of the second ports to generate a port aggregation sequence table, wherein the mesh plate numbers of the second ports which are correspondingly connected with the adjacent first ports are different.
Further, the arranging each first port according to the parameters of each second port includes:
grouping the first ports according to the parameters of the second ports to generate at least two groups of first ports, wherein the mesh plate numbers of the second ports connected with the first ports in each group are the same;
and sequentially taking out one first port in each group according to the sequence of each group, putting the first ports into the arrangement sequence, and cycling for a plurality of times until all the first ports are taken out.
Further, the parameters of the second port further include a port number;
the sequentially taking out the first ports in each group and putting the first ports into the arrangement sequence comprises the following steps:
and sequentially taking out the first ports corresponding to the second ports with the forefront port numbers in each group, and putting the first ports into the arrangement sequence.
Further, the method further comprises the following steps:
and respectively storing parameters of the second ports correspondingly connected with the first ports according to the connection relation between the first ports and the second ports.
Further, the method further comprises the following steps:
and writing the port aggregation sequence list into the exchange chip.
Further, the interface board has six, eight or ten first ports.
Further, the interface board is connected with the two net boards.
In a second aspect, a port aggregation device is provided, configured to generate a sequence table when an interface board performs port aggregation, where the interface board has a plurality of first ports, and each first port is correspondingly connected to a second port of a mesh board; the method comprises the following steps:
the acquisition module is used for acquiring parameters of a second port correspondingly connected with each first port, wherein the parameters of the second port comprise screen numbers;
and the generating module is used for arranging the first ports according to the parameters of the second ports to generate a port aggregation sequence table, wherein the screen numbers of the second ports which are correspondingly connected with the adjacent first ports are different.
In a third aspect, an electronic device is provided, the device comprising a memory for storing computer instructions executable on the processor for port aggregation based on any one of the methods when executing the computer instructions.
In a fourth aspect, a computer readable storage medium is provided, having stored thereon a computer program, which when executed by a processor, implements the method of any of the claims.
The technical scheme provided by the embodiment of the specification can comprise the following beneficial effects:
according to the port aggregation method in the embodiment of the disclosure, the first ports and the second ports are connected in one-to-one correspondence, parameters of the second ports connected with each first port are obtained, and each first port is arranged according to the parameters of each second port, so that a port aggregation sequence table is generated; because the parameters of the second ports comprise the screen numbers, the screen numbers of the second ports correspondingly connected with the adjacent first ports in the sequence table are different, namely, different screen plates are connected with each first port of the interface board at intervals, and then when data transmission is carried out between the interface board and the screen plates, data flow can be split to different screen plates, so that load balancing is realized. When data transmission is performed between two interface boards through a plurality of mesh boards, after the first ports of the source interface boards are aggregated according to the method in the embodiment, data can be transmitted to the destination interface boards through all the mesh boards, and all the first ports of the destination interface boards can receive data traffic, so that load balancing of data transmission between the interface boards is realized, traffic on each first port of the source interface boards and each first port of the destination interface boards cannot exceed load capacity of the source interface boards and the first ports of the destination interface boards, and packet loss is avoided.
Drawings
FIG. 1 is a flow diagram of a port aggregation method shown in an exemplary embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating the connection of an interface board to a mesh board according to an exemplary embodiment of the present disclosure;
FIG. 3 is a flow diagram illustrating a method of arranging first ports according to another exemplary embodiment of the present disclosure;
FIG. 4 is a flow diagram of a port aggregation method shown in another exemplary embodiment of the present disclosure;
FIG. 5 is a flow diagram of a port aggregation method shown in yet another exemplary embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a port coalescing apparatus shown in an exemplary embodiment of the present disclosure;
fig. 7 is a hardware schematic of an apparatus shown in an exemplary embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
A Switch (Switch) is a network device for forwarding electrical (optical) signals, which can provide a single shared electrical signal path for any two network nodes accessing the Switch, and is most commonly an ethernet Switch, and other common switches include a voice over telephone Switch, a fiber optic Switch, and the like. The switch is internally provided with a plurality of ports, such as a panel port, an internal port on an interface board, an internal port on a screen board and the like; in view of the working property of the switch, each port needs to pass huge traffic, and compared with the panel port, the traffic pressure of the internal port is particularly high, so that the internal traffic of the switch easily exceeds the load capacity of the internal port, and the packet is lost.
Based on this, referring to fig. 1, the disclosure provides a port aggregation method, configured to generate a sequence table when an interface board performs port aggregation, where the interface board has a plurality of first ports, and each first port is correspondingly connected to a second port of a mesh board; specifically, the method includes step S101 and step S102.
In one example, the first port is an internal port of an interface board and the second port is an internal port of a mesh board. Specifically, the interface board and the screen board are board cards of the switch, wherein the interface board is provided with a panel port and an internal port; the mesh plate has only an internal port, which provides a flow path between the interface boards, and the correspondence between the internal port of the interface board and the internal port of the mesh plate is fixed, which is determined by the hardware wiring. The panel port is a port for directly connecting the switch with other devices through a network cable, and the internal port is a port for connecting all the boards and cards in the switch.
In one example, the interface board has six, eight, or ten first ports.
In one example, the interface boards are respectively connected to two net boards.
In step S101, parameters of a second port corresponding to the connection of each first port are obtained, where the parameters of the second port include a screen number.
In this step, the second port to which the first port is correspondingly connected is fixed and unique, and is determined by the hardware wiring in the previous production process, so that the parameters of the corresponding second port can be obtained, and further, the screen plate to which the second port belongs is obtained through the screen plate number in the parameters, thereby providing a basis for arranging the first ports according to the networked plates in the subsequent step.
In one example, referring to fig. 2, a first interface board 201 and a second interface board 202 in the switch implement electrical connection, data transmission and traffic exchange through two mesh boards (i.e., a first mesh board 203 and a second mesh board 204) therebetween. Taking the first interface board 201 as an example, in a direction from top to bottom in the drawing, four internal ports (i.e., a first port) of the first interface board are a first internal port 2011, a second internal port 2012, a third internal port 2013 and a fourth internal port 2014, wherein network card numbers in parameters of the second port to which the first internal port 2011 is correspondingly connected are first network boards (or represented by a and identified), network card numbers in parameters of the second port to which the second internal port 2012 is correspondingly connected are second network boards (or represented by B and identified), network card numbers in parameters of the second port to which the third internal port 2013 is correspondingly connected are first network boards (or represented by a and identified), and network card numbers in parameters of the second port to which the fourth internal port 2014 is correspondingly connected are second network boards (or represented by B and identified); taking the second interface board 202 as an example, in a direction from top to bottom in the drawing, four internal ports (i.e., a first port) of the second interface board are a fifth internal port 2021, a sixth internal port 2022, a seventh internal port 2023 and an eighth internal port 2024, wherein the network card number in the parameter of the second port corresponding to the fifth internal port 2021 is a first network board (or denoted by a and identified), the network card number in the parameter of the second port corresponding to the sixth internal port 2022 is a first network board (or denoted by a and identified), the network card number in the parameter of the second port corresponding to the seventh internal port 2023 is a second network board (or denoted by B and identified), and the network card number in the parameter of the second port corresponding to the eighth internal port 2024 is a second network board (or denoted by B and identified). As can be seen from the connection conditions of the first interface board 201 and the second interface board 202 with the two mesh boards, the corresponding connection relationship between the first port and the second port determines the parameters of the second port connected with the first port, and the parameters are fixed after the switch leaves the factory and cannot be changed; therefore, if it is desired to reasonably allocate the flow allocation proportion between the first ports, the flow allocation proportion can only be realized by adjusting the port aggregation sequence table, and cannot be realized by changing hardware.
Referring to fig. 1, in step S102, each first port is arranged according to the parameters of each second port to generate a port aggregation sequence table, where the mesh plate numbers of the second ports corresponding to and connected to the adjacent first ports are different.
In this step, after arranging the first ports, the flow can be distributed to the mesh plates. Because the phenomenon that the flow is concentrated on part of the first ports occurs during flow distribution and is generally concentrated on the continuous part of the first ports in the port aggregation sequence table, for example, concentrated on the first half of the first ports in the sequence table, at this time, because different net plates are connected to adjacent first ports, the flow can be distributed to different net plates through part of the first ports, so that the phenomenon that the flow is concentrated on one net plate to cause data overload is avoided, and load balancing is realized.
In one example, please continue to refer to fig. 2, the four internal ports in the first interface board 201 are arranged in the following order when port aggregation is performed: the first internal port 2011, the second internal port 2012, the third internal port 2013, and the fourth internal port 2014, such that the first interface board 201 alternately connects the first net plate 203 and the second net plate 204 through the four internal ports in the above order. When the first interface board 201 transmits data to the second interface board 202 through the two mesh boards, if the data traffic is distributed to the four internal ports of the first interface board 201, the data traffic is further transmitted to the four internal ports of the second interface board 202 through the two mesh boards; if the data traffic is distributed to the first internal port 2011 and the second internal port 2012 of the first interface board 201, but the third internal port 2013 and the fourth internal port 2014 are not distributed to the traffic, the first internal port 2011 can transmit the data traffic to the fifth internal port 2021 and the sixth internal port 2022 of the second interface board 202 through the first mesh board 203, and the second internal port 2012 can transmit the data traffic to the seventh internal port 2023 and the eighth internal port 2024 of the second interface board 202 through the second mesh board 204, so that both mesh boards can be guaranteed to distribute the data traffic, and all the internal ports of the destination interface board (i.e. the second interface board 202) can be guaranteed to receive the data traffic, thereby avoiding overload and packet loss caused by the concentration of the data traffic in the individual internal ports.
In one example, please continue to refer to fig. 2, the four internal ports of the second interface board 202 are arranged in the following order when port aggregation is performed: the fifth internal port 2021, the seventh internal port 2023, the sixth internal port 2022, and the eighth internal port 2024 are so that the second interface board 202 alternately connects the first screen 203 and the second screen 204 through the four internal ports in the order described above. When the second interface board 202 transmits data to the first interface board 201 through the two mesh boards, if the data traffic is distributed to the four internal ports of the second interface board 202, the data traffic is further transmitted to the four internal ports of the first interface board 201 through the two mesh boards; if the data traffic is distributed to the fifth internal port 2021 and the seventh internal port 2023 of the second interface board 202, and the sixth internal port 2022 and the eighth internal port 2024 are not distributed to the traffic, the fifth internal port 2021 may transmit the data traffic to the first internal port 2011 and the third internal port 2013 of the first interface board 201 through the first mesh board 203, and the seventh internal port 2023 may transmit the data traffic to the second internal port 2012 and the fourth internal port 2014 of the first interface board 201 through the second mesh board 204, so that it is ensured that both mesh boards can distribute the data traffic, and further it is ensured that all the internal ports of the destination interface board (i.e. the first interface board 201) can receive the data traffic, and overload and packet loss caused by concentration of the data traffic in the respective internal ports are avoided.
In the above two examples, if the first ports are not arranged in the manner of step S102, the data traffic is concentrated on the individual mesh board and on the individual first ports of the destination interface board, which further causes overload and packet loss. Taking the example that the first interface board 201 transmits the data traffic to the second interface board 202, if the four internal ports of the first interface board 201 are arranged in the order of the first internal port 2011, the third internal port 2013, the second internal port 2012 and the fourth internal port 2014, when the traffic is concentrated on the first internal port 2011 and the third internal port 2013 which are continuous in the sequence table, the traffic can only be transmitted to the fifth internal port 2021 and the sixth internal port 2022 of the second interface board 202 through the first screen 203, and the traffic is easy to exceed the compound of the first screen 203 or exceed the load of the fifth internal port 2021 and the sixth internal port 2022, so that packet loss is caused; the same principle is adopted for the second interface board 202 to transmit data traffic to the first interface board 201, and the details are not repeated here.
According to the port aggregation method provided by the embodiment, when data transmission is carried out between the interface board and the network board, data flow can be split to different network boards, and load balancing is achieved; when data transmission is performed between two interface boards through a plurality of mesh boards, after the first ports of the source interface boards are aggregated according to the method in the embodiment, data can be transmitted to the destination interface boards through all the mesh boards, and all the first ports of the destination interface boards can receive data traffic, so that load balancing of data transmission between the interface boards is realized, traffic on each first port of the source interface boards and each first port of the destination interface boards cannot exceed load capacity of the source interface boards and the first ports of the destination interface boards, and packet loss is avoided.
Referring to fig. 3, some embodiments of the disclosure exemplarily illustrate a method for arranging first ports, that is, arranging each first port according to parameters of each second port, which specifically includes step S301 and step S302.
In step S301, the first ports are grouped according to the parameters of the second ports, so as to generate at least two groups of first ports, where the mesh numbers of the second ports connected to the first ports in each group are the same.
In this step, the grouping is performed by the net boards, each net board establishes a first port group, and then all the first ports connected to the net board are allocated into the corresponding group.
In one example, when the first ports are allocated to the corresponding groups, the first ports need to be ordered in the groups, and because the parameters of the second ports also include port numbers, the first ports are arranged according to the port numbers of the corresponding second ports when ordered in the groups. For example, when grouping the internal ports of the first interface board 201 as shown in fig. 2, since the first interface board 201 connects two net boards, namely, the first net board 203 and the second net board 204, a first group and a second group are established, then the first internal port 2011 and the third internal port 2013 are allocated into the first group, and the second internal port 2012 and the fourth internal port 2014 are allocated into the second group; then, the two internal ports in the first group are arranged according to the first internal port 2011 and the third internal port 2013, and the two internal ports in the second group are arranged according to the second internal port 2012 and the fourth internal port 2014.
In step S302, one first port in each group is sequentially fetched according to the order of each group, put into the arrangement sequence, and circulated for a plurality of times until all the first ports are fetched.
In this step, after one first port in each group is sequentially taken out, a first sub-sequence is formed, and after one first port in each group is taken out again, a second sub-sequence is formed until all the first ports in each group are taken out, namely, the formation of the whole sequence is completed. Since all the first ports of the interface board are distributed as evenly as possible to the plurality of net boards connected thereto in the process of the hardware wiring, when the number of the first ports is an integer multiple of the number of all the net boards, the number of the first ports in each group formed in step S301 is the same, and when the number of the first ports is not an integer multiple of the number of all the net boards, a part of the groups formed in step S301 are large groups and the other part are small groups, wherein the number of the first ports in the large groups is greater than the number of the first ports in the small groups by 1, and therefore, in the above two cases, the net boards connected to adjacent first ports in the sequence formed in the manner of this step are different.
In one example, when a first port is removed from each group, a first port corresponding to a second port having the forefront port number in each group is removed, placed in a sequence, for example, when an internal port is removed from a first group and a second group formed by internal ports of the first interface board 201 as shown in fig. 2, a first internal port 2011 is removed from the first group, a second internal port 2012 is removed from the second group, and then the above operation is repeated for a second round, a third internal port 2013 is removed from the first group, and a fourth internal port 2014 is removed from the second group, thereby forming a sequence of the first internal port 2011, the second internal port 2012, the third internal port 2013, and the fourth internal port 2014.
Referring to fig. 4, there is shown a port aggregation method according to another embodiment of the present disclosure, specifically, steps S402 to S403 are identical to steps S101 and S102 shown in fig. 1, except that before step S402, step S401 is further included: and respectively storing parameters of the second ports correspondingly connected with the first ports according to the connection relation between the first ports and the second ports.
Because the corresponding connection relation between the first port and the second port is determined and cannot be changed in the process of hardware wiring before the switch leaves the factory, the corresponding connection relation is stored into a memory or a memory card of the switch after the hardware wiring is completed, and is acquired and used during port aggregation, so that the efficiency and the accuracy of port aggregation are improved.
Referring to fig. 5, a port aggregation method provided by further embodiments of the present disclosure is shown, in which step S501 to step S502 are identical to step S101 and step S102 shown in fig. 1, except that after step S502, step S503 is further included: and writing the port aggregation sequence list into the exchange chip.
The generated port aggregation sequence table is written into the exchange chip to replace the inherent internal port list of the interface board which is directly brushed down, and the flow can be split according to the sequence table during port aggregation, so that the flow can be distributed to different network boards under various conditions, load balancing is realized, and overload and packet loss are prevented.
In a second aspect, referring to fig. 6, a port aggregation apparatus is provided, configured to generate a sequence table when an interface board performs port aggregation, where the interface board has a plurality of first ports, and each first port is correspondingly connected to a second port of a mesh board; the method comprises the following steps:
the obtaining module 601 is configured to obtain parameters of a second port corresponding to each first port, where the parameters of the second port include a screen number;
and the generating module 602 is configured to arrange each first port according to the parameters of each second port, and generate a port aggregation sequence table, where the mesh plate numbers of the second ports corresponding to and connected with the adjacent first ports are different.
In a third aspect, referring to fig. 7, an electronic device is provided, the device including a memory for storing computer instructions executable on the processor, and a processor for port aggregation based on any one of the methods when executing the computer instructions.
In a fourth aspect, a computer readable storage medium is provided, having stored thereon a computer program, which when executed by a processor, implements the method of any of the claims.
Embodiments of the subject matter and the functional operations described in this specification can be implemented in: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and structural equivalents thereof, or a combination of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions may be encoded on a manually-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode and transmit information to suitable receiver apparatus for execution by data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.
The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
Computers suitable for executing computer programs include, for example, general purpose and/or special purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read only memory and/or a random access memory. The essential elements of a computer include a central processing unit for carrying out or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks, etc. However, a computer does not have to have such a device. Furthermore, the computer may be embedded in another device, such as a mobile phone, a Personal Digital Assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device such as a Universal Serial Bus (USB) flash drive, to name a few.
Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disk or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features of specific embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. On the other hand, the various features described in the individual embodiments may also be implemented separately in the various embodiments or in any suitable subcombination. Furthermore, although features may be acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Furthermore, the processes depicted in the accompanying drawings are not necessarily required to be in the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the disclosure, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present disclosure.
Claims (9)
1. The port aggregation method is characterized by being used for generating a sequence table when port aggregation is carried out on an interface board, wherein the interface board is provided with a plurality of first ports, and each first port is correspondingly connected with a second port of a screen; the method comprises the following steps:
acquiring parameters of a second port correspondingly connected with each first port, wherein the parameters of the second port comprise a screen plate number;
arranging each first port according to the parameters of each second port to generate a port aggregation sequence table, wherein the screen numbers of the second ports which are correspondingly connected with the adjacent first ports are different;
wherein, the arranging each first port according to the parameters of each second port includes: grouping the first ports according to the parameters of the second ports to generate at least two groups of first ports, wherein the mesh plate numbers of the second ports connected with the first ports in each group are the same; and sequentially taking out one first port in each group according to the sequence of each group, putting the first ports into the arrangement sequence, and cycling for a plurality of times until all the first ports are taken out.
2. The port aggregation method of claim 1, wherein the parameters of the second port further comprise a port number;
the sequentially taking out the first ports in each group and putting the first ports into the arrangement sequence comprises the following steps:
and sequentially determining a second port with the forefront port number in each group, taking out a first port corresponding to the determined second port, and putting the first port into the arrangement sequence.
3. The port aggregation method of claim 1, further comprising:
and respectively storing parameters of the second ports correspondingly connected with the first ports according to the connection relation between the first ports and the second ports.
4. The port aggregation method of claim 1, further comprising:
and writing the port aggregation sequence list into the exchange chip.
5. The port aggregation method of claim 1, wherein the interface board has six, eight or ten first ports.
6. The port aggregation method of claim 1, wherein the interface board connects two mesh boards.
7. The port aggregation device is characterized by being used for generating a sequence table when port aggregation is carried out on an interface board, wherein the interface board is provided with a plurality of first ports, and each first port is correspondingly connected with a second port of a screen; comprising the following steps:
the acquisition module is used for acquiring parameters of a second port correspondingly connected with each first port, wherein the parameters of the second port comprise screen numbers;
the generating module is used for arranging the first ports according to the parameters of the second ports to generate a port aggregation sequence table, wherein the screen numbers of the second ports which are correspondingly connected with the adjacent first ports are different;
wherein, the arranging each first port according to the parameters of each second port includes: grouping the first ports according to the parameters of the second ports to generate at least two groups of first ports, wherein the mesh plate numbers of the second ports connected with the first ports in each group are the same; and sequentially taking out one first port in each group according to the sequence of each group, putting the first ports into the arrangement sequence, and cycling for a plurality of times until all the first ports are taken out.
8. An electronic device comprising a memory, a processor for storing computer instructions executable on the processor for port aggregation based on the method of any one of claims 1 to 6 when the computer instructions are executed.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of any one of claims 1 to 6.
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