CN111404540B - Class AB super source follower circuit and differential class AB super source follower circuit - Google Patents
Class AB super source follower circuit and differential class AB super source follower circuit Download PDFInfo
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- CN111404540B CN111404540B CN202010256317.7A CN202010256317A CN111404540B CN 111404540 B CN111404540 B CN 111404540B CN 202010256317 A CN202010256317 A CN 202010256317A CN 111404540 B CN111404540 B CN 111404540B
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Abstract
The invention discloses an AB super source follower circuit and a differential AB super source follower circuit, wherein the AB super source follower circuit comprises an input circuit, an output circuit, a folding circuit and a bias circuit, two ends of the input circuit are respectively connected with a first end of the folding circuit and a first end of the output circuit, the other end of the folding circuit and one end of the bias circuit are simultaneously connected with the other end of the output circuit, the input end of the input circuit is the input end of the AB super source follower circuit, and the first end of the output circuit is the output end of the AB super source follower circuit; the bias circuit is used for providing bias setting for the output circuit, and the folding circuit is used for expanding the swing amplitude of the control end of the output circuit. And forming a differential AB super source follower circuit based on the AB super source follower circuit. The bias circuit is used for setting bias for the output circuit, so that the completeness of an output signal of the follower is ensured, and the full-band following is realized; the folding circuit and the bias circuit are combined, so that negative feedback to the follower circuit is realized, and output is stabilized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an AB super source follower circuit and a differential AB super source follower circuit.
Background
In the technical field of semiconductor design, a very commonly used circuit is adopted in a follower circuit, generally, a source follower circuit is adopted, the source follower circuit has high input impedance and low output impedance and is usually used as a buffer stage of an input signal, the basic source follower circuit comprises a MOS tube and a current source circuit, but the output impedance of the basic source follower circuit is still high, the requirement is not met, in order to reduce the output impedance, output and absorb large current, the basic source follower circuit is improved, an AB super source follower circuit is formed, as shown in fig. 1, a mirror current source circuit and a capacitive coupling circuit are overlapped on the basic source follower circuit, the following of AB alternating current input is realized, a mirror end third MOS tube M3 of a mirror current source M3 and a mirror end third MOS tube M4 is connected to the source electrode of the input MOS tube M1, the drain electrode of the MOS tube is connected with the grid electrode of the current source I2 and one end of a coupling capacitor C1, the output MOS tube M2 realizes small output impedance, the other end of the coupling capacitor C1 is connected with the grid electrode of the third MOS tube M3, and the mirror end third MOS tube M4 is connected with the grid electrode of the fourth MOS tube through a resistor R1. The drain electrode of the output MOS tube M2 is used as the output of the super source follower circuit.
The specific working principle is as follows: in steady state, current source I1 is mirrored to the source of M1 by a mirrored current source. When the input signal decreases, the gate voltage of M2 increases, and the NMOS transistor M2 sinks current from the load. At the same time, the M2 gate voltage is ac coupled to the M3 gate through capacitor C1, raising the M3 gate voltage, tending to turn off PMOS transistor M3. When the input signal increases, the M2 gate will decrease while the M2 gate voltage is ac coupled to the M3 gate through capacitor C1, decreasing the M3 gate voltage, tending to turn on PMOS transistor M3. In this case, more load current than the constant current source I1 can be obtained. The large resistor R1 is used to enable ac coupling to temporarily pull down the gate of M3.
Although such AB-type super-source tracking circuits can achieve low output impedance, output and sink large currents, due to the use of the capacitor C1 for ac coupling, the circuit cannot operate when the frequency of the input signal is low or dc.
Therefore, designing a follower circuit that is not affected by the input frequency is a problem to be solved.
Disclosure of Invention
The invention aims to provide an AB super-source follower circuit and a differential AB super-source follower circuit, wherein the voltage swing of the control end of an output stage is expanded by adding a folding circuit on the basis of a basic source follower circuit, and the output impedance is reduced, the output current and current absorption capacity are increased and the output power is improved by a bias circuit and an output stage of the AB. The setting of the DC coupling bias circuit realizes the following of the input signal with any frequency and the DC signal input, and expands the application range of the circuit.
The above object of the present invention is achieved by the following technical solutions:
the input end of the input circuit is the input end of the AB super source follower circuit, and the first end of the output circuit is the output end of the AB super source follower circuit; the bias circuit is used for providing bias setting for the output circuit, and the folding circuit is used for expanding the swing of the control end of the output circuit.
The invention is further provided with: the second end of the folding circuit and the second end of the output circuit are connected with the first end of the biasing circuit, and the third end of the folding circuit and the third end of the output circuit are connected with the second end of the biasing circuit.
The invention is further provided with: the folding circuit comprises a biasing circuit and a folding sub-circuit which are connected in sequence, wherein the biasing circuit is used for providing bias voltage for the folding sub-circuit, and the folding circuit is used for expanding the swing amplitude of the control end of the output circuit.
The invention is further provided with: the folding sub-circuit comprises a second current source circuit and a fourth N-type transistor and a fifth N-type transistor which are in folding cascade connection, wherein grid electrodes or base electrodes of the fourth N-type transistor and the fifth N-type transistor are respectively connected with two output ends of the biasing circuit, a source electrode or an emitting electrode of the fourth N-type transistor is connected with a drain electrode or a collecting electrode of the fifth N-type transistor, and a source electrode or an emitting electrode of the fourth N-type transistor is a third end of the folding circuit and is connected with a third end of the output circuit; one end of the second current source circuit is connected with the positive end of the power supply, the other end of the second current source circuit is a second end of the folding circuit and is connected with the second end of the output circuit, and the source electrode or the emitter electrode of the fifth N-type transistor is connected with the power supply ground; the second current source circuit is used for providing bias current for the fourth N-type transistor and the fifth N-type transistor of the folding cascade connection.
The invention is further provided with: the input circuit comprises a first current source circuit and a first P-type transistor, one end of the first current source is connected with the positive end of the power supply, the other end of the first current source is connected with the source electrode or the emitting electrode of the first P-type transistor, the drain electrode or the collecting electrode of the first P-type transistor is connected with the folding circuit, and the grid electrode or the base electrode of the first P-type transistor is the input end of the input circuit.
The invention is further provided with: the bias circuit comprises a first bias voltage sub-circuit, a second bias voltage sub-circuit, a first bias voltage output sub-circuit and a second bias voltage output sub-circuit; the first bias voltage output sub-circuit is connected with the first output end of the second bias voltage output sub-circuit in parallel, and the output end of the first bias voltage sub-circuit is connected with the control end of the first bias voltage output sub-circuit.
The invention is further provided with: the first bias sub-circuit comprises a third current source circuit, eighth and ninth N-type transistors; the eighth and ninth N-type transistors are connected in series, one end of the third current source circuit is connected with the positive end of the power supply, the other end of the third current source circuit is connected with the drain electrode, the grid electrode or the base electrode and the collector electrode of the eighth N-type transistor, the control end of the first bias voltage output subcircuit, the source electrode or the emitter electrode of the eighth N-type transistor is connected with the drain electrode, the grid electrode or the base electrode and the collector electrode of the ninth N-type transistor, and the source electrode or the emitter electrode of the ninth N-type transistor is connected with the power supply ground; the second bias sub-circuit comprises a fourth current source circuit, tenth and eleventh P-type transistors; the tenth and eleventh P-type transistors are connected in series, the source electrode or emitter electrode of the tenth P-type transistor is connected with the positive end of the power supply, the drain electrode and the grid electrode or the base electrode and the collector electrode of the eleventh P-type transistor are connected with the source electrode or the emitter electrode of the eleventh P-type transistor, the drain electrode and the grid electrode or the base electrode and the collector electrode of the eleventh P-type transistor are connected with one end of the fourth current source circuit, and the other end of the fourth current source circuit is connected with the power supply ground.
The invention is further provided with: the second current source circuit of the folding circuit, the third current source circuit of the biasing circuit and the fourth current source circuit have the same output current value.
The above object of the present invention is achieved by the following technical solutions:
the differential AB super source follower circuit comprises a differential input circuit, a differential output circuit, a differential folding circuit and a bias circuit, wherein two input ends of the differential input circuit are used as positive and negative input ends of the differential AB super source follower circuit, and a first output end and a second output end of differential output are used as output ends of the differential AB super source follower circuit and are respectively connected with two output ends of the differential output circuit; the third output end and the fourth output end of the differential folding circuit are respectively connected with the two input ends of the differential folding circuit; the first output end and the second output end of the differential folding circuit are respectively connected with the first end and the second end of the differential output circuit, and are simultaneously connected with the first end and the second end of the bias circuit; the third and fourth output ends are respectively connected with the third and fourth ends of the differential output circuit, and are simultaneously connected with the third and fourth ends of the bias circuit.
The invention is further provided with: the differential input circuit comprises two input circuits which are arranged in a differential mode; the differential output circuit comprises two output circuits which are arranged in a differential mode; the differential folding circuit comprises two folding circuits which are arranged in a differential mode; the bias circuit comprises a first bias voltage sub-circuit, a second bias voltage sub-circuit, a first bias voltage output sub-circuit and a second bias voltage output sub-circuit; the first bias sub-circuit is connected in parallel with the second bias sub-circuit; the output end of the first bias voltage sub-circuit is connected with the control end of the first bias voltage output sub-circuit; the output end of the second bias voltage sub-circuit is connected with the control end of the second bias voltage output sub-circuit; the first output end and the second output end of the first bias voltage output sub-circuit are respectively connected with the first output end and the second output end of the second bias voltage output sub-circuit and are respectively used as the first output end and the second output end of the bias voltage circuit; the third output end and the fourth output end of the first bias voltage output subcircuit are respectively connected with the third output end and the fourth output end of the second bias voltage output subcircuit and are respectively used as the third output end and the fourth output end of the bias voltage circuit.
Compared with the prior art, the invention has the beneficial technical effects that:
1. according to the AB class super source follower circuit, the folding circuit is arranged at the output end of the input circuit, so that the swing amplitude of the control end of the output circuit is expanded, and the output amplitude range of the follower circuit is ensured;
2. further, the bias circuit is arranged to bias the output circuit, so that the follower circuit can follow all frequency input signals and direct current signals, the output circuit can completely follow the input signals, and the defect that the follower is limited by the signal frequency is overcome;
3. further, the bias circuit is arranged in a mode that a current source is connected with a transistor in series, and the bias current of the output stage is adjusted by adjusting the size of the current source;
4. further, the folding circuit and the bias circuit are combined, so that negative feedback of the follower circuit is realized, and the stability of the follower circuit is ensured;
5. the differential AB super source follower circuit adopts the same bias circuit to provide bias voltage for two differential parts.
Drawings
FIG. 1 is a schematic diagram of a prior AB class super source follower circuit;
FIG. 2 is a block schematic diagram of a class AB super source follower circuit configuration in accordance with one embodiment of the invention;
FIG. 3 is a schematic diagram of a class AB super source follower circuit configuration in accordance with one embodiment of the invention;
FIG. 4 is a block schematic diagram of a differential class AB super source follower circuit configuration in accordance with one embodiment of the invention;
fig. 5a and 5b are schematic diagrams of a differential class AB super source follower circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Detailed description of the preferred embodiments
The invention relates to an AB super source follower circuit, which is shown in figure 2, and comprises an input circuit, an output circuit, a folding circuit and a biasing circuit, wherein the input end of the input circuit is used for transmitting an input signal into the follower circuit; the second end of the input circuit is connected with the first end of the folding circuit, the second end of the output circuit is connected with the second end of the folding circuit and the first end of the biasing circuit, the third end of the output circuit is connected with the third end of the folding circuit and the second end of the biasing circuit, the biasing circuit is used for carrying out biasing setting on the output circuit, and the folding circuit is used for controlling swing amplitude of the output circuit.
Second embodiment
The AB super source follower circuit of the application, as shown in fig. 3, comprises an input circuit including a first current source I1 and a first transistor M1, wherein the gate of the first transistor M1 is used as the input end of the follower circuit, the input signal Vin is transmitted, the source of the input circuit is used as the second end of the input circuit, the output end of the first current source I1 and the output end Vout of the output circuit are connected, the drain of the input circuit is used as the third end of the input circuit, and the connection point of the fourth transistor M4 and the fifth transistor M5 connected in series of the folding circuit is connected. The first current source I1 is connected to the positive power supply terminal and provides a bias current for the first transistor M1.
The first transistor M1 is a P-type MOS transistor.
The folding circuit comprises a biasing circuit for providing bias voltages bias1, bias2 to the folding sub-circuit and a folding sub-circuit, the biasing circuit being a standard cascode current mirror biasing circuit, not shown. The folding sub-circuit comprises a second current source I2, a fourth transistor M4 and a fifth transistor M5, wherein the output end of the second current source I2 is used as the second end of the folding circuit and is connected with the second end of the output circuit, and the current of the second current source I2 provides current for the fourth transistor M4 and the fifth transistor M5 through the bias circuit; the grid electrode of the fourth transistor M4 is connected with the bias1 output end of the bias circuit, the source electrode of the fourth transistor M4 is used as the first end of the folding circuit, the drain electrode of the fourth transistor M5 is connected with the drain electrode of the fifth transistor M5, the drain electrode of the fourth transistor M4 is used as the third end of the folding circuit, and the third end of the output circuit is connected; the gate of the fifth transistor M5 is connected to the bias2 output terminal of the bias circuit, the drain thereof is connected to the source of the fourth transistor M4, and the source thereof is connected to the power ground. The second current source I2 is connected with the positive end of the power supply.
The fourth transistor M4 and the fifth transistor M5 are N-type MOS transistors.
The output circuit comprises a third transistor M3 and a second transistor M2, wherein the source electrode of the third transistor M3 is connected with the positive power supply, and the drain electrode of the third transistor M3 is connected with the drain electrode of the second transistor M2, the output end of the input circuit and the output end of the AB super source follower circuit; the source of the second transistor M2 is connected to power ground. The gates of the third transistor M3 and the second transistor M2 are respectively connected to the first end and the second end of the bias circuit.
The third transistor M3 is a P-type MOS transistor, and the second transistor M2 is an N-type MOS transistor.
The bias circuit comprises a first bias sub-circuit, a second bias sub-circuit, a first bias output sub-circuit and a second bias output sub-circuit.
The first bias subcircuit comprises a third current source I3, an eighth transistor M8 and a ninth transistor M9 connected in series; one end of the third current source I3 is connected to the positive power supply end, the output end thereof is connected to the drain and gate of the eighth transistor M8 and the control end of the first bias output sub-circuit, the source of the eighth transistor M8 is connected to the drain and gate of the ninth transistor M9, and the source of the ninth transistor M9 is connected to the power supply ground.
The eighth transistor M8 and the ninth transistor M9 are N-type MOS transistors.
The first bias output sub-circuit comprises a sixth transistor M6, wherein the grid electrode of the sixth transistor M6 is connected with the output end of the third current source I3, the drain electrode of the eighth transistor M8 and the grid electrode, the drain electrode of the sixth transistor is used as the first end of the bias circuit, the output end of the second current source I2 and the second end of the output circuit, the source electrode of the sixth transistor is used as the second end of the bias circuit, and the third end of the folding sub-circuit and the third end of the output circuit are connected.
The sixth transistor M6 is an N-type MOS transistor.
The second bias subcircuit includes a fourth current source I4, a tenth transistor M10, an eleventh transistor M11 connected in series; one end of the fourth current source I4 is connected to the power ground, the input end thereof is connected to the drain and gate of the eleventh transistor M11, the control end of the second bias output sub-circuit, the drain and gate of the tenth transistor M10 are connected to the source of the eleventh transistor M11, the source thereof is connected to the current positive end, and the drain of the eleventh transistor M11 serves as the output end of the second bias output sub-circuit and is connected to the first bias output sub-circuit.
The tenth transistor M10 and the eleventh transistor M11 are P-type MOS transistors.
The second bias output sub-circuit comprises a seventh transistor M7, wherein the grid electrode of the seventh transistor M7 is connected with the input end of the third current source I4, the drain electrode and the grid electrode of the eleventh transistor M11, the source electrode of the seventh transistor M is used as the second end of the bias circuit, the output end of the second current source I2 and the second end of the output circuit are connected, the output end of the seventh transistor M is used as the second end of the bias circuit, and the third end of the folding sub-circuit and the third end of the output circuit are connected.
The seventh transistor M6 is an N-type MOS transistor.
The first bias voltage sub-circuit is connected with the second bias voltage sub-circuit in parallel, and the input end and the output end of the first bias voltage output sub-circuit are respectively connected with the input end and the output end of the second bias voltage output sub-circuit.
The working principle of the AB super source follower circuit is as follows:
the current passing through the transistor M10/M11 flows into the fourth current source I4, the bias voltage is provided for the grid electrode of the transistor M7, and the current of the fourth current source I4 is adjusted, so that the current flowing through the transistor M3 can be controlled.
Similarly, the current of the third current source I3 flows into the transistor M8/M9, the bias voltage is supplied to the gate of the transistor M6, and the current of the third current source I3 is adjusted, so that the current flowing through the transistor M2 can be controlled.
The sizes of the transistors M2, M3, M6, M7, M8, M9, M10, M11 are set appropriately, and the quiescent current setting for the transistors M2, M3 can be realized.
The control of the gate voltage of the transistor M3/M2 is achieved by current control of the transistors M6, M7. The on-state of the transistor M3 determines the magnitude of the output current, and the on-state of the transistor M2 determines the magnitude of the sink current.
When the input signal Vin decreases, the current of the transistor M1 tends to increase, thereby increasing the voltage at the source of the transistor M4, resulting in a decrease in the current flowing through the transistor M4, an increase in the voltage at the gate of the transistor M2, an on-state of the transistor M2, an off-state of the transistor M3, an increase in the current flowing through the transistor M2, and a larger current absorption, which in turn decreases the increase in the current of the transistor M1, thereby achieving a stabilization of the current flowing through the transistor M1.
When the input signal Vin increases, M3 tends to be on, M2 tends to be off, the current flowing through M3 increases, a larger current is output, and stabilization of the current flowing through the transistor M1 is achieved.
The output impedance of the circuit is at the same level as that of the existing super source follower circuit, the NMOS transistor M2 can absorb large current from the load, and the PMOS transistor M3 can provide large current to the load. Because of the lack of ac coupling, the circuit is capable of operating on both ac and dc input signals. A large bias current is not required, and a large current can be output to the load. And the bias circuit can be shared by multiple super source follower circuits.
In another embodiment of the present application, a compensation circuit for the transistors M2/M3 is also included for stabilization of the feedback loop.
In another embodiment of the present application, the second current source I2, the third current source I3, and the fourth current source I4 have equal output current values.
Detailed description of the preferred embodiments
The differential AB super source follower circuit comprises a first input circuit, a second input circuit, a first output circuit, a first folding circuit, a second folding circuit and a bias circuit, wherein the differential AB super source follower circuit comprises a differential input circuit formed by the first input circuit and the second input circuit, and the input ends of the differential AB super source follower circuit are respectively used as positive and negative input ends of an input signal; the first output circuit and the first output circuit form a differential output circuit, and the output ends of the differential output circuit are respectively used as positive and negative output ends of an output signal; the control ends of the differential folding circuit are respectively connected with the second ends of the first input circuit and the second input circuit; the second end and the third end of the first folding circuit are connected with the second end and the third end of the first output circuit, and are simultaneously connected with the first end and the second end of the bias circuit; the second end and the third end of the second folding circuit are connected with the second end and the third end of the second output circuit, and are simultaneously connected with the third end and the fourth end of the bias circuit.
Detailed description of the preferred embodiments
The differential AB super source follower circuit comprises a differential input circuit, a differential output circuit, a differential folding circuit and a bias circuit, as shown in figures 5a and 5 b.
The first input circuit comprises a 1A current source I1A and a 1A transistor M1A; the second input circuit comprises a 1B current source I1B and a 1B transistor M1B; the first input circuit and the second input circuit form a differential input circuit, and the first input circuit structure and the second input circuit structure are the same as those of the second embodiment.
The first output circuit comprises a 3A-th transistor M3A and a 2A-th transistor M2A, and the second output circuit comprises a 3B-th transistor M3B and a 2B-th transistor M2B; the first output circuit and the second output circuit form a differential output circuit, and the structures of the first output circuit and the second output circuit are the same as those of the second embodiment.
The first folding circuit comprises a 2A current source I2A, a 4A transistor M4A and a 5A transistor M5A; the second folding circuit comprises a 2B current source I2B, a 4B transistor M4B and a 5B transistor M5B; the first folding circuit and the second folding circuit form a differential folding circuit, and the structures of the first folding circuit and the second folding circuit are the same as those of the folding circuit in the second embodiment.
The bias circuit comprises a first bias sub-circuit, a second bias sub-circuit, a first bias output sub-circuit and a second bias output sub-circuit.
The output end of the first bias voltage sub-circuit is connected with the input end of the first bias voltage output sub-circuit, and the output end of the second bias voltage sub-circuit is connected with the input end of the second bias voltage output sub-circuit.
The first bias subcircuit includes a third current source, an eighth transistor M8, a ninth transistor M9; the second bias subcircuit includes a fourth current source, a tenth transistor M10, an eleventh transistor M11; the first bias sub-circuit and the second bias sub-circuit have the same structures as the first bias sub-circuit and the second bias sub-circuit in the second embodiment, respectively.
The first bias output sub-circuit comprises a 6A-th transistor M6A and a 6B-th transistor M6B, and the gates of the 6A-th transistor M6A and the 6B-th transistor M6B are connected together to serve as an input end of the first bias output sub-circuit.
The second bias output sub-circuit includes a 7A-th transistor M7A and a 7B-th transistor M7B, and the gates of the 7A-th transistor M7A and the 7B-th transistor M7B are connected together and serve as the input end of the second bias output sub-circuit.
The drain and the source of the 6A-th transistor M6A are respectively connected with the source and the drain of the 7A-th transistor M7A, respectively serve as a first end and a second end of the bias circuit, and are respectively connected with corresponding ends of the first output circuit and the first folding circuit.
The drain and the source of the 6B-th transistor M6B are respectively connected with the source and the drain of the 7B-th transistor M7B, respectively serve as third and fourth ends of the bias circuit, and are respectively connected with corresponding ends of the second output circuit and the second folding circuit.
The 6A-th transistor M6A and the 6B-th transistor M6B are N-type transistors, and the 7A-th transistor M7A and the 7B-th transistor M7B are P-type transistors.
The circuit transmits input signals from two input ends of a first input circuit and a second input circuit, and transmits output signals from two output ends of a first output circuit and a second output circuit, and inputs and outputs the signals in a differential mode.
In the specific embodiment of the application, the MOS transistor is taken as an example for illustration, and the structure is also suitable for implementation by using a triode. The N-type MOS transistor corresponds to the N-type triode, and the P-type MOS transistor corresponds to the P-type triode.
The embodiments of the present invention are all preferred embodiments of the present invention, and are not intended to limit the scope of the present invention in this way, therefore: all equivalent changes in structure, shape and principle of the invention should be covered in the scope of protection of the invention.
Claims (9)
1. A class AB super source follower circuit is characterized in that: the input end of the input circuit is the input end of the AB super source follower circuit, and the first end of the output circuit is the output end of the AB super source follower circuit; the bias circuit is used for providing bias voltage for the output circuit, so that the follower circuit can follow all frequency input signals and direct current signals, and the folding circuit is used for expanding the swing amplitude of the control end of the output circuit.
2. The class AB super source follower circuit of claim 1, wherein: the folding circuit comprises a biasing circuit and a folding sub-circuit which are connected in sequence, wherein the biasing circuit is used for providing bias voltage for the folding sub-circuit, and the folding sub-circuit expands the swing amplitude of the control end of the output circuit.
3. The class AB super source follower circuit of claim 2, wherein: the folding sub-circuit comprises a second current source circuit and a fourth N-type transistor and a fifth N-type transistor which are in folding cascade connection, wherein grid electrodes or base electrodes of the fourth N-type transistor and the fifth N-type transistor are respectively connected with two output ends of the biasing circuit, a source electrode or an emitting electrode of the fourth N-type transistor is connected with a drain electrode or a collecting electrode of the fifth N-type transistor, and a source electrode or an emitting electrode of the fourth N-type transistor is a third end of the folding circuit and is connected with a third end of the output circuit; one end of the second current source circuit is connected with the positive end of the power supply, the other end of the second current source circuit is a second end of the folding circuit and is connected with the second end of the output circuit, and the source electrode or the emitter electrode of the fifth N-type transistor is connected with the power supply ground; the second current source circuit is used for providing bias current for the fourth N-type transistor and the fifth N-type transistor of the folding cascade connection.
4. The class AB super source follower circuit of claim 1, wherein: the input circuit comprises a first current source circuit and a first P-type transistor, one end of the first current source is connected with the positive end of the power supply, the other end of the first current source is connected with the source electrode or the emitting electrode of the first P-type transistor, the drain electrode or the collecting electrode of the first P-type transistor is connected with the first end of the folding circuit, and the grid electrode or the base electrode of the first P-type transistor is the input end of the input circuit.
5. The class AB super source follower circuit of claim 1, wherein: the bias circuit comprises a first bias voltage sub-circuit, a second bias voltage sub-circuit, a first bias voltage output sub-circuit and a second bias voltage output sub-circuit; the first bias voltage output sub-circuit is connected with the first output end of the second bias voltage output sub-circuit in parallel, and the output end of the first bias voltage sub-circuit is connected with the control end of the first bias voltage output sub-circuit.
6. The class AB super source follower circuit of claim 5, wherein: the first bias sub-circuit comprises a third current source circuit, eighth and ninth N-type transistors; the eighth and ninth N-type transistors are connected in series, one end of the third current source circuit is connected with the positive end of the power supply, the other end of the third current source circuit is connected with the drain electrode, the grid electrode or the base electrode and the collector electrode of the eighth N-type transistor, the control end of the first bias voltage output subcircuit, the source electrode or the emitter electrode of the eighth N-type transistor is connected with the drain electrode, the grid electrode or the base electrode and the collector electrode of the ninth N-type transistor, and the source electrode or the emitter electrode of the ninth N-type transistor is connected with the power supply ground; the second bias sub-circuit comprises a fourth current source circuit, tenth and eleventh P-type transistors; the tenth and eleventh P-type transistors are connected in series, the source electrode or emitter electrode of the tenth P-type transistor is connected with the positive end of the power supply, the drain electrode and the grid electrode or the base electrode and the collector electrode of the eleventh P-type transistor are connected with the source electrode or the emitter electrode of the eleventh P-type transistor, the drain electrode and the grid electrode or the base electrode and the collector electrode of the eleventh P-type transistor are connected with one end of the fourth current source circuit, and the other end of the fourth current source circuit is connected with the power supply ground.
7. The class AB super source follower circuit of claim 1, wherein: the second current source circuit of the folding circuit, the third current source circuit of the biasing circuit and the fourth current source circuit have the same output current value.
8. A differential AB super source follower circuit is characterized in that: the differential input circuit comprises a differential input circuit, a differential output circuit, a differential folding circuit and a bias circuit, wherein two input ends of the differential input circuit are used as positive and negative input ends of a differential AB super source follower circuit, and a first output end and a second output end of differential output are used as output ends of the differential AB super source follower circuit and are respectively connected with two output ends of the differential output circuit; the third output end and the fourth output end of the differential folding circuit are respectively connected with the two input ends of the differential folding circuit; the first output end and the second output end of the differential folding circuit are respectively connected with the first end and the second end of the differential output circuit, and are simultaneously connected with the first end and the second end of the bias circuit; the third and fourth output ends are respectively connected with the third and fourth ends of the differential output circuit, and are simultaneously connected with the third and fourth ends of the bias circuit, and the bias circuit is used for providing bias voltage for the output circuit, so that the follower circuit can follow all frequency input signals and direct current signals.
9. The class AB super source follower circuit of claim 8, wherein: the differential input circuit comprises two input circuits which are arranged in a differential mode; the differential output circuit comprises two output circuits which are arranged in a differential mode; the differential folding circuit comprises two folding circuits which are arranged in a differential mode; the bias circuit comprises a first bias voltage sub-circuit, a second bias voltage sub-circuit, a first bias voltage output sub-circuit and a second bias voltage output sub-circuit; the first bias sub-circuit is connected in parallel with the second bias sub-circuit; the output end of the first bias voltage sub-circuit is connected with the control end of the first bias voltage output sub-circuit; the output end of the second bias voltage sub-circuit is connected with the control end of the second bias voltage output sub-circuit; the first output end and the second output end of the first bias voltage output sub-circuit are respectively connected with the first output end and the second output end of the second bias voltage output sub-circuit and are respectively used as the first output end and the second output end of the bias voltage circuit; the third output end and the fourth output end of the first bias voltage output subcircuit are respectively connected with the third output end and the fourth output end of the second bias voltage output subcircuit and are respectively used as the third output end and the fourth output end of the bias voltage circuit.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102035547A (en) * | 2010-12-06 | 2011-04-27 | 上海集成电路研发中心有限公司 | Voltage-to-current converter |
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| US5475343A (en) * | 1994-08-15 | 1995-12-12 | Elantec, Inc. | Class AB complementary output stage |
| US5739721A (en) * | 1996-02-13 | 1998-04-14 | Advanced Micro Devices, Inc. | High swing, low power output stage for an operational amplifier |
| US6590453B2 (en) * | 2001-09-21 | 2003-07-08 | Silicon Storage Technology, Inc. | Folded cascode high voltage operational amplifier with class AB source follower output stage |
| CN106160730B (en) * | 2016-07-13 | 2017-06-13 | 华南理工大学 | Small-signal receiving front-end and method of reseptance |
| CN107834986B (en) * | 2017-11-21 | 2020-04-03 | 中国地质大学（北京） | Single-stage AB class operational transconductance amplifier and analog circuit |
| CN110311636B (en) * | 2019-06-29 | 2023-05-30 | 复旦大学 | High bandwidth Gao Baifu linear amplifier for envelope tracking power supply modulator |
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| CN102035547A (en) * | 2010-12-06 | 2011-04-27 | 上海集成电路研发中心有限公司 | Voltage-to-current converter |
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