CN111403599B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN111403599B CN111403599B CN202010121614.0A CN202010121614A CN111403599B CN 111403599 B CN111403599 B CN 111403599B CN 202010121614 A CN202010121614 A CN 202010121614A CN 111403599 B CN111403599 B CN 111403599B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 230000008859 change Effects 0.000 claims abstract description 38
- 230000007704 transition Effects 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 229910018557 Si O Inorganic materials 0.000 claims abstract description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 7
- -1 silicon ions Chemical class 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 11
- 239000001301 oxygen Substances 0.000 abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 3
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000001659 ion-beam spectroscopy Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910003070 TaOx Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005352 borofloat Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
Abstract
The invention discloses a semiconductor structure and a preparation method thereof. The invention also discloses a manufacturing method of the tantalum oxide-based semiconductor structure. A Ta-Si-O transition layer is formed between the top electrode and the resistance change layer, due to the existence of free Si, the grabbing capacity of the transition layer of the device to oxygen vacancies is stronger than that of an interface layer between the bottom electrode and the resistance change layer, more oxygen vacancies are concentrated in the transition layer and are not easily excited, and the data holding capacity and the switching characteristic of the device are further improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
RRAM (resistive random access memory) is a novel memory, has very wide application prospect in the fields of embedding, AI, edge calculation and the like, and the present mainstream RRAM memory device CELL unit capable of mass production can be divided into three parts: the resistive random access memory comprises a Top Electrode (TE), a Bottom Electrode (BE) and a resistive layer in the middle, wherein the resistive layer is made of transition metal oxides generally, while the materials of the TE and BE electrodes are more selected, such as inert metals, transition metal nitrides, cu and the like.
The RRAM (resistive random access memory) is usually in a high resistance state when the RRAM is prepared, at the moment, when a voltage is applied to two ends of a RRAM CELL device to a certain value, oxygen ions move along with an electric field to form a conductive filament under the action of the electric field to form a conductive path, so that the CELL is converted into a low resistance state, namely 1, a reverse voltage is continuously applied to a resistive random access memory unit, the conductive filament formed by oxygen vacancies is broken under the action of the electric field, and the memory unit is converted into a high resistance state, namely 0. At present, one major bottleneck of RRAM (resistive random access memory) is that when external interference is received, the conductive filament is spontaneously formed or broken to cause the state of the memory cell to be converted, and further, the stored data is lost, so that the endurance performance of the memory is poor, and the switching characteristic and the retention capability of the stored data are insufficient.
It is therefore a goal of our efforts to improve the device performance how to improve the oxygen gettering capabilities of CMOS compatible materials and improve memory endurance, switching characteristics, and retention of stored data.
Disclosure of Invention
The main object of the present invention is to provide a semiconductor structure having high durability, high data retention and high switching characteristics.
In order to achieve the above object, a first aspect of the present application provides a semiconductor structure comprising:
a semiconductor substrate;
a bottom electrode; the semiconductor substrate is formed with a plurality of grooves;
a resistance change layer;
a top electrode formed on the resistive layer;
a transition layer formed between the resistive layer and the top electrode;
the transition layer includes an element Si.
In a second aspect, the present application provides a method for manufacturing a semiconductor structure, comprising the steps of:
providing a semiconductor substrate;
forming a bottom electrode;
forming a resistance change layer on the bottom electrode;
forming a top electrode on the resistance change layer;
and carrying out Si ion implantation to the depth between the top electrode and the resistance change layer to form a transition layer containing Si element.
In addition, the semiconductor structure according to the present invention may have the following additional technical features:
according to one embodiment of the invention, the Si element is present in the transition layer in the form of free Si.
According to one embodiment of the invention, the material of the top electrode is any one of TaN, tiN, pt, ir, cu; the bottom electrode is made of any one of TaN, tiN, pt, ir and Cu.
According to one embodiment of the invention, the material of the resistance change layer is HfO x 、TaO x 、WO x Any one of the above.
According to one embodiment of the invention, said value of x is between 1.5 and 2.5.
According to one embodiment of the invention, the material of the transition layer is Ta-Si-O X -Ta。
According to an embodiment of the present invention, further comprising an interface layer formed between the bottom electrode and the resistance change layer, the interface layer not containing Si.
According to one embodiment of the invention, the material of the interfacial layer is Ta-O-N-Ta.
According to one embodiment of the present invention, the angle of the Si ion implantation is: 10 to 30 degrees.
According to one embodiment of the present invention, the step of forming the bottom electrode comprises: depositing a bottom electrode material on the semiconductor substrate, etching part of the bottom electrode material and exposing part of the semiconductor substrate; filling a barrier layer in the exposed area of the semiconductor substrate, and flattening;
the step of forming the top electrode further comprises: etching part of the top electrode and the resistance change layer, and reserving the top electrode and the resistance change layer above the bottom electrode; and the top electrode and the resistance change layer cover a part of the barrier layer;
and etching the barrier layer until the bottom electrode is exposed after Si ion implantation.
Compared with the prior art, the invention has the following technical effects:
when the materials of the bottom electrode and the top electrode can react with oxygen, the reliability of the traditional memory device is very unfavorable, the invention prevents the reaction with the oxygen by forming a transition layer containing Si between the top electrode and the resistance change layer, and due to the existence of free Si, the capture capacity of the transition layer to oxygen vacancies is stronger compared with an interface layer, more oxygen vacancies are concentrated at the transition layer and are not easily excited, and the data retention capacity and the switching characteristic of the device are further improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic illustration of a bottom electrode formed on a semiconductor substrate layer;
FIG. 2 is a schematic diagram of FIG. 1 after etching away a portion of the bottom electrode and filling the barrier layer;
FIG. 3 is a schematic diagram of FIG. 2 after forming a resistive layer, a top electrode;
FIG. 4 is a schematic illustration of FIG. 3 after etching portions of the top electrode and the resistive layer;
fig. 5 is a schematic diagram of fig. 4 after forming a transition layer by implanting Si ions between the top electrode and the resistance change layer.
Fig. 6 is a schematic illustration of fig. 5 after removal of the barrier layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Referring to fig. 6, a cross-sectional view of a semiconductor structure 100 is illustrated, in accordance with some embodiments of the present invention. Specifically, the semiconductor structure 100 of the present embodiment may be an RRAM memory device including:
a semiconductor substrate 1;
a bottom electrode 2; formed on a semiconductor substrate 1;
a resistance change layer 4;
a top electrode 5 formed on the resistance change layer 4;
a transition layer 6 formed between the resistive layer 4 and the top electrode 5; the transition layer includes an element Si. In particular, the Si in the transition layer may be present in the form of free Si.
Specifically, the material of the resistance change layer can be TaOx, and the value of x is 1.5-2.5;
growing a top electrode TaN on the resistance change layer by a PVD method;
in another embodiment, the bottom electrodes TaN and Ta are deposited first, and then the Ta is oxidized to form the resistance change layer TaOx.
Preferably, the bottom electrode material is prepared on the semiconductor substrate 1 by an industry-mature process, wherein the semiconductor substrate 1 is a silicon substrate or a glass substrate, such as Pyrex 7740, borofloat 33, and the like.
The bottom electrode 2 and the top electrode 5 may be selected from, but not limited to, one of metal materials of tantalum (Ta), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), copper nitride (CuN), and a combination thereof, and have a thickness ranging from 10 to 200nm. Typically, the memory device has a total thickness of between 100nm and 200nm after fabrication.
Preferably, the bottom and top electrodes are TaN.
In a second aspect, the present application provides a method for fabricating a semiconductor structure, comprising the steps of:
s1, as shown in FIG. 1, a semiconductor substrate 1 is provided, and a bottom electrode 2 (BE) is deposited and patterned on the semiconductor substrate 1. Specifically, the bottom electrode 2 (BE) is deposited on the upper surface of the silicon substrate by magnetron sputtering, ion beam sputtering, or electron beam evaporation, PVD or the like. Preferably, the bottom electrode 2 may have a thickness of 50 nm to 100nm, as deposited by PVD. The patterning process is to obtain a specific shape by photolithography and etching processes, deposit a bottom electrode material on the semiconductor substrate 1, and etch a part of the bottom electrode material to expose a part of the semiconductor substrate 1.
S2, as shown in fig. 2, filling the exposed region of the semiconductor substrate 1 with a barrier layer 3, and planarizing, wherein the barrier layer 3 may be selected from a low-k silicon dioxide material.
And S3, as shown in the figure 3, depositing a resistance change layer 4 on the upper surfaces of the bottom electrode 2 (BE) and the barrier layer 3. And depositing the resistance change layer 4 on the upper surface of the bottom electrode 2 (BE) by an atomic layer deposition method, magnetron sputtering, reactive sputtering, ion beam sputtering or other deposition modes. Preferably, the resistance-change layer 4 is a binary transition metal oxide type material layer by a reactive sputtering method, and may be a tantalum oxide material layer, a hafnium oxide material layer, a titanium dioxide material layer, a nickel oxide material layer, a zirconium dioxide material layer, or the like. Preferably, the resistance change layer is a tantalum oxide material layer, and further, the thickness of the resistance change layer is 5 nanometers to 20 nanometers.
S4, with continued reference to fig. 3, a top electrode 5 (TE) is deposited on the upper surface of the resistance change layer 4.
And depositing the top electrode 5 (TE) on the upper surface of the resistance change layer 4 by using an atomic layer deposition method, PVD (physical vapor deposition), magnetron sputtering, ion beam sputtering or other deposition modes. Preferably, PVD deposition is used. Further, the thickness of the top electrode 5 (TE) may be 5 nm to 10 nm.
S5, as shown in fig. 4, the resistance change layer 4 and the top electrode 5 (TE) are patterned.
Etching part of the top electrode 5 and the resistance change layer 4, and reserving the top electrode 5 and the resistance change layer 4 above the bottom electrode; and the top electrode 5 and the resistance change layer 4 cover a part of the barrier layer.
S6, as shown in FIG. 5, si ions are implanted to form the transition layer 6 so as to achieve the purpose of modification.
And controlling the implantation angle (10-30 degrees), implantation energy and implantation dose of silicon ions to enable the silicon ions to reach the interface of the resistive layer 4 and the top electrode 5, so that the interface of the resistive layer 4 and the top electrode 5 is changed, and etching the barrier layer 3 until the bottom electrode 2 is exposed after the Si ions are implanted.
S7, as shown in fig. 6, the barrier layer 3 is removed until the bottom electrode 2 is exposed, and specifically, the barrier layer 3 may be removed by using HF acid or BHF etching.
Wherein the material of the resistance change layer 3 is TaO x The top electrode 5 is made of TaN, the bottom electrode 2 is made of TaN, after ion implantation, the upper interface of the device is Ta-Si-O-X-Ta, the lower interface of the device is Ta-O-N-Ta, due to the existence of free Si, the capturing capability of the upper interface of the device to oxygen vacancies is stronger, more oxygen vacancies are concentrated at the resistance change layer and the upper interface and are not easy to be excited, and the data holding capability and the switching characteristic of the device are further improved.
While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A semiconductor structure, characterized by: the method comprises the following steps:
a semiconductor substrate;
a bottom electrode; the semiconductor substrate is formed with a plurality of grooves;
a resistance change layer;
a top electrode formed on the resistive layer;
a transition layer formed between the resistive layer and the top electrode;
the transition layer contains an Si element;
the width of the transition layer is equal to the width of the resistive layer and the top electrode;
the transition layer is formed by Si ion implantation, wherein the interface between the resistive layer and the top electrode is changed by controlling the implantation angle, implantation energy and implantation dosage of the silicon ions to enable the silicon ions to reach the interface between the resistive layer and the top electrode.
2. The semiconductor structure of claim 1, wherein: the Si element is present in the transition layer in the form of free Si.
3. The semiconductor structure of claim 1, wherein: the top electrode is made of any one of TaN, tiN, pt, ir and Cu; the bottom electrode is made of any one of TaN, tiN, pt, ir and Cu.
4. The semiconductor structure of claim 1, wherein: the material of the resistance change layer is HfO x 、TaO x 、WO x Any one of the above.
5. The semiconductor structure of claim 4, wherein: the value of x is 1.5-2.5.
6. The semiconductor structure of claim 1, wherein: the transition layer is made of Ta-Si-O X -Ta。
7. The semiconductor structure of claim 6, wherein: the resistive layer is formed between the bottom electrode and the resistive layer, and the interface layer does not contain Si.
8. The semiconductor structure of claim 7, wherein: the interface layer is made of Ta-O-N-Ta.
9. A method of fabricating a semiconductor structure according to any one of claims 1 to 8, wherein: the method comprises the following steps:
providing a semiconductor substrate;
forming a bottom electrode;
forming a resistance change layer on the bottom electrode;
forming a top electrode on the resistance change layer;
and carrying out Si ion implantation to the depth between the top electrode and the resistance change layer to form a transition layer containing Si element.
10. A method of fabricating a semiconductor structure according to claim 9, wherein: the angle of the Si ion implantation is as follows: 10 to 30 degrees.
11. A method of fabricating a semiconductor structure according to claim 9, wherein: the step of forming the bottom electrode includes: depositing a bottom electrode material on the semiconductor substrate, etching part of the bottom electrode material, and exposing part of the semiconductor substrate; filling a barrier layer in the exposed area of the semiconductor substrate, and flattening;
the step of forming the top electrode further comprises: etching part of the top electrode and the resistance change layer, and reserving the top electrode and the resistance change layer above the bottom electrode; and the top electrode and the resistance change layer cover part of the barrier layer;
and etching the barrier layer until the bottom electrode is exposed after Si ion implantation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102683583A (en) * | 2011-03-15 | 2012-09-19 | 北京大学 | Unipolar resistive random access memory and manufacturing method thereof |
| WO2016111724A1 (en) * | 2015-01-05 | 2016-07-14 | Shih-Yuan Wang | Resistive random-access memory with implanted and radiated channels |
| US9583701B1 (en) * | 2012-08-14 | 2017-02-28 | Crossbar, Inc. | Methods for fabricating resistive memory device switching material using ion implantation |
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| US20120295398A1 (en) * | 2011-05-16 | 2012-11-22 | Varian Semiconductor Equipment Associates, Inc. | Ion implant modification of resistive random access memory devices |
| US20140103281A1 (en) * | 2011-07-06 | 2014-04-17 | Fudan University | Resistive Memory Based on TaOx Containing Ru Doping and Method of Preparing the Same |
| US9515262B2 (en) * | 2013-05-29 | 2016-12-06 | Shih-Yuan Wang | Resistive random-access memory with implanted and radiated channels |
| WO2014194069A2 (en) * | 2013-05-29 | 2014-12-04 | Shih-Yuan Wang | Resistive random-access memory formed without forming voltage |
| US9425061B2 (en) * | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Buffer cap layer to improve MIM structure performance |
| DE102016005537A1 (en) * | 2016-05-04 | 2017-11-09 | Forschungszentrum Jülich GmbH Fachbereich Patente | Method for producing layers of ReRAM memories and use of an implanter |
| FR3059157B1 (en) * | 2016-11-18 | 2019-04-19 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR MANUFACTURING A RESISTIVE MEMORY |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102683583A (en) * | 2011-03-15 | 2012-09-19 | 北京大学 | Unipolar resistive random access memory and manufacturing method thereof |
| US9583701B1 (en) * | 2012-08-14 | 2017-02-28 | Crossbar, Inc. | Methods for fabricating resistive memory device switching material using ion implantation |
| WO2016111724A1 (en) * | 2015-01-05 | 2016-07-14 | Shih-Yuan Wang | Resistive random-access memory with implanted and radiated channels |
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