CN111403422A - GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel - Google Patents
GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel Download PDFInfo
- Publication number
- CN111403422A CN111403422A CN202010219047.2A CN202010219047A CN111403422A CN 111403422 A CN111403422 A CN 111403422A CN 202010219047 A CN202010219047 A CN 202010219047A CN 111403422 A CN111403422 A CN 111403422A
- Authority
- CN
- China
- Prior art keywords
- layer
- goa
- point metal
- row
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 142
- 239000002184 metal Substances 0.000 claims abstract description 142
- 230000008439 repair process Effects 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 331
- 239000011229 interlayer Substances 0.000 claims description 32
- 238000002161 passivation Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- ZXTFQUMXDQLMBY-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo] ZXTFQUMXDQLMBY-UHFFFAOYSA-N 0.000 claims description 5
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 15
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 239000010408 film Substances 0.000 description 48
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 241001391944 Commicarpus scandens Species 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000000608 laser ablation Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000004811 fluoropolymer Substances 0.000 description 1
- XPBBUZJBQWWFFJ-UHFFFAOYSA-N fluorosilane Chemical group [SiH3]F XPBBUZJBQWWFFJ-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application relates to a GOA circuit, a GOA film layer structure, a preparation method of the GOA film layer structure and a display panel, wherein the GOA circuit comprises a repair line; the repair line and a TFT circuit area of the GOA circuit are arranged at intervals; when the GOA units of each row of cascade GOA units in the GOA circuit are in a normal state, the repair lines are staggered and separated from the metal lines of the Q points of the GOA units of each row of cascade GOA units without electrical contact; the repairing line is used for electrically connecting the Q point metal lines of the GOA units in the Nth row with the Q point metal lines of the GOA units in the N-1 th row when the Q point metal lines of the GOA units in the Nth row are broken, the repairing line is additionally arranged in a TFT circuit area in the GOA circuit, if the Q point metal lines of the GOA units in the Nth row are broken, the Q point metal lines of the GOA units in the Nth row and the Q point metal lines of the GOA units in the N-1 th row are electrically connected through the repairing line, the voltage of the Q points of the GOA units in the N-1 th row is used for driving the GOA units in the Nth row, and therefore the grade transmission effectiveness of the GOA circuit is guaranteed, and the repairing mode does not need to additionally increase process procedures.
Description
Technical Field
The present disclosure relates to display driving technologies, and in particular, to a GOA circuit, a GOA film structure, a method for manufacturing the GOA film structure, and a display panel.
Background
With the continuous development of display technologies, the driving technology of display screens has made a great progress, and a great power is provided for improving the performance of display screens, wherein the GOA (Gate Driver on Array) technology makes the display screen frame narrower, the thickness thinner, the integration level higher, the product form richer, the process flow simpler, the future product is more competitive, the manufacturing cost can be reduced, and the yield of modules can be improved.
However, in the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the Q point metal wire in the traditional GOA circuit is easy to break, so that the level transmission of the GOA circuit is completely failed.
Disclosure of Invention
Therefore, it is necessary to provide a GOA circuit, a GOA film layer structure, a preparation method of the GOA film layer structure, and a display panel, aiming at the problem that a Q-point metal line in a conventional GOA circuit is easy to break, which results in complete failure of level transmission of the GOA circuit.
In order to achieve the above object, an embodiment of the present application provides a GOA circuit, including a repair line;
the repair line and a TFT circuit area of the GOA circuit are arranged at intervals; when the GOA units of each row of cascade GOA units in the GOA circuit are in a normal state, the repair lines are staggered and separated from the metal lines of the Q points of the GOA units of each row of cascade GOA units without electrical contact;
the repair line is used for electrically connecting the Q point metal wire of the GOA unit in the Nth row with the Q point metal wire of the GOA unit in the N-1 th row when the Q point metal wire of the GOA unit in the Nth row is broken.
In one embodiment, the repair line is a metal line made of a molybdenum copper material.
In one embodiment, the repair wire is a metal wire made of a molybdenum aluminum material.
A GOA film layer structure comprises a repairing wire layer;
the repairing line layer is arranged on the glass substrate of the GOA film layer structure and is buried in the buffer layer of the GOA film layer structure; when each row of cascaded GOA units in the GOA film layer structure are in a normal state, the repairing line layer and the Q point metal line layer of each row of cascaded GOA units are staggered and separated from the buffer layer;
and the repairing line layer is used for electrically connecting the Q point metal line layer of the GOA unit in the Nth row with the Q point metal line layer of the GOA unit in the (N-1) th row when the Q point metal line layer of the GOA unit in the Nth row is broken.
In one embodiment, the device further comprises an active layer, a gate insulating layer, a gate layer and an interlayer dielectric layer;
the interlayer dielectric layer is superposed on the buffer layer; the active layer, the grid insulating layer and the grid layer are sequentially overlapped on the buffer layer and are arranged in the interlayer dielectric layer; the Q-point metal wire layer is separated from the active layer, the grid electrode insulating layer and the grid electrode layer, is superposed on the buffer layer and is arranged in the interlayer dielectric layer.
In one embodiment, the pixel structure further comprises a source drain metal layer, a passivation layer, a flat layer and a pixel defining layer;
the passivation layer, the flat layer and the pixel definition layer are sequentially superposed on the interlayer dielectric layer; one end of the source drain metal layer is inserted into the interlayer dielectric layer and is mechanically connected with the active layer; the other end of the source drain metal layer is inserted into the passivation layer.
A preparation method of a GOA film layer structure comprises the following steps:
providing a glass substrate;
forming a repairing line layer on the glass substrate; when each cascaded GOA unit in the GOA film layer structure is in a normal state, the repairing line layer is staggered and separated from the Q point metal line layer of each cascaded GOA unit; the repairing line layer is used for electrically connecting the Q point metal line layer of the GOA units in the Nth row with the Q point metal line layer of the GOA units in the N-1 th row when the Q point metal line layer of the GOA units in the Nth row is broken;
a buffer layer covering the repair line layer is formed on the glass substrate.
In one embodiment, the method further comprises the following steps:
forming an active layer and a Q point metal wire layer which are arranged at intervals on the buffer layer;
sequentially forming a gate insulating layer and a gate electrode layer on the active layer;
and forming an interlayer dielectric layer covering the active layer, the Q-point metal wire layer, the grid insulating layer and the grid layer on the buffer layer.
In one embodiment, the method further comprises the following steps:
forming a trench on the interlayer dielectric layer; the side wall of one end of the groove is mechanically connected with the active layer;
forming a source drain metal layer in the groove; one end of the source drain metal layer is mechanically connected with the active layer, and the other end of the source drain metal layer extends to the interlayer dielectric layer;
forming a passivation layer covering the source drain metal layer on the interlayer dielectric layer;
a planarization layer and a pixel defining layer are sequentially formed on the passivation layer.
A display panel comprises the GOA film layer structure.
One of the above technical solutions has the following advantages and beneficial effects:
the GOA circuit provided by each embodiment of the application comprises a repairing line, wherein the repairing line and a TFT circuit area of the GOA circuit are arranged at intervals; when the GOA units of each row of cascade GOA units in the GOA circuit are in a normal state, the repair lines are staggered and separated from the metal lines of the Q points of the GOA units of each row of cascade GOA units without electrical contact; the repairing line is used for electrically connecting the Q point metal lines of the GOA units in the Nth row with the Q point metal lines of the GOA units in the N-1 th row when the Q point metal lines of the GOA units in the Nth row are broken, the repairing line is additionally arranged in the TFT circuit area in the GOA circuit, if the Q point metal lines of the GOA units in the Nth row are broken, the Q point metal lines of the GOA units in the Nth row and the Q point metal lines of the GOA units in the N-1 th row are electrically connected through the repairing line, the voltage of the Q points of the GOA units in the N-1 th row is used for driving the GOA units in the Nth row, and therefore the grade transmission of the GOA circuit is guaranteed to be effective, in addition, no additional process is needed in the repairing mode, and the improvement of the manufacturing cost is avoided.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a GOA circuit;
FIG. 2 is a schematic diagram of an embodiment of a repair of a GOA circuit;
FIG. 3 is a schematic diagram of an application circuit of a GOA circuit according to an embodiment;
FIG. 4 is a schematic diagram illustrating an exemplary embodiment of an application circuit repair of a GOA circuit;
FIG. 5 is a schematic structural diagram of a GOA film structure in one embodiment;
FIG. 6 is a schematic structural diagram of a GOA film structure in another embodiment;
FIG. 7 is a schematic structural diagram of a GOA film structure in yet another embodiment;
fig. 8 is a schematic flow chart of a method for fabricating a GOA film structure in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "disposed on," "one end," "the other end," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In order to solve the problem that the Q-point metal line in the conventional GOA circuit is easy to break, which causes the complete failure of the stage transmission of the GOA circuit, as shown in fig. 1, a GOA (Gate Driver On Array) circuit is provided, which includes a repair line 11;
the repair line 11 is arranged at an interval from a TFT (Thin Film Transistor) circuit region 13 of the GOA circuit; when the cascaded GOA units 133 in each row in the GOA circuit are in a normal state, the repair line 11 is staggered and separated from the Q-point metal line of the cascaded GOA units 133 in each row without electrical contact;
the repair line 11 is used for electrically connecting the Q-point metal line (Q (N) in fig. 2) of the GOA unit in the nth row and the Q-point metal line (Q (N) in fig. 2) of the GOA unit in the N-1 th row (Q (N-1) in fig. 2) when the Q-point metal line (Q (N) in fig. 2) of the GOA unit in the nth row is broken (as shown in fig. 2).
It should be noted that, in a display panel, for example, an AMO L ED (Active-matrix organic light-emitting diode or Active-matrix organic light-emitting diode) display panel, a top gate structure is generally adopted in a manufacturing process of a TFT circuit area, a failure of a metal line in a GOA circuit at a certain position is a level-pass failure of the GOA circuit, and an important node in the GOA circuit at a Q point is a node at which the metal line is easy to break.
The GOA circuit is wired on a film layer structure and comprises a metal wiring area and a TFT circuit area, wherein the metal wiring area is mainly used for arranging metal wiring, the TFT circuit area is mainly used for arranging thin film transistors, Q point metal wires are positioned in the TFT circuit area, repair wires are arranged at intervals in the TFT circuit area, furthermore, the repair wires are arranged in parallel to the TFT circuit area, the wiring of the repair wires passes through GOA units cascaded in each row in the TFT circuit area and is staggered and separated from the Q point metal wires of the GOA units cascaded in each row, and when the GOA circuit is normal (namely the GOA units cascaded in each row are not broken by the Q point metal wires), the repair wires are in non-electric connection with circuits in the TFT circuit area.
As shown in fig. 2, when it is detected that the Q-point metal line of the GOA unit in the nth row of the GOA circuit is broken (as shown in fig. 2 at position 1), the GOA unit in the nth row cannot obtain a normal driving voltage from the metal routing area, in order to ensure the level pass of the GOA units in the nth and subsequent rows to be valid, the Q-point metal line of the GOA unit in the nth row and the Q-point metal line of the GOA unit in the N-1 row are electrically connected through a repair line, the GOA unit in the nth row is driven by using the Q-point voltage of the GOA unit in the N-1 row, specifically, the repair line is cut off from a position between the GOA unit in the N-2 th row and the GOA unit in the N-1 row (as shown in fig. 2 at position 2), and cut off from a position between the GOA unit in the nth row and the GOA unit in the N +1 row (as shown in fig. 2 at position 3), and then the repair line between the GOA unit in the nth row and the GOA unit in the N-2 th row and the N-1 row is welded to the metal line (position 4 in fig. 2), and the other end is welded to the Q-point metal line of the GOA unit in the nth row (position 5 in fig. 2), wherein it should be noted that the welding point of the repair line on the Q-point metal line of the GOA unit in the nth row is to enable the Q-point voltage of the GOA unit in the N-1 th row to be transmitted to the thin film transistor of the GOA unit in the nth row.
In one example, the repair line and the Q-point metal line of the GOA unit in the nth row and the Q-point metal line of the GOA unit in the N-1 th row are respectively welded by a laser welding process.
The repair line is a conductive wire made of a metallic material, and in one example, the repair line is a metallic wire made of a molybdenum-copper material. In another example, the repair wire is a metal wire made of a molybdenum aluminum material.
The repair method of the present application can be applied to various GOA circuits, and now, taking the GOA circuit described in fig. 3 (as shown in fig. 3, the GOA circuit includes 6 thin film transistors and one capacitor) as an example for explanation, as shown in fig. 4, when a line break occurs at position 1 of the GOA cell in the nth row, position 2 and position 3 of the repair line are cut, and the Q-point metal line of the GOA cell in the nth row and the Q-point metal line of the GOA cell in the N-1 th row are respectively welded at position 4 and position 5.
In each embodiment of the GOA circuit, the GOA circuit comprises a repairing line, wherein the repairing line and a TFT circuit area of the GOA circuit are arranged at intervals; when the GOA units of each row of cascade GOA units in the GOA circuit are in a normal state, the repair lines are staggered and separated from the metal lines of the Q points of the GOA units of each row of cascade GOA units without electrical contact; the repairing line is used for electrically connecting the Q point metal lines of the GOA units in the Nth row with the Q point metal lines of the GOA units in the N-1 th row when the Q point metal lines of the GOA units in the Nth row are broken, the repairing line is additionally arranged in the TFT circuit area in the GOA circuit, if the Q point metal lines of the GOA units in the Nth row are broken, the Q point metal lines of the GOA units in the Nth row and the Q point metal lines of the GOA units in the N-1 th row are electrically connected through the repairing line, the voltage of the Q points of the GOA units in the N-1 th row is used for driving the GOA units in the Nth row, and therefore the grade transmission of the GOA circuit is guaranteed to be effective, in addition, no additional process is needed in the repairing mode, and the improvement of the manufacturing cost is avoided.
In one embodiment, as shown in fig. 5, a GOA film layer structure is provided, comprising a repair line layer 51;
the repairing line layer 51 is arranged on the glass substrate 53 of the GOA film layer structure and is embedded in the buffer layer 55 of the GOA film layer structure; when each cascaded GOA unit in the GOA film layer structure is in a normal state, the repairing line layer 51 and the Q point metal line layer 57 of each cascaded GOA unit are staggered and separated from the buffer layer 55;
the repair line layer 51 is used for electrically connecting the Q-point metal line layer of the N-th row of GOA units and the Q-point metal line layer of the N-1 th row of GOA units when the Q-point metal line layer of the N-th row of GOA units is broken.
It should be noted that the GOA circuit of the present application is patterned and fabricated into a GOA film layer structure, where the GOA film layer structure includes a repair line layer buried in a buffer layer of the GOA film layer structure. The GOA circuit comprises a TFT circuit region, a repairing line layer, a metal line layer and a buffer layer, wherein the TFT circuit region of the GOA circuit is formed on the buffer layer, the buffer layer is separated from the repairing line layer, specifically, wiring of the metal line layer and GOA units which are cascaded in each row in the TFT circuit region are crossed and separated from Q point metal line layers of the GOA units which are cascaded in each row, and when the GOA circuit is normal (namely, the situation that the Q point metal line layers are broken does not occur in the GOA units which are cascaded in each row), the repairing line layer is in non-electric connection with the Q.
When the breakage of the Q point metal wire layer of the GOA unit in the Nth row of the GOA circuit is detected, the repairing wire layer is cut off from a position between the GOA unit in the N-2 th row and the GOA unit in the N-1 th row, and is cut off from a position between the GOA unit in the Nth row and the GOA unit in the N +1 th row, then one end of the repairing wire layer cut off from a position between the GOA unit in the N-2 th row and the GOA unit in the N-1 th row is welded with the Q point metal wire layer of the GOA unit in the Nth row, the other end of the repairing wire layer is welded with the Q point metal wire layer of the GOA unit in the N-1 th row, specifically, the buffer layer at the intersection of the Q point metal wire layer of the GOA unit in the Nth row and the repairing wire layer cut off is penetrated, the welding of the repairing wire layer and the Q point metal wire layer of the GOA unit in the Nth row is realized, and the buffer layer at the intersection of the Q point metal wire layer of the GOA unit in the N-, and realizing the welding of the repair line layer and the Q point metal line layer of the GOA unit in the (N-1) th row, wherein the welding points on the repair line layer and the Q point metal line of the GOA unit in the Nth row are required to enable the Q point voltage of the GOA unit in the (N-1) th row to be transmitted to the thin film transistor of the GOA unit in the Nth row.
In order to avoid adding a new process technology and increasing the production and manufacturing cost, in one example, the repair line layer is manufactured by adopting a traditional M0 process (a first metal process) for manufacturing a GOA film structure, and only the metal pattern of the M0 process is changed to increase the repair line layer, so that a new process technology does not need to be added and the cost is not increased.
In one example, as shown in fig. 6, the GOA film layer structure further includes an active layer 59, a gate insulating layer 61, a gate layer 63, and an interlayer dielectric layer 65;
an interlayer dielectric layer 65 overlies the buffer layer 55; an active layer 59, a gate insulating layer 61 and a gate electrode layer 63 are sequentially stacked on the buffer layer 55 and disposed in the interlayer dielectric layer 65; the Q-point metal line layer 57 is spaced apart from the active layer 59, the gate insulating layer 61 and the gate electrode layer 63, overlaps the buffer layer 55, and is disposed in the interlayer dielectric layer 65.
In one example, as shown in fig. 7, the GOA film layer structure further includes a source drain metal layer 67, a passivation layer 69, a planarization layer 71, and a pixel defining layer 73;
a passivation layer 69, a planarization layer 71, and a pixel defining layer 73 are sequentially stacked on the interlayer dielectric layer 65; one end of the source-drain metal layer 67 is inserted into the interlayer dielectric layer 65 and is mechanically connected with the active layer 59; the other end of the source-drain metal layer 67 is inserted into the passivation layer 69.
In each embodiment of the GOA film structure, the GOA film structure comprises a repairing line layer, wherein the repairing line layer is arranged on a glass substrate of the GOA film structure and is buried in a buffer layer of the GOA film structure; when each row of cascaded GOA units in the GOA film layer structure are in a normal state, the repairing line layer and the Q point metal line layer of each row of cascaded GOA units are staggered and separated from the buffer layer, wherein the repair line layer is used for electrically connecting the Q point metal line layer of the GOA units in the Nth row with the Q point metal line layer of the GOA units in the N-1 th row when the Q point metal line layer of the GOA units in the Nth row is broken, by additionally arranging a repairing line layer in a TFT circuit area in the GOA circuit, if the Q point metal line of the GOA unit in the Nth row is broken, the Q point metal wire of the GOA unit in the Nth row is electrically connected with the Q point metal wire layer of the GOA unit in the N-1 th row through the repairing wire layer, the GOA unit in the Nth row is driven by the voltage of the Q point of the GOA unit in the N-1 th row, therefore, the grade transmission of the GOA circuit is ensured to be effective, and the repair mode does not need to additionally increase the process, thereby avoiding the increase of the manufacturing cost.
In one embodiment, as shown in fig. 8, a method for preparing a GOA film layer structure includes the following steps:
step S81, providing a glass substrate;
step S83, forming a repair line layer on the glass substrate; when each cascaded GOA unit in the GOA film layer structure is in a normal state, the repairing line layer is staggered and separated from the Q point metal line layer of each cascaded GOA unit; the repairing line layer is used for electrically connecting the Q point metal line layer of the GOA units in the Nth row with the Q point metal line layer of the GOA units in the N-1 th row when the Q point metal line layer of the GOA units in the Nth row is broken;
in step S85, a buffer layer is formed on the glass substrate to cover the repair line layer.
It should be noted that the repair line layer and the Buffer layer are deposited on the glass substrate by a Deposition process, and further, may be formed by, but not limited to, a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), an atomic layer Deposition (a L D), a low Pressure Chemical Vapor Deposition (L ow Pressure Chemical Vapor Deposition, L PCVD), a laser ablation Deposition (L a relative Deposition, L AD), and a Selective Epitaxial Growth (SEG).
Furthermore, the process of depositing the repair line layer can adopt the traditional M0 process for preparing the GOA film structure, and only the repair line layer needs to be added to the metal pattern in the M0 process.
The repair line layer in this embodiment is the same as the repair line layer described in each embodiment of the GOA film layer structure of the present application, and please refer to the repair line layer described in each embodiment of the GOA film layer structure of the present application for details, which is not described herein again.
In one embodiment, the method for preparing a GOA film layer structure further comprises the following steps:
forming an active layer and a Q point metal wire layer which are arranged at intervals on the buffer layer;
sequentially forming a gate insulating layer and a gate electrode layer on the active layer;
and forming an interlayer dielectric layer covering the active layer, the Q-point metal wire layer, the grid insulating layer and the grid layer on the buffer layer.
The active (Poly) layer is formed of a material such as polysilicon, the source, Q-point metal line layer is formed of a material such as molybdenum copper or molybdenum aluminum, the Gate Insulator (GI) layer is formed of an inorganic material (e.g., silicon nitride or silicon oxide) for isolating the active layer from the Gate layer, the Gate (Gate) layer is formed of a conductive material (e.g., tantalum, tungsten, tantalum nitride, or titanium nitride), and the interlayer dielectric (I L D) layer is formed of a dielectric material (e.g., a fluoropolymer base or inorganic titanate surface-modified with fluorosilane).
The active layer, the gate insulating layer, the gate electrode layer, and the interlayer dielectric layer are formed using a Deposition process, and further, may be formed using, but not limited to, a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), an atomic layer Deposition (a L D), a low Pressure Chemical Vapor Deposition (L ow Pressure Chemical Vapor Deposition, L PCVD), a laser ablation Deposition (L area Deposition, L AD), and a Selective Epitaxial Growth (SEG).
In one embodiment, as shown in the figure, the method for preparing the GOA film layer structure further includes the following steps:
forming a trench on the interlayer dielectric layer; the side wall of one end of the groove is mechanically connected with the active layer;
forming a source drain metal layer in the groove; one end of the source drain metal layer is mechanically connected with the active layer, and the other end of the source drain metal layer extends to the interlayer dielectric layer;
forming a passivation layer covering the source drain metal layer on the interlayer dielectric layer;
a planarization layer and a pixel defining layer are sequentially formed on the passivation layer.
The source-drain metal layer is formed of a material such as copper, molybdenum, aluminum, titanium, or a combination thereof, the passivation layer is formed of a material such as silicon oxide, the planarization layer is formed of a material such as a resin, and the pixel defining layer is formed of a material such as a photosensitive resin.
The source and drain metal layers, the passivation layer, the planarization layer, and the pixel defining layer are formed using a Deposition process, and further, may be formed using, but not limited to, a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), an atomic layer Deposition (a L D), a low Pressure Chemical Vapor Deposition (L ow Pressure Chemical Vapor Deposition, L PCVD), a laser ablation Deposition (L a displacement, L AD), and a Selective Epitaxial Growth (SEG) in which the repair line layer is formed of a molybdenum copper or molybdenum aluminum material.
In the embodiment of the preparation method of the GOA film layer structure, the repairing line layer is formed on the GOA film layer structure, the repairing line is additionally arranged in the TFT circuit area in the GOA circuit, if the Q point metal line of the GOA unit in the Nth row is broken, the Q point metal line of the GOA unit in the Nth row and the Q point metal line of the GOA unit in the N-1 th row are electrically connected through the repairing line, the voltage of the Q point of the GOA unit in the N-1 th row is used for driving the GOA unit in the Nth row, so that the grade transmission effectiveness of the GOA circuit is ensured, the repairing mode does not need to additionally increase a process, and the Q point broken line problem in the GOA circuit can be repaired without increasing the manufacturing cost.
It should be understood that, although the steps in the flowchart of fig. 8 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 8 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, a display panel includes the GOA film layer structure described in the embodiments of the GOA film layer structure.
The Display panel may be an O L ED (Organic L light-Emitting Diode, Organic electroluminescent Display) Display panel or a L CD (L acquired Crystal Display, liquid Crystal Display) panel.
The structure of the GOA film in this embodiment is the same as the structure of the GOA film described in the embodiments of the GOA film structure of this application, and please refer to the description of the embodiments of the GOA film structure of this application in detail, which is not described herein again.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A GOA circuit is characterized by comprising a repair line;
the repairing line and a TFT circuit region of the GOA circuit are arranged at intervals; when GOA units cascaded in each row in the GOA circuit are in a normal state, the repair lines are staggered and separated from Q point metal lines of the GOA units cascaded in each row and are not in electric contact;
the repair line is used for electrically connecting the Q point metal wire of the GOA unit in the Nth row with the Q point metal wire of the GOA unit in the N-1 th row when the Q point metal wire of the GOA unit in the Nth row is broken.
2. The GOA circuit of claim 1, wherein the repair wire is a metal wire made of a molybdenum copper material.
3. The GOA circuit of claim 1, wherein the repair wire is a metal wire made of a molybdenum aluminum material.
4. A GOA film layer structure is characterized by comprising a repairing wire layer;
the repairing line layer is arranged on the glass substrate of the GOA film layer structure and is buried in the buffer layer of the GOA film layer structure; when each cascaded GOA unit in the GOA film layer structure is in a normal state, the repairing line layer and the Q point metal line layer of each cascaded GOA unit are staggered and separated from the buffer layer;
the repairing line layer is used for electrically connecting the Q point metal line layer of the GOA units in the Nth row with the Q point metal line layer of the GOA units in the (N-1) th row when the Q point metal line layer of the GOA units in the Nth row is broken.
5. The GOA film structure of claim 4, further comprising an active layer, a gate insulating layer, a gate layer and an interlayer dielectric layer;
the interlayer dielectric layer is superposed on the buffer layer; the active layer, the gate insulating layer and the gate electrode layer are sequentially overlapped on the buffer layer and are arranged in the interlayer dielectric layer; the Q-point metal wire layer is separated from the active layer, the grid electrode insulating layer and the grid electrode layer, is superposed on the buffer layer and is arranged in the interlayer dielectric layer.
6. The GOA film structure of claim 5, further comprising a source drain metal layer, a passivation layer, a planarization layer and a pixel defining layer;
the passivation layer, the flat layer and the pixel defining layer are sequentially superposed on the interlayer dielectric layer; one end of the source drain metal layer is inserted into the interlayer dielectric layer and is mechanically connected with the active layer; and the other end of the source drain metal layer is inserted into the passivation layer.
7. The preparation method of the GOA film layer structure is characterized by comprising the following steps:
providing a glass substrate;
forming a repair line layer on the glass substrate; when each cascaded GOA unit in the GOA film layer structure is in a normal state, the repairing line layer is staggered and separated from the Q point metal line layer of each cascaded GOA unit; the repair line layer is used for electrically connecting the Q point metal line layer of the GOA units in the Nth row with the Q point metal line layer of the GOA units in the (N-1) th row when the Q point metal line layer of the GOA units in the Nth row is broken;
and forming a buffer layer covering the repair line layer on the glass substrate.
8. The method for preparing a GOA film structure according to claim 7, further comprising the steps of:
forming an active layer and a Q point metal wire layer which are arranged at intervals on the buffer layer;
sequentially forming a gate insulating layer and a gate electrode layer on the active layer;
forming an interlayer dielectric layer on the buffer layer to cover the active layer, the Q-point metal line layer, the gate insulating layer, and the gate layer.
9. The method for preparing a GOA film structure according to claim 8, further comprising the steps of:
forming a trench on the interlayer dielectric layer; the side wall of one end of the groove is mechanically connected with the active layer;
forming a source drain metal layer in the groove; one end of the source drain metal layer is mechanically connected with the active layer, and the other end of the source drain metal layer extends to the interlayer dielectric layer;
forming a passivation layer covering the source drain metal layer on the interlayer dielectric layer;
and sequentially forming a flat layer and a pixel defining layer on the passivation layer.
10. A display panel comprising the GOA film structure of any one of claims 4 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010219047.2A CN111403422B (en) | 2020-03-25 | 2020-03-25 | GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010219047.2A CN111403422B (en) | 2020-03-25 | 2020-03-25 | GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111403422A true CN111403422A (en) | 2020-07-10 |
| CN111403422B CN111403422B (en) | 2023-04-18 |
Family
ID=71413554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010219047.2A Active CN111403422B (en) | 2020-03-25 | 2020-03-25 | GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111403422B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101216644A (en) * | 2007-12-28 | 2008-07-09 | 昆山龙腾光电有限公司 | LCD device array substrate, its defect mending method |
| CN102156366A (en) * | 2010-12-28 | 2011-08-17 | 友达光电股份有限公司 | Repairing circuit for displaying panel |
| CN103345093A (en) * | 2013-06-28 | 2013-10-09 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, manufacturing and restoring method of array substrate and display device |
| CN103745700A (en) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | Self-repairing type grid drive circuit |
| CN105044946A (en) * | 2015-09-09 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display device and restoration method |
| US20160313620A1 (en) * | 2015-04-27 | 2016-10-27 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Goa circuit repair method |
| CN106803414A (en) * | 2017-03-07 | 2017-06-06 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and display device |
| CN107768387A (en) * | 2017-11-29 | 2018-03-06 | 武汉华星光电技术有限公司 | A kind of array base palte and its restorative procedure |
| CN108761929A (en) * | 2018-05-18 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of display base plate, display device, production method and its restorative procedure |
| CN108877683A (en) * | 2018-07-25 | 2018-11-23 | 京东方科技集团股份有限公司 | Gate driving circuit and driving method, display device, manufacturing method of array base plate |
| CN110568678A (en) * | 2019-09-26 | 2019-12-13 | 深圳市华星光电技术有限公司 | Display panel |
-
2020
- 2020-03-25 CN CN202010219047.2A patent/CN111403422B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101216644A (en) * | 2007-12-28 | 2008-07-09 | 昆山龙腾光电有限公司 | LCD device array substrate, its defect mending method |
| CN102156366A (en) * | 2010-12-28 | 2011-08-17 | 友达光电股份有限公司 | Repairing circuit for displaying panel |
| CN103345093A (en) * | 2013-06-28 | 2013-10-09 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, manufacturing and restoring method of array substrate and display device |
| CN103745700A (en) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | Self-repairing type grid drive circuit |
| US20160313620A1 (en) * | 2015-04-27 | 2016-10-27 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Goa circuit repair method |
| CN105044946A (en) * | 2015-09-09 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display device and restoration method |
| CN106803414A (en) * | 2017-03-07 | 2017-06-06 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and display device |
| CN107768387A (en) * | 2017-11-29 | 2018-03-06 | 武汉华星光电技术有限公司 | A kind of array base palte and its restorative procedure |
| CN108761929A (en) * | 2018-05-18 | 2018-11-06 | 京东方科技集团股份有限公司 | A kind of display base plate, display device, production method and its restorative procedure |
| CN108877683A (en) * | 2018-07-25 | 2018-11-23 | 京东方科技集团股份有限公司 | Gate driving circuit and driving method, display device, manufacturing method of array base plate |
| CN110568678A (en) * | 2019-09-26 | 2019-12-13 | 深圳市华星光电技术有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111403422B (en) | 2023-04-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7476900B2 (en) | Thin film transistor, organic electroluminescence display device and manufacturing method of the same | |
| CN100363830C (en) | Tft LCD, laminated capacitor and forming method thereof | |
| US10591763B2 (en) | Display device | |
| US5897328A (en) | Thin film transistor, organic electroluminescence display device and manufacturing method of the same | |
| CN100511756C (en) | Flat panel display and method for fabricating the same | |
| US4935792A (en) | Thin film transistor array | |
| CN101068025B (en) | Display device | |
| US20110266542A1 (en) | Semiconductor device and method of fabricating the same | |
| US7817216B2 (en) | Flat panel display and method for fabricating the same | |
| CN1841780B (en) | Thin film transistor, thin film transistor display panel, and manufacturing method thereof | |
| US9373650B2 (en) | TFT array substrate, manufacturing method thereof and display panel | |
| US4961629A (en) | Liquid crystal display device | |
| CN104733470A (en) | Panel display device and preparation method thereof | |
| US7816174B2 (en) | Control element of an organic electro-luminescent display and manufacturing process thereof | |
| CN111341791B (en) | GOA circuit, GOA film layer structure preparation method and display panel | |
| CN111403422B (en) | GOA circuit, GOA film layer structure, preparation method of GOA film layer structure and display panel | |
| JPH10142636A (en) | Active matrix type display circuit | |
| CN100405610C (en) | Conductor arrangement layering structure formed in contact hole, manufacturing method of conductor arrangement layering structure and display device having said conductor arrangement layering | |
| JP5079512B2 (en) | Display device using thin film element and method of manufacturing display device | |
| CN102998866B (en) | Array substrate, display device and manufacturing method | |
| CN112259555A (en) | Array substrate, preparation method thereof and display panel | |
| WO2020208704A1 (en) | Display device and manufacturing method | |
| CN104536227B (en) | Array base palte, display device and preparation method | |
| CN111063698B (en) | Organic light emitting diode array substrate, manufacturing method, display panel and device | |
| KR101054340B1 (en) | Thin film transistor array panel and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |