CN111403305A - Method for testing electrical parameters of diode in semiconductor structure - Google Patents
Method for testing electrical parameters of diode in semiconductor structure Download PDFInfo
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- CN111403305A CN111403305A CN201910003281.9A CN201910003281A CN111403305A CN 111403305 A CN111403305 A CN 111403305A CN 201910003281 A CN201910003281 A CN 201910003281A CN 111403305 A CN111403305 A CN 111403305A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
The invention relates to a method for testing electrical parameters of a diode in a semiconductor structure. The method comprises the following steps: forming a semiconductor structure; and contacting a first test head of the test equipment with the first conductive type doping area, and contacting a second test head with the second conductive type doping area, and testing the electrical parameters of the diode consisting of the second conductive type doping area and the first conductive type well area. The isolation region is arranged between the first conduction type doping region and the second conduction type doping region to separate the first conduction type doping region from the second conduction type doping region, so that the electrical parameters of the diode consisting of the second conduction type doping region and the first conduction type well region can be accurately measured through the first testing head in contact with the first conduction type doping region and the second testing head in contact with the second conduction type doping region.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for testing electrical parameters of a diode in a semiconductor structure.
Background
The most basic devices of semiconductors are diodes (diodes), and for 0.18-0.13 micron processes, 3 kinds of wells, N-wells (NW), P-wells (PW) and deep N-wells (DNW) are usually used, wherein DNW is set when a customer needs to use a bipolar transistor (BJT) or a metal oxide semiconductor transistor (Isolation MOS), so that two diodes (diodes) of PW-NW and PW-DNW exist, and how to set a layout (L ayout) structure to test electrical parameters of the diodes (diodes) is important.
Because the DNW implant is deep, the same type of upper well (i.e., NW) extraction must be used, and then the two test terminals (e.g., two probes) of the test equipment are connected to the NW and the PW terminal to test the electrical parameters of the PW-DNW diode, such as the reverse voltage (BV) and the junction capacitance. However, because the NW and PW are in contact, a PW-NW diode is formed, and the reverse voltage (BV) of the PW-NW diode is relatively low, so the reverse voltage of the PW-NW diode actually measured by the test cannot faithfully reflect the reverse voltage of the PW-DNW diode.
Disclosure of Invention
Based on this, it is necessary to provide a new method for testing electrical parameters of a diode in a semiconductor structure for the electrical performance test problem of the PW-DNW diode.
A method of testing an electrical parameter of a diode in a semiconductor structure, comprising: step A, forming a semiconductor structure; the semiconductor structure comprises a first conductive type doping area, a second conductive type doping area, a first conductive type well area and an isolation area, wherein the isolation area is positioned between the first conductive type doping area and the second conductive type doping area, and the isolation area isolates the first conductive type doping area from the second conductive type doping area; a part of the first conductive type well region is positioned below the first conductive type doped region and is in contact with the first conductive type doped region, and a part of the first conductive type well region is positioned below the second conductive type doped region and is in contact with the second conductive type doped region, wherein the first conductive type and the second conductive type are opposite conductive types; and step B, contacting a first test head of the test equipment with the first conductive type doping area, and contacting a second test head with the second conductive type doping area, and testing the electrical parameters of the diode consisting of the second conductive type doping area and the first conductive type well area.
In one embodiment, a doping concentration of the first conductive type doping region is greater than a doping concentration of the first conductive type well region.
In one embodiment, the first-conductivity-type doped region is arranged on the periphery of the second-conductivity-type doped region so as to surround the second-conductivity-type doped region on a plane.
In one embodiment, the isolation region and the first conductive type well region are formed in a same doping process.
In one embodiment, the step a includes: obtaining a substrate; doping the substrate to form the first conductive type well region; and doping the substrate to form the first conductive type doped region and the second conductive type doped region respectively, wherein the first conductive type well region between the first conductive type doped region and the second conductive type doped region is used as the isolation region.
In one embodiment, the implantation depth of the first conductivity type well region is 1 to 2 micrometers deeper than the implantation depth of the first conductivity type doped region and the second conductivity type doped region.
In one embodiment, the electrical parameters tested in step B include reverse voltage and junction capacitance.
In one embodiment, the doping concentrations of the first conductive type doping region and the second conductive type doping region are the same.
In one embodiment, the implantation depth of the first conductive type doping region and the second conductive type doping region is the same.
In one embodiment, the second conductive type doping region is implanted to a depth of 0.5 to 1 micron.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
According to the method for testing the electrical parameters of the diode in the semiconductor structure, the isolation region is arranged between the first conduction type doping region and the second conduction type doping region to separate the first conduction type doping region from the second conduction type doping region, so that the electrical parameters of the diode consisting of the second conduction type doping region and the first conduction type well region can be accurately tested through the first testing head in contact with the first conduction type doping region and the second testing head in contact with the second conduction type doping region.
Drawings
FIG. 1 is a schematic top view of a semiconductor structure to be tested in one embodiment;
FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1;
FIG. 3 is a flow diagram of a method for testing electrical parameters of a diode in a semiconductor structure, according to one embodiment;
FIG. 4 is a schematic top view of a semiconductor structure to be tested in another embodiment;
figure 5 is a flow diagram of a method for forming the semiconductor structure of figure 4 in one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
FIG. 1 is a schematic top view of a semiconductor structure to be tested in one embodiment, FIG. 2 is a cross-sectional view along line AA' of FIG. 1, and FIG. 3 is a flow chart of a method for testing electrical parameters of a diode in a semiconductor structure in one embodiment, the method comprising:
s310, forming a semiconductor structure to be tested.
The semiconductor structure includes a first conductive type doped region 20, a second conductive type doped region 21, a first conductive type well region 10 and an isolation region 22, wherein a portion of the first conductive type well region 10 is located under the first conductive type doped region 20 and is in contact with the first conductive type doped region 20, and a portion is located under the second conductive type doped region 21 and is in contact with the second conductive type doped region 21. The isolation region 22 is located between the first-conductivity-type doped region 20 and the second-conductivity-type doped region 21, and the isolation region 22 isolates the first-conductivity-type doped region 20 from the second-conductivity-type doped region 21. In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
After the semiconductor structure shown in fig. 1 and 2 is formed, an electrical parameter test is performed on the diode in the semiconductor structure by the following test method:
s320, testing the electrical parameters of the diode composed of the second conductive-type doped region 21 and the first conductive-type well region 10.
A first test head of the test equipment is brought into contact with the first conductivity type doped region 20, and a second test head is brought into contact with the second conductivity type doped region 21, to test electrical parameters of the diode composed of the second conductivity type doped region 21 and the first conductivity type well region 10. In one embodiment, the first and second test heads may be probes or probe cards.
The method for testing the electrical parameters of the diode in the semiconductor structure isolates the first conductive type doped region 20 from the second conductive type doped region 21 by arranging the isolation region 22 between the first conductive type doped region 20 and the second conductive type doped region 21. Thus, the electrical parameters of the diode composed of the second conductive-type doped region 21 and the first conductive-type well region 10 can be accurately measured by the first test head in contact with the first conductive-type doped region 20 and the second test head in contact with the second conductive-type doped region 21.
In one embodiment, the electrical parameters tested in step S320 include reverse voltage (BV) and Junction (Junction) capacitance.
In one embodiment, a scan voltage of 0 v to 20 v is applied between the first conductive type doping region 20 and the second conductive type doping region 21 by the testing device, wherein the N-type test point is set to a high potential, the P-type test point is set to a zero potential, and when a current value on the testing device is 1 microamp (i.e., a current between the first conductive type doping region 20 and the second conductive type doping region 21 is 1 microamp), the scan voltage value is a reverse voltage of the diode composed of the second conductive type doping region 21 and the first conductive type well region 10.
Specifically, the junction capacitance is composed of 2 parts, namely, a bottom capacitance (see downward arrow in fig. 4, the junction capacitance is determined by an area) and a side capacitance (see left and right arrows in fig. 4, the side capacitance is determined by a perimeter), the second conductivity type doped regions 21 with different sizes can be designed, and the capacitance per unit area of the bottom of the contact surface and the capacitance per unit perimeter of the side of the contact surface are calculated by giving a capacitance value measured under the size of the second conductivity type doped region 21, so that the total capacitance of the diode composed of the second conductivity type doped region 21 and the first conductivity type well region 10 with any area can be calculated.
In one embodiment, the doping concentration of the first conductive-type doping region 20 is greater than the doping concentration of the first conductive-type well region 10.
Referring to fig. 1 and 2, in this embodiment, the first conductive-type doped region 20 is located at the periphery of the second conductive-type doped region 21 so as to surround the second conductive-type doped region 21 in a plane. That is, the first conductive-type doped region 20 surrounds the second conductive-type doped region 21 from a cross-sectional view of the semiconductor structure.
When the layout design is performed, the first conductive type doped region 20 may be designed as an outer ring, the isolation region 22 may be drawn as an intermediate ring in the outer ring, and after the logic operation, the second conductive type doped region 21 is used as a reverse of the first conductive type doped region 20 and the isolation region 22 (that is, the regions of the first conductive type doped region 20 and the isolation region 22 except the first conductive type doped region 20 and the isolation region 22 are the second conductive type doped region 21), and due to the existence of the isolation region 22, the second conductive type doped region 21 and the first conductive type doped region 20 are isolated.
In one embodiment, the first-conductivity-type doped region 20 is an N-well, the second-conductivity-type doped region 21 is a P-well, and the first-conductivity-type well region 10 is a deep N-well. Other doped regions may be further formed in the N-well and the P-well subsequently.
In one embodiment, the implantation depth of the first conductivity type well region 10 is deeper than the first conductivity type doped region 20 and the second conductivity type doped region 21, for example: 1 micron to 2 microns and 1.5 microns.
In one embodiment, the doping concentrations of the first conductive-type doping region 20 and the second conductive-type doping region 21 are the same.
In one embodiment, the implantation depth of the first conductivity type well region 10 may be set as desired, for example, 0.5 to 1 micron, 0.7 micron.
In one embodiment, the semiconductor structure under test further includes a substrate extraction region Psub disposed at the periphery of the second conductive-type doped region 21 and isolated from the second conductive-type doped region 21.
Fig. 4 is a schematic top view of a semiconductor structure to be tested in another embodiment, which includes a first-conductivity-type well region 110, a first-conductivity-type doped region 120, and a second-conductivity-type doped region 121. The main difference from the embodiment shown in fig. 2 is that a portion of the first-conductivity-type well region 110 is directly used as the isolation region 22, so that the isolation region and the first-conductivity-type well region 110 are formed in the same doping process.
FIG. 5 is a flow chart of a method of forming the semiconductor structure of FIG. 4 in one embodiment:
s410, acquiring the substrate.
In one embodiment, the substrate is a second conductivity type substrate.
And S420, doping the substrate to form a first conductive type well region.
In one embodiment, the first conductive type well region 110 may be formed by implanting first conductive type ions into the substrate through an ion implantation process.
And S430, doping the substrate to form a first conductive type doped region and a second conductive type doped region.
In one embodiment, the first conductive type ions and the second conductive type ions may be respectively implanted into the substrate through two ion implantation processes, thereby respectively forming the first conductive type doped region 120 and the second conductive type doped region 121, and the first conductive type well region 110 between the first conductive type doped region 120 and the second conductive type doped region 121 serves as an isolation region.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method of testing an electrical parameter of a diode in a semiconductor structure, comprising:
step A, forming a semiconductor structure; the semiconductor structure comprises a first conductive type doping area, a second conductive type doping area, a first conductive type well area and an isolation area, wherein the isolation area is positioned between the first conductive type doping area and the second conductive type doping area, and the isolation area isolates the first conductive type doping area from the second conductive type doping area; a part of the first conductive type well region is positioned below the first conductive type doped region and is in contact with the first conductive type doped region, and a part of the first conductive type well region is positioned below the second conductive type doped region and is in contact with the second conductive type doped region, wherein the first conductive type and the second conductive type are opposite conductive types;
and step B, contacting a first test head of the test equipment with the first conductive type doping area, and contacting a second test head with the second conductive type doping area, and testing the electrical parameters of the diode consisting of the second conductive type doping area and the first conductive type well area.
2. The method according to claim 1, wherein a doping concentration of the first-conductivity-type doped region is greater than a doping concentration of the first-conductivity-type well region.
3. The method according to claim 1, wherein the first-conductivity-type-doped region is provided at a periphery of the second-conductivity-type-doped region so as to surround the second-conductivity-type-doped region in a plane.
4. The method of claim 1, wherein the isolation region and the first conductivity type well region are formed in a same doping process.
5. The method of claim 4, wherein step A comprises:
obtaining a substrate;
doping the substrate to form the first conductive type well region;
and doping the substrate to form the first conductive type doped region and the second conductive type doped region respectively, wherein the first conductive type well region between the first conductive type doped region and the second conductive type doped region is used as the isolation region.
6. The method of claim 1, wherein the first conductivity type well region has an implantation depth that is 1-2 μm deeper than the implantation depths of the first and second conductivity type doped regions.
7. The method of claim 1, wherein the electrical parameters tested in step B include reverse voltage and junction capacitance.
8. The method of claim 1, wherein the doping concentrations of the first-conductivity-type-doped region and the second-conductivity-type-doped region are the same.
9. The method of claim 1, wherein the first and second conductivity-type doped regions are implanted to the same depth.
10. The method according to any of claims 1-9, wherein the first conductivity type is N-type and the second conductivity type is P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910003281.9A CN111403305A (en) | 2019-01-03 | 2019-01-03 | Method for testing electrical parameters of diode in semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910003281.9A CN111403305A (en) | 2019-01-03 | 2019-01-03 | Method for testing electrical parameters of diode in semiconductor structure |
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| Publication Number | Publication Date |
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| CN111403305A true CN111403305A (en) | 2020-07-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910003281.9A Withdrawn CN111403305A (en) | 2019-01-03 | 2019-01-03 | Method for testing electrical parameters of diode in semiconductor structure |
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- 2019-01-03 CN CN201910003281.9A patent/CN111403305A/en not_active Withdrawn
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Application publication date: 20200710 |