CN111385028A - Automatic bias control system and method for bipolar orthogonal Mach-Zehnder modulator - Google Patents
Automatic bias control system and method for bipolar orthogonal Mach-Zehnder modulator Download PDFInfo
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Abstract
The invention relates to the technical field of optical communication, and particularly discloses an automatic bias control system and method of a bipolar quadrature Mach-Zehnder modulator, which superposes two low-frequency alternating current signals on a bias voltage input end of a DP-IQMm modulator, periodically samples sum frequency or difference frequency signal components of the two superposed alternating current signals contained in output light of the DP-IQMm modulator at an optical output end of the DP-IQMm modulator through a photoelectric conversion and digital sampling circuit and feeds back the sum frequency or difference frequency signal components to a controller, the controller calculates the real-time bias state of the DP-IQMm modulator, searches for the optimal working point of each path of bias voltage of the DP-IQMm modulator, controls the bias voltage of the DP-IQMm modulator through a group of digital-to-analog converters and driving circuits, can complete the optimal bias point search of the DP-IQMm modulator within a few seconds without being influenced by factors such as device noise, modulation format and the like, and the bias voltage of the DP-IQMm modulator can be always kept at the optimal working point.
Description
Technical Field
The invention relates to the technical field of optical communication, in particular to a Dual-Polarization Quadrature Modulator (I & Q) Mach-Zehnder Modulator (DP-IQMm) Automatic Bias Control (ABC) system and method.
Background
Theory and experiments of coherent optical communication began in the 80's of the last century. Since coherent optical communication systems are known to have the advantage of high sensitivity, a great deal of research work has been done in various countries on coherent optical transmission techniques. In recent years, high-order modulation schemes such as 112G/s-DQPSK and 224G/s-DP16QAM have begun to be put into practical use.
The optical modulator is a key device in the aspects of optical fiber communication, microwave photonic technology and the like, and the performance of the whole system is directly determined by the quality of the characteristics of the optical modulator. However, the optical modulator is easily affected by environmental factors such as temperature and pressure in practical use, which causes the static operating point to drift, affects the quality and stability of the optical modulation signal, and degrades the error performance of the transmission system.
Mach-Zehnder electro-optic external modulators (MZM: Mach-Zehnder modulators) are important components in modern optical communication technology and are widely used in various optical technologies. With the continuous development of optical fiber communication technology, the service demand is gradually increased and communication means are more and more diversified, which puts a severe demand on the performance of the optical fiber communication system. To ensure stable optical signal quality and improve the performance of the optical transmission system, each bias voltage on the DP-IQMZM modulator needs to be monitored and controlled so that the modulator bias is maintained at the optimum operating point for a long time.
Only a small number of documents mention methods for DP-IQMZM modulator Automatic Bias Control (ABC), essentially in the form of power detection or first order detection. In practical application, it is found that these control modes are easily affected by factors such as device Noise and modulation format, and the bias voltage drift and Optical Signal to Noise Ratio (OSNR) are deteriorated.
Disclosure of Invention
The invention aims to provide an automatic bias control system and method of a bipolar quadrature Mach-Zehnder modulator, which can quickly complete the optimal bias point search of the DP-IQMz modulator and keep the optimal operating point for a long time.
To achieve the above object, the present invention provides an automatic bias control system for a bipolar orthogonal mach-zehnder modulator, comprising: the device comprises a controller, a digital-to-analog conversion and driving circuit, a DP-IQMZM modulator and a photoelectric conversion and digital sampling circuit which are electrically connected in sequence, wherein one end of the photoelectric conversion and digital sampling circuit is electrically connected with the controller; the controller outputs a group of direct current bias signals and two paths of low-frequency alternating current signals to each bias pin of the DP-IQMZM modulator according to needs, the photoelectric conversion and digital sampling circuit periodically samples sum frequency or difference frequency signal components of superposed alternating current signals contained in output light of the DP-IQMZM modulator and feeds the sum frequency or difference frequency signal components back to the controller, the controller calculates the current bias state of the DP-IQMZM modulator, the optimal working point of each path of bias voltage of the DP-IQMZM modulator is searched, and the DP-IQMZM modulator is controlled through a group of digital-to-analog conversion and driving circuits.
The output end of the DP-IQMm modulator is electrically connected with the photoelectric conversion and digital sampling circuit through an optical power coupler, the optical power coupler separates the signal from the DP-IQMm modulator into two paths of optical signals, one path of optical signals is directly output, and the other path of optical signals is transmitted to the photoelectric conversion and digital sampling circuit.
Specifically, the controller comprises a control state machine, a synchronous detector and an alternating current signal generator, wherein the synchronous detector and the alternating current signal generator are electrically connected with the control state machine respectively; one end of the control state machine is electrically connected with the digital-to-analog conversion and drive circuit, and one end of the synchronous detector is electrically connected with the photoelectric conversion and digital sampling circuit.
Furthermore, the invention also provides an automatic bias control method of the bipolar orthogonal Mach-Zehnder modulator, the controller outputs a group of direct current bias signals and two paths of low-frequency alternating current signals to each bias pin of the DP-IQMZM modulator according to the requirement, the AC signal component contained in the output light of the DP-IQMm modulator is periodically sampled by an opto-electronic conversion and digital sampling circuit, and detects the sum frequency or difference frequency signal components of two low-frequency alternating current signals superposed on the bias pin of the DP-IQMZM modulator through a synchronous detection algorithm and feeds back the sum frequency or difference frequency signal components to the controller, the controller calculates the current bias state of the DP-IQMZM modulator, searches the optimal working point of each path of bias voltage of the DP-IQMZM modulator, each bias pin of the DP-IQMm modulator is controlled by a set of digital-to-analog conversion and driving circuits, so that the DP-IQMZM modulator bias voltage is always maintained at the optimum operating point.
The controller comprises a control state machine, a synchronous detector and an alternating current signal generator;
in particular, the alternating current signal generator is used for generating two low-frequency alternating current signals AC1And AC2The alternating current signal AC1And AC2The output values of (a) are:
AC1(n)＝Vπ*0.02*cos(2*n*f1*n*T)
AC2(n)＝Vπ*0.02*cos(2*π*f2*n*T)
in which n is a sequence of integers, VπFor the half-wave bias voltage of the DP-IQMm modulator, f1 and f2 represent the AC signal AC1、AC2T represents the refresh period of the digital-to-analog conversion and drive circuit;
the synchronous detector carries out synchronous detection on signals from the photoelectric conversion and digital sampling circuit, and the calculation method of the synchronous detector is as follows:
wherein S is a synchronous detection result, N is an integer sequence, T represents a sampling period of the photoelectric conversion and digital sampling circuit, ADC (N) is an output value of the photoelectric conversion and digital sampling circuit at a time N x T, f3 is equal to the sum of frequencies of f1 and f2, N represents the sampling times required by one-time synchronous detection, and theta is a phase difference between an input signal of the synchronous detector and an alternating current signal generator;
and the control state machine calculates a new DP-IQMm modulator bias voltage according to the self state, the current bias voltage, the output value of the alternating current signal generator and the output value of the synchronous detector, outputs the new DP-IQMm modulator bias voltage to the digital-to-analog conversion and driving circuit, and further controls the DP-IQMm modulator.
Specifically, the control of the DP-IQMZM modulator by the control state machine comprises the steps of:
step a, setting each path of bias voltage direct current component XIDC,XQDC,XPDC,YIDC,YQDC,YPDCIs zero;
b, searching the optimal working point of each path of bias voltage of the X channel;
step c, searching the optimal working point of each path of bias voltage of the Y channel;
d, tracking each path of offset optimal working point of the X channel;
step e, tracking each path of bias optimal working point of the Y channel;
and f, repeating the step d and the step e, so that the bias voltage of the DP-IQMZM modulator is always kept at the optimal working point.
Wherein the step b comprises:
step b 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the Y-channel bias voltage as YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step b 2: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)-M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 3: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)+M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 4: modifying XI according to synchronous detection results S1, S2DCValue, XI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 5: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)-M
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 6: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)+M
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 7: modifying XQ based on synchronous detection results S1, S2DCValue, if ABS (S1) ≧ ABS (S2), XQDCSubtracting M, otherwise adding M;
step b 8: dividing the one-time bias voltage modification value M by 2;
step b 9: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC-M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 10: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC+M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 11: XP is modified according to synchronous detection results S1 and S2DCValue, XP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 12: checking the magnitude of the one-time bias voltage modification value M, if it is greater than Vπ128, repeating the operation from the step b2 to the step b 12;
step b 13: according to XPDCSign adjusted XPDCValue, if XPDCNot less than 0, XPDCValue minus Vπ/4, and according to the detection result S2 of the step b10, setting the phase direction Xs of the X channel, if S2 is not less than 0, Xs is 1, if S2<0, Xs ═ 1; if XPDC< 0, XPDCValue plus Vπ/4, detecting the junction also from synchronous detectionIf S2 ≧ 0, Xs ═ 1, if S2 sets the phase direction Xs of the X channel at S2<0， Xs＝1。
The step c comprises the following steps:
step c 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the X channel bias voltage as XI ═ XIDC，XQ＝XQDC，XP＝XPDCAnd remains unchanged;
step c 2: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)-M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 3: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)+M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 4: modifying YI according to synchronous detection result S1, S2DCValue, YI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 5: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)–M
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 6: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)+M
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 7: modifying YQ according to synchronous detection results S1, S2DCValue, YQ if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 8: dividing the one-time bias voltage modification value M by 2;
step c 9: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC-M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 10: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC+M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 11: modifying YP according to synchronous detection results S1, S2DCValue, YP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 12: checking the magnitude of the one-shot bias voltage modification value if it is greater than Vπ128, repeating the operation steps c2 to c 12;
step c 13: according to YPDCSign-adjusted YPDCValue if VPDCMore than or equal to 0, YPDCValue minus Vπ/4 and setting the phase direction Ys of the Y channel according to the detection result S2 of the step c10, if S2 is not less than 0, Ys is 1, if S2<0, Ys ═ 1; if YPDC< 0, YPDCValue plus Vπ/4, the phase direction Ys of the Y channel is set based on the synchronous detection result S2, if S2 ≧ 0, YIf S is-1, if S2<0， Ys＝1。
The step d comprises the following steps:
step d 1: setting the Y-channel bias voltage output value to YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step d 2: setting XI (n) ═ XIDC+AC1(n)，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDCAfter waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 3: modifying XPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new XPDCEquals the current XPDCSubtract Xs*Vπ/256, new XP otherwiseDCEquals the current XPDCSubtracting Xs, ks, S;
step d 4: setting XI (n) ═ XIDC，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 5: modifying XIDCValue if ABS (k S) > Vπ/256, New XIDCIs equal to current XIDCSubtract XS*Vπ/128, else new XIDCIs equal to current XIDCSubtracting Xs, ks, S;
step d 6: setting XI (n) ═ XIDC+AC2(n)，XQ(n)＝XIDC，XP(n)＝XPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 7: modifying XQDCValue if ABS (k S) > Vπ/256, novel XQDCIs equal to current XIDCSubtract XS*Vπ/128, otherwise new XQDCIs equal to current XIDCXs × k × S is subtracted.
The step e comprises the following steps:
step e 1: setting X channel bias voltage as XI ═ XIDC，XQ＝XIDC，XP＝XPDCAnd also protectKeeping unchanged;
step e 2: setting YI (n) ═ YIDC+AC1(n)，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDCAfter waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step e 3: modifying YPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new YPDCIs equal to the current YPDCMinus YS*Vπ/256, otherwise new YPDCIs equal to the current YPDCSubtracting Ys k S;
step e 4: setting YI (n) ═ YIDC，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step e 5: modifying YIDCValue if ABS (k S) > Vπ/256, new YIDCIs equal to the current YIDCMinus YS*Vπ/128, else the new YIDCIs equal to the current YIDCSubtracting Ys k S;
step e 6: setting YI (n) ═ YIDC+AC2(n)，YQ(n)＝YIDC，YP(n)＝YPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step e 7: modifying YQDC value if ABS (k S) > Vπ/256, novel YQDCEqual to the current YQDCMinus YS*Vπ/128, new YQ otherwiseDCEqual to the current YQDCSubtract Ys k S.
The automatic bias control system and method of the bipolar orthogonal Mach-Zehnder modulator can complete the optimal bias point search of the DP-IQMZM modulator within a few seconds without being influenced by factors such as device noise, modulation format and the like, and can keep IQ gain imbalance (IQ-OFFSET) within-25 dB and quadrature PHASE ERROR (PHASE-ERROR) within 4 ℃ for a long time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a block diagram of an embodiment of an automatic bias control system for a bipolar quadrature mach-zehnder modulator according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides an automatic bias control system for a bipolar orthogonal mach-zehnder modulator, comprising: the device comprises a controller 1, a digital-to-analog conversion and driving circuit 2, a DP-IQMZM modulator 3 and a photoelectric conversion and digital sampling circuit 4 which are electrically connected in sequence, wherein one end of the photoelectric conversion and digital sampling circuit 4 is electrically connected with the controller 1. The controller 1 may be an MCU or an FPGA or a DPS, and all control processes are implemented in this device. The output terminal of the controller 1 is connected to the input terminal of the digital-to-analog conversion and driving circuit 2, and the output terminal of the digital-to-analog conversion and driving circuit 2 is directly electrically connected to the bias pin of the DP-IQMZM modulator 3. The digital-to-analog conversion and drive circuit 2 converts a digital quantity of the bias voltage from the controller 1 into an analog quantity, and then outputs the analog quantity after filtering amplification to the DP-IQMZM modulator 3.
Specifically, the output terminal of the DP-IQMZM modulator 3 is electrically connected to the photoelectric conversion and digital sampling circuit 4 through a TAP-Coupler (TAP) 5. The input end of the optical power coupler 5 is connected with the output end of the DP-IQMm modulator 3, and separates the signal from the DP-IQMm modulator 3 into two optical signals, one of which is directly output, and the other is transmitted to the photoelectric conversion and digital sampling circuit 4. The photoelectric conversion and digital sampling circuit 4 converts the optical signal from the optical power coupler 5 into an electrical signal, the electrical signal is amplified, filtered and subjected to analog-to-digital conversion and then fed back to the controller 1, and the controller 1 calculates the bias voltage of the DP-IQMZM modulator 3 and completes the whole control process of the control system.
In the embodiment of the present invention, the controller 1 includes a control state machine 12, a synchronous detector 14 and an ac signal generator 16, which are electrically connected to the control state machine 12; one end of the control state machine 12 is electrically connected with the digital-to-analog conversion and driving circuit 2, and one end of the synchronous detector 14 is electrically connected with the photoelectric conversion and digital sampling circuit 4. The control state machine 12 calculates new bias voltages XI, XQ, XP, YI, YQ and YP of the DP-IQMm modulator 3 according to the state of the state machine, the current bias voltage, the output value of the alternating current signal generator 16 and the output value of the synchronous detector 14, and outputs the new bias voltages XI, XQ, XP, YI, YQ and YP to the digital-to-analog conversion and driving circuit 2, so that the whole control process of the control system is completed.
Furthermore, the invention also provides an automatic bias control method of the bipolar orthogonal Mach-Zehnder modulator, the controller 1 outputs a group of direct current bias signals and two paths of low-frequency alternating current signals to each bias pin of the DP-IQMz modulator 3 according to the requirement, the alternating signal component contained in the output light of the DP-IQMZM modulator 3 is periodically sampled by an opto-electric conversion and digital sampling circuit 4, and detects the sum frequency or difference frequency signal components of two low-frequency alternating current signals superposed on the offset pins of the two low-frequency alternating current signals through a synchronous detection algorithm and feeds the sum frequency or difference frequency signal components back to the controller 1, the controller 1 calculates the current offset state of the DP-IQMm modulator 3, searches the optimal working point of each path of offset voltage of the DP-IQMm modulator 3, the bias pins of the DP-IQMZM modulator 3 are controlled by a set of digital-to-analog conversion and driving circuits 2, so that the DP-IQMZM modulator 3 bias voltage is always kept at the optimum operating point. In the embodiment of the present invention, the controller 1 includes a control state machine 12, a synchronous detector 14 and an ac signal generator 16.
In particular, the alternating current signal generator 16 is adapted to generate two low frequency alternating current signals AC1And AC2The alternating current signal AC1And AC2The output values of (a) are:
AC1(n)＝Vπ*0.02*cos(2*π*f1*n*T)
AC2(n)＝Vπ*0.02*cos(2*π*f2*n*T)
in which n is a sequence of integers, VπThe half-wave bias voltage for DP-IQMZM modulator 3 is given by the modulator manufacturer. f1 and f2 represent the frequencies of the AC signals AC1 and AC2, respectively, and T represents the refresh period of the digital-to-analog conversion and driving circuit 2. As a specific embodiment of the present invention, f1 ≠ f2, where f1 ═ 3KHz, f2 ≠ 4KHz, and T ═ 0.5us can be set.
The synchronous detector 14 performs synchronous detection of the signal from the photoelectric conversion and digital sampling circuit 4, and the calculation method of the synchronous detector is as follows:
where S is the synchronous detection result, n is the integer sequence, T represents the sampling period of the photoelectric conversion and digital sampling circuit 4, adc (n) is the output value of the photoelectric conversion and digital sampling circuit 4 at time n × T, and f3 is equal to the sum of the frequencies of f1 and f 2. In an embodiment of the present invention, f1 may be 3KHz, f2 may be 4KHz, so f3 may be 7KHz, and T may be 0.5us, which is the same as the refresh period of the digital-to-analog conversion and driving circuit 2. N represents the number of samples required for a synchronous detection, where N is 32 (1/(f2-f1)) (1/T) is 6400. θ is the phase difference between the synchronous detector input signal and the ac signal generator, which can be calculated by the circuit or obtained in actual measurement.
The control state machine 12 calculates a new bias voltage of the DP-IQMZM modulator 3 according to its own state, the current bias voltage, the output value of the ac signal generator 16, and the output value of the synchronous detector 14, and outputs the new bias voltage to the digital-to-analog conversion and driving circuit, thereby controlling the DP-IQMZM modulator.
Specifically, the control state machine 12 includes the following variables: the synchronous detector 14 outputs a value S; the output value AC1, AC of the AC signal generator 162; a bias voltage modification value M; DC component XI of X-channel bias voltageDC、XIDC、XPDC(ii) a Y-channel bias voltage DC component YIDC、YIDC、YPDC(ii) a The phase direction Xs of the X channel; the phase direction Ys of the Y channel; x channel bias voltage output values XI, XQ and XP; y channel bias voltage output values YI, YQ and YP;
specifically, the control of DP-IQMZM modulator 3 by control state machine 12 comprises the steps of:
step a, setting each path of bias voltage direct current component XIDC,XQDC,XPDC,YIDC,YQDC,YPDCIs zero;
b, searching the optimal working point of each path of bias voltage of the X channel;
step c, searching the optimal working point of each path of bias voltage of the Y channel;
d, tracking each path of offset optimal working point of the X channel;
step e, tracking each path of bias optimal working point of the Y channel;
and f, repeating the step d and the step e, so that the bias voltage of the DP-IQMZM modulator is always kept at the optimal working point.
As a specific embodiment of the present invention, the step b includes:
step b 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the Y-channel bias voltage as YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step b 2: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)-M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for a while, the synchronous detection result is recorded and assigned to S1. In particular embodiments of the present invention, the wait time may be set to 10ms, or other times.
Step b 3: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)+M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step b 4: modifying XI according to synchronous detection results S1, S2DCValue, XI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 5: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)-M
XP(n)＝XPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S1;
step b 6: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)+M
XP(n)＝XPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step b 7: modifying XQ based on synchronous detection results S1, S2DCValue, if ABS (S1) ≧ ABS (S2), XQDCSubtracting M, otherwise adding M;
step b 8: dividing the one-time bias voltage modification value M by 2;
step b 9: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC-M
After waiting for 10ms, recording the synchronous detection result and assigning a value to S1;
step b 10: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC+M
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step b 11: XP is modified according to synchronous detection results S1 and S2DCValue, XP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 12: checking the magnitude of the one-time bias voltage modification value M if it is greater than Vπ128, repeating the operation from the step b2 to the step b 12;
step b 13: according to XPDCSign adjusted XPDCValue, if XPDCNot less than 0, XPDCValue minus Vπ/4, and according to the detection result S2 of the step b10, setting the phase direction Xs of the X channel, if S2 is not less than 0, Xs is 1, if S2<0, Xs ═ 1; if XPDC< 0, XPDCValue plus VπAnd/4, similarly setting the phase direction Xs of the X channel according to the synchronous detection result S2, if S2 is more than or equal to 0, the Xs is equal to-1, and if S2<0， Xs＝1。
The step c comprises the following steps:
step c 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the X channel bias voltage as XI ═ XIDC，XQ＝XQDC，XP＝XPDCAnd remains unchanged;
step c 2: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)-M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S1;
step c 3: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)+M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step c 4: modifying YI according to synchronous detection result S1, S2DCValue, YI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 5: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)–M
YP(n)＝YPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S1;
step c 6: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)+M
YP(n)＝YPDC
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step c 7: modifying YQ according to synchronous detection results S1, S2DCValue, YQ if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 8: dividing the one-time bias voltage modification value M by 2M;
step c 9: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC-M
After waiting for 10ms, recording the synchronous detection result and assigning a value to S1;
step c 10: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC+M
After waiting for 10ms, recording the synchronous detection result and assigning a value to S2;
step c 11: modifying YP according to synchronous detection results S1, S2DCValue, YP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 12: checking the magnitude of the one-shot bias voltage modification value if it is greater than Vπ128, repeating the operation steps c2 to c 12;
step c 13: according to YPDCSign-adjusted YPDCValue if YPDCMore than or equal to 0, YPDCValue minus Vπ/4 and setting the phase direction Ys of the Y channel according to the detection result S2 of the step c10, if S2 is not less than 0, Ys is 1, if S2<0, Ys ═ 1; if YPDC< 0, YPDCValue plus VπAnd/4, setting the phase direction Ys of the Y channel according to the synchronous detection result S2, if S2 is more than or equal to 0, Ys is equal to-1, and if S2<0，Ys＝1。
The step d comprises the following steps:
step d 1: setting the Y-channel bias voltage output value to YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step d 2: setting XI (n) ═ XIDC+AC1(n)，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDCAfter waiting for 10ms, recording a synchronous detection result and assigning the result to S;
step d 3: modifying XPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new XPDCEquals the current XPDCSubtract XS*Vπ/256, new XP otherwiseDCEquals the current XPDCSubtracting Xs, ks, S;
step d 4: setting XI (n) ═ XIDC，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDC+AC1(n), after waiting for 10ms, recording the sameStep-detecting the detection result and assigning the detection result to S;
step d 5: modifying XIDCValue if ABS (k S) > Vπ/256, New XIDCIs equal to current XIDCSubtract XS*Vπ/128, else new XIDCIs equal to current XIDCSubtracting Xs, ks, S;
step d 6: setting XI (n) ═ XIDC+AC2(n)，XQ(n)＝XIDC，XP(n)＝XPDC+AC1(n), after waiting for 10ms, recording a synchronous detection result and assigning the synchronous detection result to S;
step d 7: modifying XQDCValue if ABS (k S) > Vπ/256, novel XQDCIs equal to current XIDCSubtract XS*Vπ/128, otherwise new XQDCIs equal to current XIDCXs × k × S is subtracted.
The step e comprises the following steps:
step e 1: setting X channel bias voltage as XI ═ XIDC，XQ＝XIDC，XP＝XPDCAnd remains unchanged;
step e 2: setting YI (n) ═ YIDC+AC1(n)，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDCAfter waiting for 10ms, recording a synchronous detection result and assigning the result to S;
step e 3: modifying YPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new YPDCIs equal to the current YPDCMinus YS*Vπ/256, otherwise new YPDCIs equal to the current YPDCSubtracting Ys k S;
step e 4: setting YI (n) ═ YIDC，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDC+AC1(n), after waiting for 10ms, recording a synchronous detection result and assigning the synchronous detection result to S;
step e 5: modifying YIDCValue if ABS (k S) > Vπ/256, new YIDCIs equal to the current YIDCMinus YS*Vπ/128, else the new YIDCIs equal to the current YIDCSubtracting Ys k S;
step e 6: setting YI (n) ═ YIDC+AC2(n)，YQ(n)＝YIDC，YP(n)＝YPDC+AC1(n), after waiting for 10ms, recording a synchronous detection result and assigning the synchronous detection result to S;
step e 7: modifying YQDC value if ABS (k S) > Vπ/256, novel YQDCEqual to the current YQDCMinus YS*Vπ/128, new YQ otherwiseDCEqual to the current YQDCSubtract Ys k S.
In summary, the present invention provides an automatic bias control system and method for a bipolar quadrature mach-zehnder modulator, which can complete the optimum bias point search of a DP-IQMZM modulator within several seconds without being affected by factors such as device noise and modulation format, and can maintain IQ gain imbalance (IQ-OFFSET) within-25 dB and quadrature PHASE ERROR (PHASE-ERROR) within 4 ℃ for a long time.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The automatic bias control system of the bipolar orthogonal Mach-Zehnder modulator is characterized by comprising a controller, a digital-to-analog conversion and driving circuit, a DP-IQMZM modulator and a photoelectric conversion and digital sampling circuit which are electrically connected in sequence, wherein one end of the photoelectric conversion and digital sampling circuit is electrically connected with the controller; the controller outputs a group of direct current bias signals and two paths of low-frequency alternating current signals to each bias pin of the DP-IQMZM modulator according to needs, the photoelectric conversion and digital sampling circuit periodically samples sum frequency or difference frequency signal components of superposed alternating current signals contained in output light of the DP-IQMZM modulator and feeds the sum frequency or difference frequency signal components back to the controller, the controller calculates the current bias state of the DP-IQMZM modulator, the optimal working point of each path of bias voltage of the DP-IQMZM modulator is searched, and the DP-IQMZM modulator is controlled through a group of digital-to-analog conversion and driving circuits.
2. The system of claim 1, wherein the output of the DP-IQMZM modulator is electrically connected to the optical-to-electrical conversion and digital sampling circuit through an optical power coupler, the optical power coupler splits the signal from the DP-IQMZM modulator into two optical signals, one of which is directly output and the other of which is transmitted to the optical-to-electrical conversion and digital sampling circuit.
3. The automatic bias control system of a bipolar orthogonal mach-zehnder modulator of claim 1, wherein the controller includes therein a control state machine, a synchronous detector and an alternating current signal generator electrically connected to the control state machine, respectively; one end of the control state machine is electrically connected with the digital-to-analog conversion and drive circuit, and one end of the synchronous detector is electrically connected with the photoelectric conversion and digital sampling circuit.
4. An automatic bias control method of a bipolar orthogonal Mach-Zehnder modulator is characterized in that a controller outputs a group of direct current bias signals and two paths of low-frequency alternating current signals to each bias pin of a DP-IQMZM modulator according to requirements, the AC signal component contained in the output light of the DP-IQMm modulator is periodically sampled by an opto-electronic conversion and digital sampling circuit, and detects the sum frequency or difference frequency signal components of two low-frequency alternating current signals superposed on the bias pin of the DP-IQMZM modulator through a synchronous detection algorithm and feeds back the sum frequency or difference frequency signal components to the controller, the controller calculates the current bias state of the DP-IQMZM modulator, searches the optimal working point of each path of bias voltage of the DP-IQMZM modulator, each bias pin of the DP-IQMm modulator is controlled by a set of digital-to-analog conversion and driving circuits, so that the DP-IQMZM modulator bias voltage is always maintained at the optimum operating point.
5. The method for automatic bias control of a bipolar orthogonal mach-zehnder modulator as defined in claim 4 wherein the controller includes therein a control state machine, a synchronous detector and an ac signal generator;
the alternating current signal generator is used for generating two low-frequency alternating current signals AC1And AC2The alternating current signal AC1And AC2The output values of (a) are:
AC1(n)＝Vπ*0·02*cos(2*π*f1*n*T)
AC2(n)＝Vπ*0.02*cos(2*π*f2*n*T)
in which n is a sequence of integers, VπFor the half-wave bias voltage of the DP-IQMm modulator, f1 and f2 represent the AC signal AC1、AC2T represents the refresh period of the digital-to-analog conversion and drive circuit;
the synchronous detector carries out synchronous detection on signals from the photoelectric conversion and digital sampling circuit, and the calculation method of the synchronous detector is as follows:
wherein S is a synchronous detection result, N is an integer sequence, T represents a sampling period of the photoelectric conversion and digital sampling circuit, ADC (N) is an output value of the photoelectric conversion and digital sampling circuit at a time N x T, f3 is equal to the sum of frequencies of f1 and f2, N represents the sampling times required by one-time synchronous detection, and theta is a phase difference between an input signal of the synchronous detector and an alternating current signal generator;
and the control state machine calculates a new DP-IQMm modulator bias voltage according to the self state, the current bias voltage, the output value of the alternating current signal generator and the output value of the synchronous detector, outputs the new DP-IQMm modulator bias voltage to the digital-to-analog conversion and driving circuit, and further controls the DP-IQMm modulator.
6. The method of automatic bias control for a bipolar quadrature mach-zehnder modulator of claim 5 wherein the controlling of the DP-IQMZM modulator by the control state machine comprises the steps of:
step a, setting each path of bias voltage direct current component XIDC,XQDC,XPDC,YIDC,YQDC,YPDCIs zero;
b, searching the optimal working point of each path of bias voltage of the X channel;
step c, searching the optimal working point of each path of bias voltage of the Y channel;
d, tracking each path of offset optimal working point of the X channel;
step e, tracking each path of bias optimal working point of the Y channel;
and f, repeating the step d and the step e, so that the bias voltage of the DP-IQMZM modulator is always kept at the optimal working point.
7. The method for automatic bias control of a bipolar orthogonal mach-zehnder modulator of claim 6, wherein step b comprises:
step b 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the Y-channel bias voltage as YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step b 2: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)-M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 3: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)+M
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 4: modifying XI according to synchronous detection results S1, S2DCValue, XI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 5: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)-M
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 6: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)+M
XP(n)＝XPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 7: modifying XQ based on synchronous detection results S1, S2DCValue, if ABS (S1) ≧ ABS (S2), XQDCSubtracting M, otherwise adding M;
step b 8: dividing the one-time bias voltage modification value M by 2;
step b 9: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC-M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step b 10: setting each bias voltage output value of X channel as
XI(n)＝XIDC+AC1(n)
XQ(n)＝XIDC+AC2(n)
XP(n)＝XPDC+M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step b 11: XP is modified according to synchronous detection results S1 and S2DCValue, XP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step b 12: checking the magnitude of the one-time bias voltage modification value M if it is greater than Vπ128, repeat operationStep b2 to step b 12;
step b 13: according to XPDCSign adjusted XPDCValue, if XPDCNot less than 0, XPDCValue minus Vπ/4, and according to the detection result S2 of the step b10, setting the phase direction Xs of the X channel, if S2 is not less than 0, Xs is 1, if S2<0, Xs ═ 1; if XPDC< 0, XPDCValue plus VπAnd/4, similarly setting the phase direction Xs of the X channel according to the synchronous detection result S2, if S2 is more than or equal to 0, the Xs is equal to-1, and if S2<0，Xs＝1。
8. The method for automatic bias control of a bipolar orthogonal mach-zehnder modulator of claim 7 wherein step c comprises:
step c 1: setting the one-time bias voltage modification value M-VπAnd/2, setting the output value of the X channel bias voltage as XI ═ XIDC，XQ＝XQDC，XP＝XPDCAnd remains unchanged;
step c 2: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)-M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 3: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)+M
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 4: modifying YI according to synchronous detection result S1, S2DCValue, YI if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 5: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)–M
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 6: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)+M
YP(n)＝YPDC
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 7: modifying YQ according to synchronous detection results S1, S2DCValue, YQ if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 8: dividing the one-time bias voltage modification value M by 2;
step c 9: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC-M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S1;
step c 10: setting each bias voltage output value of Y channel as
YI(n)＝YIDC+AC1(n)
YQ(n)＝YIDC+AC2(n)
YP(n)＝YPDC+M
After waiting for a period of time, recording the synchronous detection result and assigning the synchronous detection result to S2;
step c 11: modifying YP according to synchronous detection results S1, S2DCValue, YP if ABS (S1) ≧ ABS (S2)DCSubtracting M, otherwise adding M;
step c 12: checking the magnitude of the one-shot bias voltage modification value if it is greater than Vπ128, repeating the operation steps c2 to c 12;
step c 13: according to YPDCSign-adjusted YPDCValue if YPDCMore than or equal to 0, YPDCValue minus Vπ/4 and setting the phase direction Ys of the Y channel according to the detection result S2 of the step c10, if S2 is not less than 0, Ys is 1, if S2<0, Ys ═ 1; if YPDC< 0, YPDCValue plus VπAnd/4, setting the phase direction Ys of the Y channel according to the synchronous detection result S2, if S2 is more than or equal to 0, Ys is equal to-1, and if S2<0，Ys＝1。
9. The method for automatic bias control of a bipolar orthogonal mach-zehnder modulator of claim 8, wherein step d comprises:
step d 1: setting the Y-channel bias voltage output value to YI ═ YIDC，YQ＝YQDC，YP＝YPDCAnd remains unchanged;
step d 2: setting XI (n) ═ XIDC+AC1(n)，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDCAfter waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 3: modifying XPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new XPDCEquals the current XPDCSubtract Xs*Vπ/256, new XP otherwiseDCEquals the current XPDCSubtracting Xs, ks, S;
step d 4: setting XI (n) ═ XIDC，XQ(n)＝XIDC+AC2(n)，XP(n)＝XPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 5: modifying XIDCValue if ABS (k S) > Vπ/256, New XIDCIs equal to current XIDCSubtract XS*Vπ/128, else new XIDCIs equal to current XIDCSubtracting Xs, ks, S;
step d 6: setting XI (n) ═ XIDC+AC2(n)，XQ(n)＝XIDC，XP(n)＝XPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step d 7: modifying XQDCValue if ABS (k S) > Vπ/256, novel XQDCIs equal to current XIDCSubtract XS*Vπ/128, otherwise new XQDCIs equal to current XIDCXs × k × S is subtracted.
10. The method for automatic bias control of a bipolar quadrature mach-zehnder modulator of claim 9, wherein step e comprises:
step e 1: setting X channel bias voltage as XI ═ XIDC，XQ＝XIDC，XP＝XPDCAnd remains unchanged;
step e 2: setting YI (n) ═ YIDC+AC1(n)，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDCAfter waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step e 3: modifying YPDCValue if ABS (k S) > Vπ/256 (where K is a proportionality constant, and the specific value is determined by experiment), new YPDCIs equal to the current YPDCMinus YS*Vπ/256, otherwise new YPDCIs equal to the current YPDCSubtracting Ys k S;
step e 4: setting YI (n) ═ YIDC，YQ(n)＝YIDC+AC2(n)，YP(n)＝YPDC+AC1(n), after waiting for a period of time, recording the synchronous detection result and assigning a value to S;
step e 5: modifying YIDCValue if ABS (k S) > Vπ/256, new YIDCIs equal to the current YIDCMinus YS*Vπ/128, else the new YIDCIs equal to the current YIDCSubtracting Ys k S;
step e 6: setting YI (n) ═ YIDC+AC2(n)，YQ(n)＝YIDC，YP(n)＝YPDC+AC1(n), waitAfter a period of time, recording the synchronous detection result and assigning the result to S;
step e 7: modifying YQDC value if ABS (k S) > Vπ/256, novel YQDCEqual to the current YQDCMinus YS*Vπ/128, new YQ otherwiseDCEqual to the current YQDCSubtract Ys k S.
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